From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 55E68C433EF for ; Thu, 9 Jun 2022 12:01:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234615AbiFIMB4 (ORCPT ); Thu, 9 Jun 2022 08:01:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56808 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229851AbiFIMBy (ORCPT ); Thu, 9 Jun 2022 08:01:54 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9BD1415A32 for ; Thu, 9 Jun 2022 05:01:53 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 386F360DE6 for ; Thu, 9 Jun 2022 12:01:53 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 94140C34114; Thu, 9 Jun 2022 12:01:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1654776112; bh=u+XcfQReiKtxDuoUpBEx6UyrLDzkBQyxvH5fW+kzcYo=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=pcSP3/VTTdmDQELmxtlbXoFgmKAGwZcf+V0kLp95iAtBY+KZ9iVAHlfKwm1Io07vp oiF0uIcToS/EpdF9ONCzdQdThqURJoBZYbsdIOevwxgANCYfnyN/rPcmGh5rKY5J7y W9moHY103jFeCYAJQePsbVVdJUi0pwaxZ7cN+w8dvHPV5f6ZJ07sGlLeOPkEN6efXL +vf7IXT5XCaVzcKilP8BdmGt53BLNgW16jalCSZRdUJV/xO0g2ei65VP6eEkrW6HVN 2UmEyqkIPIiVv/QgRlYNsNGJxIrd+r57VQzigtaYmwjKQj7jZavHuTT7LHiqUowNK9 WI60p8fHdRQaQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1nzGrG-00GrMO-6i; Thu, 09 Jun 2022 13:01:50 +0100 Date: Thu, 09 Jun 2022 13:01:49 +0100 Message-ID: <87a6am3v0y.wl-maz@kernel.org> From: Marc Zyngier To: Jiaxun Yang Cc: Huacai Chen , Thomas Gleixner , linux-kernel@vger.kernel.org, Xuefeng Li , Huacai Chen , Jianmin Lv Subject: Re: [PATCH V11 00/10] irqchip: Add LoongArch-related irqchip drivers In-Reply-To: References: <20220430085344.3127346-1-chenhuacai@loongson.cn> <87v8uk6kfa.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: jiaxun.yang@flygoat.com, chenhuacai@loongson.cn, tglx@linutronix.de, linux-kernel@vger.kernel.org, lixuefeng@loongson.cn, chenhuacai@gmail.com, lvjianmin@loongson.cn X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org + Jianmin Lv On Fri, 20 May 2022 16:04:28 +0100, Jiaxun Yang wrote: >=20 >=20 >=20 > =E5=9C=A8 2022/5/5 16:58, Marc Zyngier =E5=86=99=E9=81=93: > >> LoongArch use ACPI, but ACPI tables cannot describe the hierarchy of > >> irqchips, so we initilize the irqchip subsystem in this way (from arch > >> code): > >>=20 > >> cpu_domain =3D loongarch_cpu_irq_init(); > >> liointc_domain =3D liointc_acpi_init(cpu_domain, acpi_liointc); > >> eiointc_domain =3D eiointc_acpi_init(cpu_domain, acpi_eiointc); > >> pch_pic_domain =3D pch_pic_acpi_init(eiointc_domain, acpi_pchpic); > >> pch_msi_domain =3D pch_msi_acpi_init(eiointc_domain, acpi_pchmsi); > > I said no to this in the past, and I'm going to reiterate: this is > > *not* acceptable. This obviously doesn't scale and isn't manageable in > > the long run. Hardcoding the topology and the probing order in the > > kernel code has repeatedly proved to be a disaster, and yet you refuse > > to take any input from past experience. This is pretty worrying. > Just my two cents here. >=20 > Those drivers have such a topology just because this was my design to > handle irqchip differences between RS780E and LS7A for MIPS-era Loongson. >=20 > TBH, for LoongArch-era Loongson, they should be handled by the same drive= r, > cuz the topology behind them just looks like GIC PPI SPI and MSI for > Arm GIC. >=20 > PCH PIC and eiointc in combination relays interrupts from > peripherals just like SPI. liointc is doing the PPI job. They are > not separated modules in hardware, they are interlocked. That was my impression too, but I keep getting pushback on that. I wouldn't mind leaving the existing drivers for MIPS only and get new ones for Loongson if that made things clearer. > The system should be treated as a whole, pretty much like how we see > Arm's GIC. The topology will last forever for every ACPI enabled > LoongArch PC. >=20 > I see no reason they should be described separately. Adding complicities = to > ACPI bindings brings no benefit. Changing ACPI binding which is already in > final draft stage can only leave us with chaos. OK. So how do we move forward? You seem to have a good grasp on how this should be structured, so can you work with Jianmin Lv to make some progress on this? Thanks, M. --=20 Without deviation from the norm, progress is not possible.