From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AF3C1C33CB3 for ; Wed, 15 Jan 2020 23:05:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8DF7F2187F for ; Wed, 15 Jan 2020 23:05:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730700AbgAOXFr (ORCPT ); Wed, 15 Jan 2020 18:05:47 -0500 Received: from Galois.linutronix.de ([193.142.43.55]:49497 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726513AbgAOXFr (ORCPT ); Wed, 15 Jan 2020 18:05:47 -0500 Received: from p5b06da22.dip0.t-ipconnect.de ([91.6.218.34] helo=nanos.tec.linutronix.de) by Galois.linutronix.de with esmtpsa (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1irrjG-0002zJ-VA; Thu, 16 Jan 2020 00:05:39 +0100 Received: by nanos.tec.linutronix.de (Postfix, from userid 1000) id 13D65100C1B; Thu, 16 Jan 2020 00:05:38 +0100 (CET) From: Thomas Gleixner To: Kar Hin Ong , Bjorn Helgaas Cc: linux-rt-users , LKML , x86@kernel.org, "linux-pci\@vger.kernel.org" , "H. Peter Anvin" , Dave Hansen , Julia Cartwright , Keng Soon Cheah Subject: RE: Re: "oneshot" interrupt causes another interrupt to be fired erroneously in Haswell system In-Reply-To: References: <20191031230532.GA170712@google.com> Date: Thu, 16 Jan 2020 00:05:38 +0100 Message-ID: <87a76oxqv1.fsf@nanos.tec.linutronix.de> MIME-Version: 1.0 Content-Type: text/plain X-Linutronix-Spam-Score: -1.0 X-Linutronix-Spam-Level: - X-Linutronix-Spam-Status: No , -1.0 points, 5.0 required, ALL_TRUSTED=-1,SHORTCIRCUIT=-0.0001 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Kar Hin Ong writes: >> > > From Intel Xeon Processor E5/E7 v3 Product Family External Design >> > > Specification (EDS), Volume One: Architecture, section 13.1 (Legacy >> > > PCI Interrupt Handling), it mention: "If the I/OxAPIC entry is >> > > masked (via the 'mask' bit in the corresponding Redirection Table >> > > Entry), then the corresponding PCI Express interrupt(s) is forwarded >> > > to the legacy PCH" >> >> Oh well. Really useful behaviour - NOT! Second thoughts on this. This behaviour is intentional to make PCI interrupts work even when the IOAPIC is not initialized at all. I don't have access to the document you mentioned, but I know that chipsets have a knob to control that behaviour. Just checked a few chipset docs and they contain the same sentence, but then in the next paragraph they say: "If the I/OxAPIC entry is masked (via the mask bit in the corresponding Redirection Table Entry), then the corresponding PCI Express interrupt(s) is forwarded to the legacy ICH, provided the Disable PCI INTx Routing to ICH bit is clear, Section 19.10.2.27, QPIPINTRC: Intel QuickPath Interconnect Protocol Interrupt Control." That control bit is 0 after reset, so the legacy forwarding works. Another way to avoid this is to use MSI interrupts instead of the legacy PCI ones, which is recommended for various reasons (including performance) anyway. Can you please provide the exact CPU and PCH types and the output of 'lspci -vvv'? Thanks, tglx