From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BAA48C433B4 for ; Mon, 26 Apr 2021 18:04:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8B103613BC for ; Mon, 26 Apr 2021 18:04:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234328AbhDZSFU (ORCPT ); Mon, 26 Apr 2021 14:05:20 -0400 Received: from mga06.intel.com ([134.134.136.31]:20705 "EHLO mga06.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234427AbhDZSDj (ORCPT ); Mon, 26 Apr 2021 14:03:39 -0400 IronPort-SDR: 7GdcOe91OWgJj46HQNoBL+ZCWykeWxOBKytDKREnM+ix1csSNwtiasU8AucWB35RWg8Kd5s0Qh 17Zdbw3f9anA== X-IronPort-AV: E=McAfee;i="6200,9189,9966"; a="257683615" X-IronPort-AV: E=Sophos;i="5.82,252,1613462400"; d="scan'208";a="257683615" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2021 11:02:56 -0700 IronPort-SDR: NJkW7kEWNsJib9pDt/LXphHRPaBEvht2gdxL5sGWtYmxR3TfmnPfTXopDhY8n+K3x1CIk4bHOR R6UVQg9uVJDA== X-IronPort-AV: E=Sophos;i="5.82,252,1613462400"; d="scan'208";a="447353445" Received: from ssumanpx-mobl.amr.corp.intel.com (HELO skuppusw-mobl5.amr.corp.intel.com) ([10.254.34.197]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2021 11:02:55 -0700 From: Kuppuswamy Sathyanarayanan To: Peter Zijlstra , Andy Lutomirski , Dave Hansen , Dan Williams , Tony Luck Cc: Andi Kleen , Kirill Shutemov , Kuppuswamy Sathyanarayanan , Raj Ashok , Sean Christopherson , linux-kernel@vger.kernel.org, Kuppuswamy Sathyanarayanan Subject: [RFC v2 27/32] x86/tdx: Exclude Shared bit from __PHYSICAL_MASK Date: Mon, 26 Apr 2021 11:01:54 -0700 Message-Id: <87b31425b79df3cc44d2bdc6a79d6aa36c42d116.1619458733.git.sathyanarayanan.kuppuswamy@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: "Kirill A. Shutemov" tdx_shared_mask() returns the mask that has to be set in a page table entry to make page shared with VMM. Also, note that we cannot club shared mapping configuration between AMD SME and Intel TDX Guest platforms in common function. SME has to do it very early in __startup_64() as it sets the bit on all memory, except what is used for communication. TDX can postpone as we don't need any shared mapping in very early boot. Signed-off-by: Kirill A. Shutemov Reviewed-by: Andi Kleen Signed-off-by: Kuppuswamy Sathyanarayanan --- arch/x86/Kconfig | 1 + arch/x86/include/asm/tdx.h | 6 ++++++ arch/x86/kernel/tdx.c | 9 +++++++++ 3 files changed, 16 insertions(+) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 67f99bf27729..5f92e8205de2 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -882,6 +882,7 @@ config INTEL_TDX_GUEST select PARAVIRT_XL select X86_X2APIC select SECURITY_LOCKDOWN_LSM + select X86_MEM_ENCRYPT_COMMON help Provide support for running in a trusted domain on Intel processors equipped with Trusted Domain eXtenstions. TDX is an new Intel diff --git a/arch/x86/include/asm/tdx.h b/arch/x86/include/asm/tdx.h index b972c6531a53..dc80cf7f7d08 100644 --- a/arch/x86/include/asm/tdx.h +++ b/arch/x86/include/asm/tdx.h @@ -111,6 +111,8 @@ unsigned char tdg_inb(unsigned short port); unsigned short tdg_inw(unsigned short port); unsigned int tdg_inl(unsigned short port); +extern phys_addr_t tdg_shared_mask(void); + #else // !CONFIG_INTEL_TDX_GUEST static inline bool is_tdx_guest(void) @@ -149,6 +151,10 @@ static inline long tdx_kvm_hypercall4(unsigned int nr, unsigned long p1, return -ENODEV; } +static inline phys_addr_t tdg_shared_mask(void) +{ + return 0; +} #endif /* CONFIG_INTEL_TDX_GUEST */ #endif /* __ASSEMBLY__ */ #endif /* _ASM_X86_TDX_H */ diff --git a/arch/x86/kernel/tdx.c b/arch/x86/kernel/tdx.c index 1f1bb98e1d38..7e391cd7aa2b 100644 --- a/arch/x86/kernel/tdx.c +++ b/arch/x86/kernel/tdx.c @@ -76,6 +76,12 @@ bool is_tdx_guest(void) } EXPORT_SYMBOL_GPL(is_tdx_guest); +/* The highest bit of a guest physical address is the "sharing" bit */ +phys_addr_t tdg_shared_mask(void) +{ + return 1ULL << (td_info.gpa_width - 1); +} + static void tdg_get_info(void) { u64 ret; @@ -87,6 +93,9 @@ static void tdg_get_info(void) td_info.gpa_width = out.rcx & GENMASK(5, 0); td_info.attributes = out.rdx; + + /* Exclude Shared bit from the __PHYSICAL_MASK */ + physical_mask &= ~tdg_shared_mask(); } static __cpuidle void tdg_halt(void) -- 2.25.1