From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8DF94C2B9F4 for ; Sat, 19 Jun 2021 22:53:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5AA7861183 for ; Sat, 19 Jun 2021 22:53:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229901AbhFSWxr (ORCPT ); Sat, 19 Jun 2021 18:53:47 -0400 Received: from Galois.linutronix.de ([193.142.43.55]:36262 "EHLO galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229522AbhFSWxr (ORCPT ); Sat, 19 Jun 2021 18:53:47 -0400 From: Thomas Gleixner DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1624143094; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=djP8GCwU7E3FeJYesIhhi3VDXpZX+OZV3RZ8wvDxhCY=; b=B1WktvRZvmtYYmMVkUZjinpquKlqQpRdqeGfQo/QV2QFvGvEJOyC/TaPhi0O9RFmKhcKee BraDiDVOb+5qm5cvTUVaLxMWFhIk0Z1cbBKjzdMHLzNVE833btnlOAFBB1JQ5XClJS/7p+ liUbCt5dXwnsueNcYqv7WEegdrDHSk9vLN6Dp5S76X1+08OLzddAhY/llHp++I2Snk5nhu BuEiGuMH2O58XcfQ6dteHKRfZDb0k2iX8CcNS3MjmMOq9RCCuncj8X9YaLlpzCiYAlcnJ4 Ny5QO/ifqcx8DBSozUhZKrzZJMy8vJFAhHrmWNPwCdcNqC8JYnWJdUHhG1/x4w== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1624143094; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=djP8GCwU7E3FeJYesIhhi3VDXpZX+OZV3RZ8wvDxhCY=; b=ZU/tG3N9pzZkCQgemEF/gIvkrCcA1okHqsj1ASkM0i0WrkVwwEsZYEV2I1giezbLcj/t+d wwHTb07M2pB5NrBA== To: Lai Jiangshan , linux-kernel@vger.kernel.org Cc: Steven Rostedt , Lai Jiangshan , Andy Lutomirski , Ingo Molnar , Borislav Petkov , x86@kernel.org, "H. Peter Anvin" , Juergen Gross , "Peter Zijlstra \(Intel\)" , Al Viro , Arvind Sankar Subject: Re: [RFC PATCH 1/4] x86/entry/nmi: Switch to the entry stack before switching to the thread stack In-Reply-To: <20210601065217.23540-2-jiangshanlai@gmail.com> References: <20210601065217.23540-1-jiangshanlai@gmail.com> <20210601065217.23540-2-jiangshanlai@gmail.com> Date: Sun, 20 Jun 2021 00:51:34 +0200 Message-ID: <87bl81h3ih.ffs@nanos.tec.linutronix.de> MIME-Version: 1.0 Content-Type: text/plain Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Jun 01 2021 at 14:52, Lai Jiangshan wrote: > From: Lai Jiangshan > > Current kernel has no code to enforce data breakpoint not on the thread > stack. If there is any data breakpoint on the top area of the thread > stack, there might be problem. And because the kernel does not prevent data breakpoints on the thread stack we need to do more complicated things in the already horrible entry code instead of just doing the obvious and preventing data breakpoints on the thread stack? Confused. Thanks, tglx