From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.0 required=3.0 tests=BAYES_00,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 305A5C4338F for ; Wed, 18 Aug 2021 16:58:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0EE4B610A3 for ; Wed, 18 Aug 2021 16:58:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232782AbhHRQ67 (ORCPT ); Wed, 18 Aug 2021 12:58:59 -0400 Received: from mail.kernel.org ([198.145.29.99]:55008 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231402AbhHRQ66 (ORCPT ); Wed, 18 Aug 2021 12:58:58 -0400 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 9BF0F60E09; Wed, 18 Aug 2021 16:58:23 +0000 (UTC) Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mGOtR-005ntG-EA; Wed, 18 Aug 2021 17:58:21 +0100 Date: Wed, 18 Aug 2021 17:58:21 +0100 Message-ID: <87czqasn9u.wl-maz@kernel.org> From: Marc Zyngier To: Valentin Schneider Cc: Guenter Roeck , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH] irqchip/gic: Convert to handle_strict_flow_irq() In-Reply-To: <87k0kk7w0c.mognet@arm.com> References: <20210814194737.GA3951530@roeck-us.net> <87sfzb7jeo.mognet@arm.com> <87eeav19mc.wl-maz@kernel.org> <87k0kk7w0c.mognet@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: valentin.schneider@arm.com, linux@roeck-us.net, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 17 Aug 2021 01:30:43 +0100, Valentin Schneider wrote: > > On 15/08/21 07:54, Marc Zyngier wrote: > > This is going and-up in a wack-a-mole game. There is probably a bunch > > of these all over the place. I'd rather squash it at the root, > > i.e. with something like this (untested): > > > > diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c > > index 099bc7e13d1b..601ad3fc47cd 100644 > > --- a/kernel/irq/chip.c > > +++ b/kernel/irq/chip.c > > @@ -410,7 +410,12 @@ void irq_percpu_disable(struct irq_desc *desc, unsigned int cpu) > > > > void ack_irq(struct irq_desc *desc) > > { > > - desc->irq_data.chip->irq_ack(&desc->irq_data); > > + struct irq_data *data = &desc->irq_data; > > + > > + while (!data->chip->irq_ack) > > + data = data->parent_data; > > + > > + data->chip->irq_ack(&desc->irq_data); > > > > if (desc->irq_data.chip->flags & IRQCHIP_AUTOMASKS_FLOW) > > irq_state_set_flow_masked(desc); > > > > We probably need something similar for irq_eoi(). > > > > This however shows a more fundamental problem, I'm afraid. We set > > IRQCHIP_AUTOMASKS_FLOW in the GIC drivers (i.e. at the root), but test > > for it at the top of the hierarchy. As soon as we have more than a > > single layer of irqchip, this will do the wrong thing (or at least > > miss the masking optimisation). > > > > Yup. > > > This probably advocates for moving the flag into the descriptor. This > > really makes sense, as the flow is global to the whole stack, not just > > to the localised irqchip. > > > > Are we guaranteed to have > > .irq_ack \in {NULL, irq_chip_ack_parent} > > for all intermediate (!root) irqchips? I don't see why that wouldn't > be the case, and with that in mind what you described makes sense to > me. An intermediate layer is allowed to implement its own irq_ack that is not irq_chip_ack_parent, but it then has to call irq_chip_ack_parent itself. There is the bizarre case of drivers/gpio/gpio-thunderx.c that changes the irqchip flow to use either handle_fasteoi_ack_irq or handle_fasteoi_mask_irq, which won't play very nicely with this. Someone said Cavium? > > > In order to restore -next into a working state, I'm temporarily > > dropping this series. Hopefully, we can sort this out before the merge > > window and reinstate it. > > > > I'm away from any keyboard for most of this week, but I'll get to it by the > weekend. No worries, enjoy your break! M. -- Without deviation from the norm, progress is not possible.