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[91.155.214.58]) by smtp.gmail.com with ESMTPSA id r19sm992094ljp.68.2020.05.15.03.41.26 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 15 May 2020 03:41:27 -0700 (PDT) From: Felipe Balbi To: Jun Li , Jun Li Cc: John Stultz , lkml , Yu Chen , Greg Kroah-Hartman , Rob Herring , Mark Rutland , ShuFan Lee , Heikki Krogerus , Suzuki K Poulose , Chunfeng Yun , Hans de Goede , Andy Shevchenko , Valentin Schneider , Jack Pham , Linux USB List , "open list\:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Peter Chen , Thinh Nguyen Subject: RE: [PATCH v4 3/9] usb: dwc3: Increase timeout for CmdAct cleared by device controller In-Reply-To: References: <20191028215919.83697-1-john.stultz@linaro.org> <20191028215919.83697-4-john.stultz@linaro.org> <87mudjj4rc.fsf@gmail.com> <87h7wqmwrv.fsf@kernel.org> <87imgx35pg.fsf@kernel.org> Date: Fri, 15 May 2020 13:41:23 +0300 Message-ID: <87d07532gc.fsf@kernel.org> MIME-Version: 1.0 Content-Type: multipart/signed; boundary="=-=-="; micalg=pgp-sha256; protocol="application/pgp-signature" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --=-=-= Content-Type: text/plain Content-Transfer-Encoding: quoted-printable Hi, Jun Li writes: >> Jun Li writes: >> >> @@ -397,12 +407,18 @@ int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep= , unsigned >> cmd, >> >> dwc3_gadget_ep_get_transfer_index(dep); >> >> } >> >> >> >> - if (saved_config) { >> >> + if (saved_hs_config) { >> >> reg =3D dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); >> >> - reg |=3D saved_config; >> >> + reg |=3D saved_hs_config; >> >> dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); >> >> } >> >> >> >> + if (saved_ss_config) { >> >> + reg =3D dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); >> >> + reg |=3D saved_ss_config; >> >> + dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); >> >> + } >> >> + >> >> return ret; >> >> } >> > >> > Unfortunately this way can't work, once the SS PHY enters P3, disable >> > suspend_en can't force SS PHY exit P3, unless do this at the very >> > beginning to prevent SS PHY entering P3(e.g. add "snps,dis_u3_susphy_q= uirk" for >> test). >>=20 >> It sounds like you have a quirky PHY.=20 > > From what I got from the IC design, the behavior of DWC3_GUSB3PIPECTL_SUS= PHY > bit should be as what I said, not a quirky. > > Hi Thinh, could you comment this? > >> If that's the case, then you probably need >> to use the flag you mentioned above. Please verify with that. > > With quirk of "snps,dis_u3_susphy_quirk", I had verified it can > resolve the problem, but this will make USB3 Super Speed PHY > never enter P3, this is a huge impact on USB power consumption. > > The timeout increase has no impact on those platforms which have > no this problem, but can give chance for platform with very low > supspend clk(like my case 32k) to work. I was under the impression that issuing a command would wake the PHY up. I don't have access to DWC3 documentation to verify, but that's as I remember. Is that not the case? =2D-=20 balbi --=-=-= Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIzBAEBCAAdFiEElLzh7wn96CXwjh2IzL64meEamQYFAl6+cdMACgkQzL64meEa mQYMMQ//ReGJl+YwiKBw2I8knemHDYhudQuGQSG6s78dfTKTJkH84XJ197AGxIPm s4vOk6VAuXpsWmota81ZU57GGC+NZqPLVQMXsrEE08HgFrHjjIriIv6AwoQ8rHfi pVQHdma8yaZRFRLYtzpGUf0lEHbgIgcy50gnGpjcQKc/FvChJNCbBNVvp8IVJPIA L/Zi5Vsl+lyLYSHYYYIDXU3EhPEbel8GmDYwNqn+N8jgxdDqF+vxwx+t1uXy584S EdVTnJZihL6TcTwck7//mrGfvIZ04sLtrGgbaUcmw/QotlfmrkWcmUN1P4as2A51 A/+z0NcV6FQBIKj8lnDlYUjSL36qYw32mCvb1TTp6JnZ/khMclrYd/5o8C+beRna OUS0dhOy2/ygBfuiUiw2x15pe0GQ24EN0ZiLmTWrjd49whqkqheM7PWKNLxtnnmP 2/10rAdQpD5STJSHiQi6YZSQaMsRPDlQasyVcrlAgOqNBfA3pRXz6rqRYD4NTLL0 1IGl4EtzZlEfQpIqpZlaLtirz6iPkqMrRXROaTiZC55tHoItwaJ+wqZ47n8QQWyG NehsGGD3dk9LyGjiIpXnZ3HIalOTLXKwagEpfD39sgQsTBuzSfexUYER3diNe93k X4exS7gdYwhTfbYPiFbY9HcyQqRDckgC5p0k/qEdpeqw+WsQ3MQ= =ljzj -----END PGP SIGNATURE----- --=-=-=--