From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BFD0DC433F5 for ; Mon, 7 Mar 2022 11:35:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237250AbiCGLgO (ORCPT ); Mon, 7 Mar 2022 06:36:14 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41198 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229854AbiCGLgM (ORCPT ); Mon, 7 Mar 2022 06:36:12 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 24E884160B; Mon, 7 Mar 2022 03:35:18 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id B082E60AE3; Mon, 7 Mar 2022 11:35:17 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 11B7CC340E9; Mon, 7 Mar 2022 11:35:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1646652917; bh=Osz8sllZUSrLQqMcpk13nTc3kdPqrqmd1TJr5Spr3g4=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=eajbeZsnGmvzhIDQnG0aWaPTMjtUp9jyo8k7jDEnQzBq2abOCF65hye22JZILw3Tj JPmyjEGkMUweaWu5KWKUm6kTYzySF1f0/3bPYUAIhsMMWDnS5twzTrpqTCShtxvAsf jV5BnXAHkjEkJNwO81hosH5wbw+2uM+EbLrNy3pab/EjI5Mq67dIlSa1EZ8kGH6uBm 7dp6Ql1MIWcvYenz81Pz1r/MxWXLudQWAEKq//J870tMN0X/gqE60q2zrGenk20hRg jbX8hTrXwUIxg5HLADPxxr0r6RwKvW0jzH/qXXnP3ACdRucJetvf24SF/CFSGh+YY9 zWu5E9JV5PvhA== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1nRBdy-00ClcM-L0; Mon, 07 Mar 2022 11:35:14 +0000 Date: Mon, 07 Mar 2022 11:35:14 +0000 Message-ID: <87fsnu0zd9.wl-maz@kernel.org> From: Marc Zyngier To: Hector Martin Cc: Thomas Gleixner , Rob Herring , Sven Peter , Alyssa Rosenzweig , Mark Kettenis , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v2 3/7] irqchip/apple-aic: Add Fast IPI support In-Reply-To: References: <20220224130741.63924-1-marcan@marcan.st> <20220224130741.63924-4-marcan@marcan.st> <87mtif2eoz.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: marcan@marcan.st, tglx@linutronix.de, robh+dt@kernel.org, sven@svenpeter.dev, alyssa@rosenzweig.io, mark.kettenis@xs4all.nl, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sun, 27 Feb 2022 15:33:54 +0000, Hector Martin wrote: > > On 25/02/2022 23.39, Marc Zyngier wrote: > > On Thu, 24 Feb 2022 13:07:37 +0000, > >> if (!(pending & irq_bit) && > >> - (atomic_read(per_cpu_ptr(&aic_vipi_enable, cpu)) & irq_bit)) > >> - send |= AIC_IPI_SEND_CPU(cpu); > >> + (atomic_read(per_cpu_ptr(&aic_vipi_enable, cpu)) & irq_bit)) { > >> + if (static_branch_likely(&use_fast_ipi)) > >> + aic_ipi_send_fast(cpu); > > > > OK, this is suffering from the same issue that GICv3 has, which is > > that memory barriers don't provide order against sysregs. You need a > > DSB for that, which is a pain. Something like this: > > Doesn't the control flow here guarantee the ordering? atomic_read() must > complete before the sysreg is written since there is a control flow > dependency, and the prior atomic/barrier dance ensures that read is > ordered properly with everything that comes before it. Yes, you're right. Mixing memory ordering and control dependency hurts my head badly, but hey, why not. M. -- Without deviation from the norm, progress is not possible.