From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E1A86C433FE for ; Thu, 21 Apr 2022 09:48:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1387873AbiDUJvU (ORCPT ); Thu, 21 Apr 2022 05:51:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54216 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1387854AbiDUJvS (ORCPT ); Thu, 21 Apr 2022 05:51:18 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C2BC12495B; Thu, 21 Apr 2022 02:48:29 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 5FD4C61862; Thu, 21 Apr 2022 09:48:29 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id BDD31C385A5; Thu, 21 Apr 2022 09:48:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1650534508; bh=XrSuvi/kMNvYFryLGbGEihpymmK29jNalrxYVMSfVak=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=cMKgodRj8swyo8xWhXe8sE+34c6gmzvqGrltAya9Ptso4f2piSprGseeBONPjOgvp Lcgimt8hBa++2OGqnnHsyVJhuPcmD7bepOQHXvCy5hZ85q0AI87l2hmg83X++Voxu3 nWnXZ29dcDXKBuRGX9qlt6d4WpgEs4Q4xLvO6Z0hASmySk0ad/DbEx/wDMHa3RWNF5 kfaERV9oxTF0vd/RLeOF1KxaRL9mM5zNIHkJv3jhVmlBZ7//K7b/I5+q6Dyl85NtCx cAGp+ejIzWaakzKCRg6jIXjelAZz2C7GNSidHjWjlFlGpWQL3tykvcBDJtGy2PZxst JrFLBXUdmZVGw== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1nhTQI-005qiP-82; Thu, 21 Apr 2022 10:48:26 +0100 Date: Thu, 21 Apr 2022 10:48:26 +0100 Message-ID: <87h76mahsl.wl-maz@kernel.org> From: Marc Zyngier To: Linus Walleij , Sander Vanheule Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Bert Vermeulen , linux-kernel@vger.kernel.org Subject: Re: [PATCH v1 3/6] gpio: realtek-otto: Support per-cpu interrupts In-Reply-To: References: <8d4e0848f233c2c1b98aa141741c61d95cd3843f.1649533972.git.sander@svanheule.net> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linus.walleij@linaro.org, sander@svanheule.net, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, brgl@bgdev.pl, robh+dt@kernel.org, krzk+dt@kernel.org, bert@biot.com, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 21 Apr 2022 00:04:16 +0100, Linus Walleij wrote: > > On Sat, Apr 9, 2022 at 9:56 PM Sander Vanheule wrote: > > > On SoCs with multiple cores, it is possible that the GPIO interrupt > > controller supports assigning specific pins to one or more cores. > > > > IRQ balancing can be performed on a line-by-line basis if the parent > > interrupt is routed to all available cores, which is the default upon > > initialisation. > > > > Signed-off-by: Sander Vanheule > > That sounds complicated. > > Sounds like something the IRQ maintainer (Marc Z) should > have a quick look at. This is pretty odd indeed. There seem to be a direct mapping between the GPIOs and the CPU it interrupts (or at least that's what the code seem to express). However, I don't see a direct relation between the CPUs and the chained interrupt. It isn't even clear if this interrupt itself is per-CPU. So this begs a few questions: - is the affinity actually affecting the target CPU? or is it affecting the target mux? - how is the affinity of the mux interrupt actually enforced? M. -- Without deviation from the norm, progress is not possible.