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d="scan'208";a="81897758" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 02 Jun 2020 01:39:34 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Tue, 2 Jun 2020 01:39:33 -0700 Received: from soft-dev15.microsemi.net.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5 via Frontend Transport; Tue, 2 Jun 2020 01:39:18 -0700 References: <20200513125532.24585-1-lars.povlsen@microchip.com> <20200513125532.24585-11-lars.povlsen@microchip.com> <20200528021826.GA3221035@bogus> From: Lars Povlsen To: Rob Herring List-Id: CC: Lars Povlsen , SoC Team , "Arnd Bergmann" , Stephen Boyd , Linus Walleij , Steen Hegelund , Microchip Linux Driver Support , Olof Johansson , Michael Turquette , , , , , , Alexandre Belloni Subject: Re: [PATCH 10/14] dt-bindings: clock: sparx5: Add Sparx5 SoC DPLL clock In-Reply-To: <20200528021826.GA3221035@bogus> Date: Tue, 2 Jun 2020 10:39:29 +0200 Message-ID: <87h7vtq2ta.fsf@soft-dev15.microsemi.net> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Rob Herring writes: > On Wed, May 13, 2020 at 02:55:28PM +0200, Lars Povlsen wrote: >> This add the DT bindings documentation for the Sparx5 SoC DPLL clock >> >> Reviewed-by: Alexandre Belloni >> Signed-off-by: Lars Povlsen >> --- >> .../bindings/clock/microchip,sparx5-dpll.yaml | 46 +++++++++++++++++++ >> 1 file changed, 46 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/clock/microchip,sparx5-dpll.yaml >> >> diff --git a/Documentation/devicetree/bindings/clock/microchip,sparx5-dpll.yaml b/Documentation/devicetree/bindings/clock/microchip,sparx5-dpll.yaml >> new file mode 100644 >> index 0000000000000..594007d8fc59a >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/clock/microchip,sparx5-dpll.yaml >> @@ -0,0 +1,46 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/clock/microchip,sparx5-dpll.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Microchip Sparx5 DPLL Clock >> + >> +maintainers: >> + - Lars Povlsen >> + >> +description: | >> + The Sparx5 DPLL clock controller generates and supplies clock to >> + various peripherals within the SoC. >> + >> + This binding uses common clock bindings >> + [1] Documentation/devicetree/bindings/clock/clock-bindings.txt >> + >> +properties: >> + compatible: >> + const: microchip,sparx5-dpll >> + >> + reg: >> + items: >> + - description: dpll registers > > For a single entry, just: > > maxItems: 1 Ok. > >> + >> + '#clock-cells': >> + const: 1 >> + >> +required: >> + - compatible >> + - reg >> + - '#clock-cells' >> + >> +additionalProperties: false >> + >> +examples: >> + # Clock provider for eMMC: >> + - | >> + clks: clks@61110000c { > > clock-controller@1110000c { > Got that. >> + compatible = "microchip,sparx5-dpll"; >> + #clock-cells = <1>; >> + reg = <0x1110000c 0x24>; > > Looks like this is a sub-block in some other h/w block. What's the > parent device? That should be described and this should be part of it > either as a single node or a child node. Without a complete view of what > this block has I can't provide any guidance. No, as Alex noted to a similar comment in the temp. sensor driver, the chip is using packed register spaces predominantly. So don't put too much into the register offsets. ---Lars > > Rob -- Lars Povlsen, Microchip