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Tue, 3 May 2022 16:16:36 +0000 (GMT) Received: from localhost (unknown [9.160.48.141]) by b03ledav004.gho.boulder.ibm.com (Postfix) with ESMTPS; Tue, 3 May 2022 16:16:35 +0000 (GMT) From: Fabiano Rosas To: Michael Ellerman , Laurent Dufour Cc: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org, Nicholas Piggin Subject: Re: [PATCH v2] powerpc/rtas: Keep MSR[RI] set when calling RTAS In-Reply-To: <87r15aveny.fsf@mpe.ellerman.id.au> References: <20220401140634.65726-1-ldufour@linux.ibm.com> <87r15aveny.fsf@mpe.ellerman.id.au> Date: Tue, 03 May 2022 13:16:29 -0300 Message-ID: <87levia8wy.fsf@linux.ibm.com> MIME-Version: 1.0 Content-Type: text/plain X-TM-AS-GCONF: 00 X-Proofpoint-GUID: 4QIy9T9IVO1N4-KCXdHIXyrKE1c93rvw X-Proofpoint-ORIG-GUID: YQ4p8xJgLWTLQN6qlQo2zo0ubGdZUdNr X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.858,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-05-03_06,2022-05-02_03,2022-02-23_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 mlxscore=0 malwarescore=0 priorityscore=1501 lowpriorityscore=0 phishscore=0 suspectscore=0 bulkscore=0 spamscore=0 mlxlogscore=852 adultscore=0 clxscore=1011 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2202240000 definitions=main-2205030109 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Michael Ellerman writes: >> diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S >> index 9581906b5ee9..65cb14b56f8d 100644 >> --- a/arch/powerpc/kernel/entry_64.S >> +++ b/arch/powerpc/kernel/entry_64.S >> @@ -330,22 +330,18 @@ _GLOBAL(enter_rtas) >> clrldi r4,r4,2 /* convert to realmode address */ >> mtlr r4 >> >> - li r0,0 >> - ori r0,r0,MSR_EE|MSR_SE|MSR_BE|MSR_RI >> - andc r0,r6,r0 >> - >> - li r9,1 >> - rldicr r9,r9,MSR_SF_LG,(63-MSR_SF_LG) >> - ori r9,r9,MSR_IR|MSR_DR|MSR_FE0|MSR_FE1|MSR_FP|MSR_RI|MSR_LE >> - andc r6,r0,r9 > > One advantage of the old method is it can adapt to new MSR bits being > set by the kernel. > > For example we used to use RTAS on powernv, and this code didn't need > updating to cater to MSR_HV being set. We will probably never use RTAS > on bare-metal again, so that's OK. > > But your change might break secure virtual machines, because it clears > MSR_S whereas the old code didn't. I think SVMs did use RTAS, but I > don't know whether it matters if it's called with MSR_S set or not? > > Not sure if anyone will remember, or has a working setup they can test. > Maybe for now we just copy MSR_S from the kernel MSR the way the > current code does. Would the kernel even be able to change the bit? I think only urfid can clear MSR_S.