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From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
To: Christophe Leroy <christophe.leroy@c-s.fr>,
	Benjamin Herrenschmidt <benh@kernel.crashing.org>,
	Paul Mackerras <paulus@samba.org>,
	Michael Ellerman <mpe@ellerman.id.au>
Cc: linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org
Subject: Re: [PATCH  09/17] powerpc: make __ioremap_caller() common to PPC32 and PPC64
Date: Tue, 08 May 2018 15:26:20 +0530	[thread overview]
Message-ID: <87lgcusc6z.fsf@linux.vnet.ibm.com> (raw)
In-Reply-To: <457781f2de403852ba2a60257c3d9aca75c4d2c8.1525435203.git.christophe.leroy@c-s.fr>

Christophe Leroy <christophe.leroy@c-s.fr> writes:

> Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
> ---
>  arch/powerpc/include/asm/book3s/64/pgtable.h |   1 +
>  arch/powerpc/mm/ioremap.c                    | 126 +++++++--------------------
>  2 files changed, 34 insertions(+), 93 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/book3s/64/pgtable.h b/arch/powerpc/include/asm/book3s/64/pgtable.h
> index c5c6ead06bfb..2bebdd8302cb 100644
> --- a/arch/powerpc/include/asm/book3s/64/pgtable.h
> +++ b/arch/powerpc/include/asm/book3s/64/pgtable.h
> @@ -18,6 +18,7 @@
>  #define _PAGE_RO		0
>  #define _PAGE_USER		0
>  #define _PAGE_HWWRITE		0
> +#define _PAGE_COHERENT		0

This is something I was trying to avoid when I split the headers. We do
support _PAGE_USER it is !_PAGE_PRIVILEGED. It gets really confusing
when we have these conflicting names because we are trying to make code
common across platforms.


>  
>  #define _PAGE_EXEC		0x00001 /* execute permission */
>  #define _PAGE_WRITE		0x00002 /* write access allowed */
> diff --git a/arch/powerpc/mm/ioremap.c b/arch/powerpc/mm/ioremap.c
> index 65d611d44d38..59be5dfcb3e9 100644
> --- a/arch/powerpc/mm/ioremap.c
> +++ b/arch/powerpc/mm/ioremap.c
> @@ -33,95 +33,6 @@ unsigned long ioremap_bot;
>  unsigned long ioremap_bot = IOREMAP_BASE;
>  #endif
>  
> -#ifdef CONFIG_PPC32
> -
> -void __iomem *
> -__ioremap_caller(phys_addr_t addr, unsigned long size, unsigned long flags,
> -		 void *caller)
> -{
> -	unsigned long v, i;
> -	phys_addr_t p;
> -	int err;
> -
> -	/* Make sure we have the base flags */
> -	if ((flags & _PAGE_PRESENT) == 0)
> -		flags |= pgprot_val(PAGE_KERNEL);
> -
> -	/* Non-cacheable page cannot be coherent */
> -	if (flags & _PAGE_NO_CACHE)
> -		flags &= ~_PAGE_COHERENT;
> -
> -	/*
> -	 * Choose an address to map it to.
> -	 * Once the vmalloc system is running, we use it.
> -	 * Before then, we use space going up from IOREMAP_BASE
> -	 * (ioremap_bot records where we're up to).
> -	 */
> -	p = addr & PAGE_MASK;
> -	size = PAGE_ALIGN(addr + size) - p;
> -
> -	/*
> -	 * If the address lies within the first 16 MB, assume it's in ISA
> -	 * memory space
> -	 */
> -	if (p < 16*1024*1024)
> -		p += _ISA_MEM_BASE;
> -
> -#ifndef CONFIG_CRASH_DUMP
> -	/*
> -	 * Don't allow anybody to remap normal RAM that we're using.
> -	 * mem_init() sets high_memory so only do the check after that.
> -	 */
> -	if (slab_is_available() && (p < virt_to_phys(high_memory)) &&
> -	    page_is_ram(__phys_to_pfn(p))) {
> -		printk("__ioremap(): phys addr 0x%llx is RAM lr %ps\n",
> -		       (unsigned long long)p, __builtin_return_address(0));
> -		return NULL;
> -	}
> -#endif
> -
> -	if (size == 0)
> -		return NULL;
> -
> -	/*
> -	 * Is it already mapped?  Perhaps overlapped by a previous
> -	 * mapping.
> -	 */
> -	v = p_block_mapped(p);
> -	if (v)
> -		goto out;
> -
> -	if (slab_is_available()) {
> -		struct vm_struct *area;
> -		area = get_vm_area_caller(size, VM_IOREMAP, caller);
> -		if (area == 0)
> -			return NULL;
> -		area->phys_addr = p;
> -		v = (unsigned long) area->addr;
> -	} else {
> -		v = ioremap_bot;
> -		ioremap_bot += size;
> -	}
> -
> -	/*
> -	 * Should check if it is a candidate for a BAT mapping
> -	 */
> -
> -	err = 0;
> -	for (i = 0; i < size && err == 0; i += PAGE_SIZE)
> -		err = map_kernel_page(v+i, p+i, flags);
> -	if (err) {
> -		if (slab_is_available())
> -			vunmap((void *)v);
> -		return NULL;
> -	}
> -
> -out:
> -	return (void __iomem *) (v + ((unsigned long)addr & ~PAGE_MASK));
> -}
> -
> -#else
> -
>  /**
>   * __ioremap_at - Low level function to establish the page tables
>   *                for an IO mapping
> @@ -135,6 +46,10 @@ void __iomem * __ioremap_at(phys_addr_t pa, void *ea, unsigned long size,
>  	if ((flags & _PAGE_PRESENT) == 0)
>  		flags |= pgprot_val(PAGE_KERNEL);
>  
> +	/* Non-cacheable page cannot be coherent */
> +	if (flags & _PAGE_NO_CACHE)
> +		flags &= ~_PAGE_COHERENT;
> +
>  	/* We don't support the 4K PFN hack with ioremap */
>  	if (flags & H_PAGE_4K_PFN)
>  		return NULL;
> @@ -187,6 +102,33 @@ void __iomem * __ioremap_caller(phys_addr_t addr, unsigned long size,
>  	if ((size == 0) || (paligned == 0))
>  		return NULL;
>  
> +	/*
> +	 * If the address lies within the first 16 MB, assume it's in ISA
> +	 * memory space
> +	 */
> +	if (IS_ENABLED(CONFIG_PPC32) && paligned < 16*1024*1024)
> +		paligned += _ISA_MEM_BASE;
> +
> +	/*
> +	 * Don't allow anybody to remap normal RAM that we're using.
> +	 * mem_init() sets high_memory so only do the check after that.
> +	 */
> +	if (!IS_ENABLED(CONFIG_CRASH_DUMP) &&
> +	    slab_is_available() && (paligned < virt_to_phys(high_memory)) &&
> +	    page_is_ram(__phys_to_pfn(paligned))) {
> +		printk("__ioremap(): phys addr 0x%llx is RAM lr %ps\n",
> +		       (u64)paligned, __builtin_return_address(0));
> +		return NULL;
> +	}
> +
> +	/*
> +	 * Is it already mapped?  Perhaps overlapped by a previous
> +	 * mapping.
> +	 */
> +	ret = (void __iomem *)p_block_mapped(paligned);
> +	if (ret)
> +		goto out;
> +
>  	if (slab_is_available()) {
>  		struct vm_struct *area;
>  
> @@ -205,14 +147,12 @@ void __iomem * __ioremap_caller(phys_addr_t addr, unsigned long size,
>  		if (ret)
>  			ioremap_bot += size;
>  	}
> -
> +out:
>  	if (ret)
> -		ret += addr & ~PAGE_MASK;
> +		ret += (unsigned long)addr & ~PAGE_MASK;
>  	return ret;
>  }
>  
> -#endif
> -
>  /*
>   * Unmap an IO region and remove it from imalloc'd list.
>   * Access to IO memory should be serialized by driver.
> -- 
> 2.13.3

  reply	other threads:[~2018-05-08  9:56 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-05-04 12:33 [PATCH 00/17] Implement use of HW assistance on TLB table walk on 8xx Christophe Leroy
2018-05-04 12:33 ` [PATCH 01/17] powerpc/nohash: remove hash related code from nohash headers Christophe Leroy
2018-05-08  8:25   ` Aneesh Kumar K.V
2018-05-04 12:33 ` [PATCH 02/17] powerpc/nohash: remove _PAGE_BUSY Christophe Leroy
2018-05-08  8:26   ` Aneesh Kumar K.V
2018-05-04 12:33 ` [PATCH 03/17] powerpc/nohash: use IS_ENABLED() to simplify __set_pte_at() Christophe Leroy
2018-05-04 12:33 ` [PATCH 04/17] Revert "powerpc/8xx: Use L1 entry APG to handle _PAGE_ACCESSED for CONFIG_SWAP" Christophe Leroy
2018-05-04 12:34 ` [PATCH 05/17] powerpc: move io mapping functions into ioremap.c Christophe Leroy
2018-05-11  6:01   ` Michael Ellerman
2018-05-16 10:13     ` Christophe LEROY
2018-05-04 12:34 ` [PATCH 06/17] powerpc: common ioremap functions Christophe Leroy
2018-05-04 12:34 ` [PATCH 07/17] powerpc: make ioremap_bot common to PPC32 and PPC64 Christophe Leroy
2018-05-04 12:34 ` [PATCH 08/17] powerpc: make __iounmap() " Christophe Leroy
2018-05-04 12:34 ` [PATCH 09/17] powerpc: make __ioremap_caller() " Christophe Leroy
2018-05-08  9:56   ` Aneesh Kumar K.V [this message]
2018-05-16  9:58     ` Christophe LEROY
2018-05-04 12:34 ` [PATCH 10/17] powerpc: use _ALIGN macro Christophe Leroy
2018-05-04 12:34 ` [PATCH 11/17] powerpc/nohash32: set GUARDED attribute in the PMD directly Christophe Leroy
2018-05-11  6:45   ` Michael Ellerman
2018-05-04 12:34 ` [PATCH 12/17] powerpc/8xx: Remove PTE_ATOMIC_UPDATES Christophe Leroy
2018-05-04 13:16   ` Joakim Tjernlund
2018-05-04 12:34 ` [PATCH 13/17] powerpc/mm: Use hardware assistance in TLB handlers on the 8xx Christophe Leroy
2018-05-04 12:34 ` [PATCH 14/17] powerpc/8xx: reunify TLB handler routines Christophe Leroy
2018-05-04 12:34 ` [PATCH 15/17] powerpc/8xx: Free up SPRN_SPRG_SCRATCH2 Christophe Leroy
2018-05-04 12:34 ` [PATCH 16/17] powerpc/mm: Make pte_fragment_alloc() common to PPC32 and PPC64 Christophe Leroy
2018-05-04 12:34 ` [PATCH BAD 17/17] powerpc/mm: Use pte_fragment_alloc() on 8xx Christophe Leroy
2018-05-11  6:48 ` [PATCH 00/17] Implement use of HW assistance on TLB table walk " Michael Ellerman
2018-05-16 10:17   ` Christophe LEROY

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