From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753157AbcJFGrU (ORCPT ); Thu, 6 Oct 2016 02:47:20 -0400 Received: from smtp01.smtpout.orange.fr ([80.12.242.123]:34510 "EHLO smtp.smtpout.orange.fr" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752127AbcJFGrT (ORCPT ); Thu, 6 Oct 2016 02:47:19 -0400 X-ME-Helo: belgarion X-ME-Auth: amFyem1pay5yb2JlcnRAb3JhbmdlLmZy X-ME-Date: Thu, 06 Oct 2016 08:47:16 +0200 X-ME-IP: 90.5.140.104 From: Robert Jarzmik To: Mark Rutland Cc: Rob Herring , Nicolas Pitre , Russell King - ARM Linux , Arnd Bergmann , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 3/3] net: smsc911x: add u16 workaround for pxa platforms References: <1475485553-18747-1-git-send-email-robert.jarzmik@free.fr> <1475485553-18747-3-git-send-email-robert.jarzmik@free.fr> <20161003154624.GG7632@leverpostej> <87oa319zv8.fsf@belgarion.home> <20161003165032.GB15313@leverpostej> <871szx9rhc.fsf@belgarion.home> X-URL: http://belgarath.falguerolles.org/ Date: Thu, 06 Oct 2016 08:47:13 +0200 In-Reply-To: <871szx9rhc.fsf@belgarion.home> (Robert Jarzmik's message of "Mon, 03 Oct 2016 21:12:31 +0200") Message-ID: <87lgy27z4e.fsf@belgarion.home> User-Agent: Gnus/5.130008 (Ma Gnus v0.8) Emacs/24.4 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Robert Jarzmik writes: > Mark Rutland writes: > >> On Mon, Oct 03, 2016 at 06:11:23PM +0200, Robert Jarzmik wrote: >>> Mark Rutland writes: >>> >>> reg-u16-align4 tells that a specific hardware doesn't support 16 bit writes not >>> being 32 bits aligned, or said differently that a "store" 16 bits wide on an >>> address of the format 4*n + 2 deserves a special handling in the driver, while a >>> store 16 bits wide on an address of the format 4*n can follow the simple casual >>> case. >> >> If I've understood correctly, effectively the low 2 address lines to the >> device are hard-wired to zero, e.g. a 16-bit access to 4*n + 2 would go >> to 4*n + 0 on the device? Or is the failure case distinct from that? > It is distinct. > > The "awful truth" is that an FPGA lies between the system bus and the > smc91c111. And this FPGA cannot handle correctly the 4*n + 2 u16 writes. > >> Do we have other platforms where similar is true? e.g. u8 accesses >> requiring 16-bit alignment? > > Not really, ie. not with a alignement requirement. > > But there are of course these ones are handled by reg-io-width and the > SMC_USE_xxx_BITS flags as far as I understand it. These cases are when a > platform declares SMC91X_USE_16BIT or SMC91X_USE_32BIT, but not SMC91X_USE_8BIT, > which would make me think of : > - CONFIG_SH_SH4202_MICRODEV, > - CONFIG_M32R > - several omap1 boards > - 1 sa1100 board > - several MMP and realview boards > > With all these platforms, each u8 access is replaced with a u16 access and a > mask / shift + mask. Or so what should I call this entry if reg-u16-align4 is not a good candidate ? Cheers. -- Robert