From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S966603AbcCPN4p (ORCPT ); Wed, 16 Mar 2016 09:56:45 -0400 Received: from mga02.intel.com ([134.134.136.20]:20625 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934289AbcCPN4o (ORCPT ); Wed, 16 Mar 2016 09:56:44 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.24,344,1455004800"; d="asc'?scan'208";a="67470297" From: Felipe Balbi To: Roger Quadros , John Youn Cc: nsekhar@ti.com, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, Roger Quadros Subject: Re: [PATCH 1/2] usb: dwc3: core: Introduce dwc3_device_reinit() In-Reply-To: <87r3fah8h3.fsf@intel.com> References: <1458133551-3071-1-git-send-email-rogerq@ti.com> <1458133551-3071-2-git-send-email-rogerq@ti.com> <87r3fah8h3.fsf@intel.com> User-Agent: Notmuch/0.21 (http://notmuchmail.org) Emacs/25.0.90.3 (x86_64-pc-linux-gnu) Date: Wed, 16 Mar 2016 15:55:43 +0200 Message-ID: <87lh5ih6hs.fsf@intel.com> MIME-Version: 1.0 Content-Type: multipart/signed; boundary="=-=-="; micalg=pgp-sha1; protocol="application/pgp-signature" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --=-=-= Content-Type: text/plain Content-Transfer-Encoding: quoted-printable heh, +john Felipe Balbi writes: > [ text/plain ] > > Hi, > > Roger Quadros writes: >> [ text/plain ] >> We will need this function for a workaround. >> The function issues a softreset only to the device >> controller and performs minimal re-initialization >> so that the device controller can be usable. >> >> As some code is similar to dwc3_core_init() take out >> common code into dwc3_get_gctl_quirks(). >> >> We add a new member (prtcap_mode) to struct dwc3 to >> keep track of the current mode in the PRTCAPDIR register. >> >> Signed-off-by: Roger Quadros > > I must say, I don't like this at all :-p There's ONE known silicon which > needs this because of a poor silicon integration which took an IP with a > known erratum where it can't be made to work on lower speeds and STILL > was integrated without a superspeed PHY. > > There's a reason why I never tried to push this upstream myself ;-) > > I'm really thinking we might be better off adding a quirk flag to skip > the metastability workaround and allow this ONE silicon to set the > controller to lower speed. > > John, can you check with your colleagues if we would ever fall into > STAR#9000525659 if we set maximum speed to high speed during driver > probe and never touch it again ? I would assume we don't really fall > into the metastability workaround, right ? We're not doing any sort of > PM for dwc3... > > --=20 > balbi > [ signature.asc: application/pgp-signature ] =2D-=20 balbi --=-=-= Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAEBAgAGBQJW6WXfAAoJEIaOsuA1yqREy1wP/3ijWMMtIqUbUDNSV3XMt/YP hXVfb1rPDNiSAJkqT03H4JcOJSUnVeH3G29tAyjbyasznNERAm0L//VxVRMHQZoh ljSwSS6RyI2kMmaNCd6lsmRxeNxWpQN3miJYaHDMwGxY/vu5QsG9vsS3lczAwN2z 6XP2kxNXZoh/pjQPPsNGaPVcLt4QqyO9TFOpYE+/JPTR0PP0Ga9W7aINBQueVabB PDXsG3fwGZWjqJMyiGBuu0FuP5VV7H+NRExqRDqIx7pijVBp2qMv9Oqxcb+0h1jf RyPJoqnAODj9djAkTeEv0yTDdiObjwhBxn0LuSvOBvbTwY+Tq6OPeSNuaLp8UM5x ZLdyD1oLDbojUjcjnbgJuarKdZjNFuEOEzFkSi9+Sarv3N43Z6zw7SNOo+ahMuP9 6IV2aWdkeNoLSY3m6i+/BspVqg56tmlx1JEMn8F9oonK4xJ9SHeKJkHe/IHVRo3l jX3qJiLNi2QL6XiksgHbb1no90fPO4j0ABnFNCGYITz5Xbz5wl6lzwdN8aU4fgBp +XWxwDmiujor2xYfQJAwcfFczs8kBtkbu4jIrOvHWFbqk74Bm0WOIyU2SuSQHkvN P1vz4rO2Vp5LqKzhMVAQmE71/i0PwTsFsm+wDb938teGPy72GUuGy2cEl2tujzhe xL+e5Hdk+JX+L4lJVznw =xp3U -----END PGP SIGNATURE----- --=-=-=--