From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 58ED3C433F5 for ; Mon, 11 Oct 2021 13:40:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3DF1E61040 for ; Mon, 11 Oct 2021 13:40:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237238AbhJKNmN (ORCPT ); Mon, 11 Oct 2021 09:42:13 -0400 Received: from mail.kernel.org ([198.145.29.99]:60720 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237098AbhJKNls (ORCPT ); Mon, 11 Oct 2021 09:41:48 -0400 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 6B71460F21; Mon, 11 Oct 2021 13:39:48 +0000 (UTC) Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mZvWs-00G1D5-4p; Mon, 11 Oct 2021 14:39:46 +0100 Date: Mon, 11 Oct 2021 14:39:45 +0100 Message-ID: <87mtnfptni.wl-maz@kernel.org> From: Marc Zyngier To: Will Deacon Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Mark Rutland , Daniel Lezcano , Thomas Gleixner , Peter Shier , Raghavendra Rao Ananta , Ricardo Koller , Oliver Upton , Catalin Marinas , Linus Walleij , kernel-team@android.com Subject: Re: [PATCH v3 00/17] clocksource/arm_arch_timer: Add basic ARMv8.6 support In-Reply-To: <20211011110243.GB4068@willie-the-truck> References: <20211010114306.2910453-1-maz@kernel.org> <20211011110243.GB4068@willie-the-truck> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: will@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, mark.rutland@arm.com, daniel.lezcano@linaro.org, tglx@linutronix.de, pshier@google.com, rananta@google.com, ricarkol@google.com, oupton@google.com, catalin.marinas@arm.com, linus.walleij@linaro.org, kernel-team@android.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 11 Oct 2021 12:02:44 +0100, Will Deacon wrote: > > On Sun, Oct 10, 2021 at 12:42:49PM +0100, Marc Zyngier wrote: > > This is v3 of the series enabling ARMv8.6 support for timer subsystem, > > and was prompted by a discussion with Oliver around the fact that an > > ARMv8.6 implementation must have a 1GHz counter, which leads to a > > number of things to break in the timer code: > > > > - the counter rollover can come pretty quickly as we only advertise a > > 56bit counter, > > - the maximum timer delta can be remarkably small, as we use the > > countdown interface which is limited to 32bit... > > > > Thankfully, there is a way out: we can compute the minimal width of > > the counter based on the guarantees that the architecture gives us, > > and we can use the 64bit comparator interface instead of the countdown > > to program the timer. > > > > Finally, we start making use of the ARMv8.6 ECV features by switching > > accesses to the counters to a self-synchronising register, removing > > the need for an ISB. Hopefully, implementations will *not* just stick > > an invisible ISB there... > > > > A side effect of the switch to CVAL is that XGene-1 breaks. I have > > added a workaround to keep it alive. > > > > I have added Oliver's original patch[0] to the series and tweaked a > > couple of things. Blame me if I broke anything. > > > > The whole things has been tested on Juno (sysreg + MMIO timers), > > XGene-1 (broken sysreg timers), FVP (FEAT_ECV, CNT*CTSS_EL0). > > The arm64 bits look pretty good to me (I left some minor comments). Thanks for that. All addressed now. I'll repost the series once we've addressed the question below. > How do you want to merge this series? It would be nice to have the arch > bits in the arm64 tree, if possible, as we'll be tripping over the cpucaps > stuff otherwise. I think we should keep the series together, as asm/arch_timer.h gets a beating all over the place, and there is no chance the arm64 bits at the end can apply (let alone work) on their own. So either Daniel would ack the series for it to go via arm64, or create a stable branch with the first 13 patches that would go in both the clocksource and arm64 trees. Daniel, any preference? Thanks, M. -- Without deviation from the norm, progress is not possible.