From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A5D56C83011 for ; Mon, 23 Nov 2020 13:53:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7548A20781 for ; Mon, 23 Nov 2020 13:53:11 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=kernel.org header.i=@kernel.org header.b="1DmGyMg9" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388787AbgKWNxC (ORCPT ); Mon, 23 Nov 2020 08:53:02 -0500 Received: from mail.kernel.org ([198.145.29.99]:38226 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388734AbgKWNw7 (ORCPT ); Mon, 23 Nov 2020 08:52:59 -0500 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id A6EBE206F1; Mon, 23 Nov 2020 13:52:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1606139578; bh=oUMhhreD7ORSVrrrxM5Yp8Xa1lT9bZsNE1HGqNx/qbI=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=1DmGyMg9eMalGYHoQw6TtxoithgNF2WCrrlalkPjTDIThefRks1IY2/MCE5C84fCn UjCt0DR0TwRmheSneb3LDTFout9MOCchOC/G4VcMluASR3m91xpKn/QPgNQRr6rtu4 UunLVdT99666+RRSOwxISTl8mX8C5i2wWx6VcAYk= Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94) (envelope-from ) id 1khCH1-00Cxvt-Is; Mon, 23 Nov 2020 13:52:56 +0000 Date: Mon, 23 Nov 2020 13:52:54 +0000 Message-ID: <87mtz85geh.wl-maz@kernel.org> From: Marc Zyngier To: David Brazdil Cc: kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, James Morse , Julien Thierry , Suzuki K Poulose , Catalin Marinas , Will Deacon , Dennis Zhou , Tejun Heo , Christoph Lameter , Mark Rutland , Lorenzo Pieralisi , Quentin Perret , Andrew Scull , Andrew Walbran , kernel-team@android.com Subject: Re: [PATCH v2 04/24] arm64: Move MAIR_EL1_SET to asm/memory.h In-Reply-To: <20201116204318.63987-5-dbrazdil@google.com> References: <20201116204318.63987-1-dbrazdil@google.com> <20201116204318.63987-5-dbrazdil@google.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: dbrazdil@google.com, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, james.morse@arm.com, julien.thierry.kdev@gmail.com, suzuki.poulose@arm.com, catalin.marinas@arm.com, will@kernel.org, dennis@kernel.org, tj@kernel.org, cl@linux.com, mark.rutland@arm.com, lorenzo.pieralisi@arm.com, qperret@google.com, ascull@google.com, qwandor@google.com, kernel-team@android.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 16 Nov 2020 20:42:58 +0000, David Brazdil wrote: > > KVM currently initializes MAIR_EL2 to the value of MAIR_EL1. In > preparation for initializing MAIR_EL2 before MAIR_EL1, move the constant > into a shared header file. Since it is used for EL1 and EL2, rename to > MAIR_ELx_SET. > > Signed-off-by: David Brazdil > --- > arch/arm64/include/asm/memory.h | 29 ++++++++++++++--------------- > arch/arm64/include/asm/sysreg.h | 30 ++++++++++++++++++++++++++++++ > arch/arm64/mm/proc.S | 15 +-------------- > 3 files changed, 45 insertions(+), 29 deletions(-) > > diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm/memory.h > index cd61239bae8c..8ae8fd883a0c 100644 > --- a/arch/arm64/include/asm/memory.h > +++ b/arch/arm64/include/asm/memory.h > @@ -13,6 +13,7 @@ > #include > #include > #include > +#include > > /* > * Size of the PCI I/O space. This must remain a power of two so that > @@ -124,21 +125,6 @@ > */ > #define SEGMENT_ALIGN SZ_64K > > -/* > - * Memory types available. > - * > - * IMPORTANT: MT_NORMAL must be index 0 since vm_get_page_prot() may 'or' in > - * the MT_NORMAL_TAGGED memory type for PROT_MTE mappings. Note > - * that protection_map[] only contains MT_NORMAL attributes. > - */ > -#define MT_NORMAL 0 > -#define MT_NORMAL_TAGGED 1 > -#define MT_NORMAL_NC 2 > -#define MT_NORMAL_WT 3 > -#define MT_DEVICE_nGnRnE 4 > -#define MT_DEVICE_nGnRE 5 > -#define MT_DEVICE_GRE 6 > - > /* > * Memory types for Stage-2 translation > */ > @@ -152,6 +138,19 @@ > #define MT_S2_FWB_NORMAL 6 > #define MT_S2_FWB_DEVICE_nGnRE 1 > > +/* > + * Default MAIR_EL1. MT_NORMAL_TAGGED is initially mapped as Normal memory and > + * changed during __cpu_setup to Normal Tagged if the system supports MTE. > + */ > +#define MAIR_ELx_SET \ > + (MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRnE, MT_DEVICE_nGnRnE) | \ > + MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRE, MT_DEVICE_nGnRE) | \ > + MAIR_ATTRIDX(MAIR_ATTR_DEVICE_GRE, MT_DEVICE_GRE) | \ > + MAIR_ATTRIDX(MAIR_ATTR_NORMAL_NC, MT_NORMAL_NC) | \ > + MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL) | \ > + MAIR_ATTRIDX(MAIR_ATTR_NORMAL_WT, MT_NORMAL_WT) | \ > + MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL_TAGGED)) > + > #ifdef CONFIG_ARM64_4K_PAGES > #define IOREMAP_MAX_ORDER (PUD_SHIFT) > #else > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index e2ef4c2edf06..24e773414cb4 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -635,6 +635,34 @@ > /* Position the attr at the correct index */ > #define MAIR_ATTRIDX(attr, idx) ((attr) << ((idx) * 8)) > > +/* > + * Memory types available. > + * > + * IMPORTANT: MT_NORMAL must be index 0 since vm_get_page_prot() may 'or' in > + * the MT_NORMAL_TAGGED memory type for PROT_MTE mappings. Note > + * that protection_map[] only contains MT_NORMAL attributes. > + */ > +#define MT_NORMAL 0 > +#define MT_NORMAL_TAGGED 1 > +#define MT_NORMAL_NC 2 > +#define MT_NORMAL_WT 3 > +#define MT_DEVICE_nGnRnE 4 > +#define MT_DEVICE_nGnRE 5 > +#define MT_DEVICE_GRE 6 > + > +/* > + * Default MAIR_ELx. MT_NORMAL_TAGGED is initially mapped as Normal memory and > + * changed during __cpu_setup to Normal Tagged if the system supports MTE. > + */ > +#define MAIR_ELx_SET \ > + (MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRnE, MT_DEVICE_nGnRnE) | \ > + MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRE, MT_DEVICE_nGnRE) | \ > + MAIR_ATTRIDX(MAIR_ATTR_DEVICE_GRE, MT_DEVICE_GRE) | \ > + MAIR_ATTRIDX(MAIR_ATTR_NORMAL_NC, MT_NORMAL_NC) | \ > + MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL) | \ > + MAIR_ATTRIDX(MAIR_ATTR_NORMAL_WT, MT_NORMAL_WT) | \ > + MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL_TAGGED)) > + > /* id_aa64isar0 */ > #define ID_AA64ISAR0_RNDR_SHIFT 60 > #define ID_AA64ISAR0_TLB_SHIFT 56 > @@ -992,6 +1020,7 @@ > /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */ > #define SYS_MPIDR_SAFE_VAL (BIT(31)) > > +#ifndef LINKER_SCRIPT This is terribly ugly. Why is this included by the linker script? Does it actually define __ASSEMBLY__? > #ifdef __ASSEMBLY__ > > .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30 > @@ -1109,5 +1138,6 @@ > }) > > #endif > +#endif /* LINKER_SCRIPT */ > > #endif /* __ASM_SYSREG_H */ > diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S > index 23c326a06b2d..e3b9aa372b96 100644 > --- a/arch/arm64/mm/proc.S > +++ b/arch/arm64/mm/proc.S > @@ -45,19 +45,6 @@ > #define TCR_KASAN_FLAGS 0 > #endif > > -/* > - * Default MAIR_EL1. MT_NORMAL_TAGGED is initially mapped as Normal memory and > - * changed during __cpu_setup to Normal Tagged if the system supports MTE. > - */ > -#define MAIR_EL1_SET \ > - (MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRnE, MT_DEVICE_nGnRnE) | \ > - MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRE, MT_DEVICE_nGnRE) | \ > - MAIR_ATTRIDX(MAIR_ATTR_DEVICE_GRE, MT_DEVICE_GRE) | \ > - MAIR_ATTRIDX(MAIR_ATTR_NORMAL_NC, MT_NORMAL_NC) | \ > - MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL) | \ > - MAIR_ATTRIDX(MAIR_ATTR_NORMAL_WT, MT_NORMAL_WT) | \ > - MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL_TAGGED)) > - > #ifdef CONFIG_CPU_PM > /** > * cpu_do_suspend - save CPU registers context > @@ -425,7 +412,7 @@ SYM_FUNC_START(__cpu_setup) > /* > * Memory region attributes > */ > - mov_q x5, MAIR_EL1_SET > + mov_q x5, MAIR_ELx_SET > #ifdef CONFIG_ARM64_MTE > /* > * Update MAIR_EL1, GCR_EL1 and TFSR*_EL1 if MTE is supported > -- > 2.29.2.299.gdc1121823c-goog > > Thanks, M. -- Without deviation from the norm, progress is not possible.