From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4D5FDC4320E for ; Fri, 20 Aug 2021 13:12:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 36D3460F91 for ; Fri, 20 Aug 2021 13:12:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240745AbhHTNM4 convert rfc822-to-8bit (ORCPT ); Fri, 20 Aug 2021 09:12:56 -0400 Received: from mail.kernel.org ([198.145.29.99]:44674 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240739AbhHTNMy (ORCPT ); Fri, 20 Aug 2021 09:12:54 -0400 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id BDE7560F91; Fri, 20 Aug 2021 13:12:15 +0000 (UTC) Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mH4Jh-006C42-Qa; Fri, 20 Aug 2021 14:12:13 +0100 Date: Fri, 20 Aug 2021 14:12:13 +0100 Message-ID: <87o89sqmz6.wl-maz@kernel.org> From: Marc Zyngier To: Andreas =?UTF-8?B?RsOkcmJlcg==?= Cc: Chester Lin , Rob Herring , s32@nxp.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-serial@vger.kernel.org, Greg Kroah-Hartman , Shawn Guo , Krzysztof Kozlowski , Oleksij Rempel , Stefan Riedmueller , Matthias Schiffer , Li Yang , Fabio Estevam , Matteo Lisi , Frieder Schrempf , Tim Harvey , Jagan Teki , catalin-dan.udma@nxp.com, bogdan.hamciuc@nxp.com, bogdan.folea@nxp.com, ciprianmarian.costea@nxp.com, radu-nicolae.pirea@nxp.com, ghennadi.procopciuc@nxp.com, Matthias Brugger , "Ivan T . Ivanov" , "Lee, Chun-Yi" Subject: Re: [PATCH 4/8] arm64: dts: add NXP S32G2 support In-Reply-To: References: <20210805065429.27485-1-clin@suse.com> <20210805065429.27485-5-clin@suse.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: afaerber@suse.de, clin@suse.com, robh+dt@kernel.org, s32@nxp.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-serial@vger.kernel.org, gregkh@linuxfoundation.org, shawnguo@kernel.org, krzk@kernel.org, linux@rempel-privat.de, s.riedmueller@phytec.de, matthias.schiffer@ew.tq-group.com, leoyang.li@nxp.com, festevam@gmail.com, matteo.lisi@engicam.com, frieder.schrempf@kontron.de, tharvey@gateworks.com, jagan@amarulasolutions.com, catalin-dan.udma@nxp.com, bogdan.hamciuc@nxp.com, bogdan.folea@nxp.com, ciprianmarian.costea@nxp.com, radu-nicolae.pirea@nxp.com, ghennadi.procopciuc@nxp.com, matthias.bgg@gmail.com, iivanov@suse.de, jlee@suse.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 12 Aug 2021 18:26:28 +0100, Andreas Färber wrote: > > Hi Chester et al., > > On 05.08.21 08:54, Chester Lin wrote: > > Add an initial dtsi file for generic SoC features of NXP S32G2. > > > > Signed-off-by: Chester Lin > > --- > > arch/arm64/boot/dts/freescale/s32g2.dtsi | 98 ++++++++++++++++++++++++ > > 1 file changed, 98 insertions(+) > > create mode 100644 arch/arm64/boot/dts/freescale/s32g2.dtsi > > > > diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi > > new file mode 100644 > > index 000000000000..3321819c1a2d > > --- /dev/null > > +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi [...] > > + gic: interrupt-controller@50800000 { > > + compatible = "arm,gic-v3"; > > + #interrupt-cells = <3>; > > + interrupt-controller; > > + reg = <0 0x50800000 0 0x10000>, > > + <0 0x50880000 0 0x200000>, That's enough redistributor space for 16 CPUs. However, you only describe 4. Either the number of CPUs is wrong, the size is wrong, or the GIC has been configured for more cores than the SoC has. > > + <0 0x50400000 0 0x2000>, > > + <0 0x50410000 0 0x2000>, > > + <0 0x50420000 0 0x2000>; > > Please order reg after compatible by convention, and sort > interrupt-controller or at least #interrupt-cells (applying to > consumers) last, after the below one applying to this device itself. > > > + interrupts = > + IRQ_TYPE_LEVEL_HIGH)>; > > + }; > > CC'ing Marc for additional GIC scrutiny, often the sizes are wrong. There is more than just sizes. The interrupt specifier for the maintenance interrupt is also wrong. M. -- Without deviation from the norm, progress is not possible.