From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EE0DFC4338F for ; Mon, 26 Jul 2021 10:05:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D42C460F11 for ; Mon, 26 Jul 2021 10:05:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233219AbhGZJZC (ORCPT ); Mon, 26 Jul 2021 05:25:02 -0400 Received: from mail.kernel.org ([198.145.29.99]:56968 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233245AbhGZJYl (ORCPT ); Mon, 26 Jul 2021 05:24:41 -0400 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 1D6E1603E7; Mon, 26 Jul 2021 10:05:10 +0000 (UTC) Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1m7xTw-00100G-4x; Mon, 26 Jul 2021 11:05:08 +0100 Date: Mon, 26 Jul 2021 11:05:07 +0100 Message-ID: <87r1fle6gc.wl-maz@kernel.org> From: Marc Zyngier To: Mark Kettenis Cc: devicetree@vger.kernel.org, robin.murphy@arm.com, sven@svenpeter.dev, Mark Kettenis , Hector Martin , Bjorn Helgaas , Rob Herring , linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 0/2] Apple M1 PCIe DT bindings In-Reply-To: <20210726083204.93196-1-mark.kettenis@xs4all.nl> References: <20210726083204.93196-1-mark.kettenis@xs4all.nl> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: mark.kettenis@xs4all.nl, devicetree@vger.kernel.org, robin.murphy@arm.com, sven@svenpeter.dev, kettenis@openbsd.org, marcan@marcan.st, bhelgaas@google.com, robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 26 Jul 2021 09:31:59 +0100, Mark Kettenis wrote: > > From: Mark Kettenis > > This small series adds bindings for the PCIe controller found on the > Apple M1 SoC. > > At this point, the primary consumer for these bindings is U-Boot. > With these bindings U-Boot can bring up the links for the root ports > of the PCIe root complex. A simple OS driver can then provide > standard ECAM access and manage MSI interrupts to provide access > to the built-in Ethernet and XHCI controllers of the Mac mini. > > The Apple controller incorporates Synopsys Designware PCIe logic > to implement its root port. But unlike other hardware currently > supported by U-Boot and the Linux kernel the Apple hardware > integrates multiple root ports. As such the existing bindings > for the DWC PCIe interface can't be used. There is a single ECAM > space for all root space, but separate GPIOs to take the PCI devices > on those ports out of reset. Therefore the standard "reset-gpio" and > "max-link-speed" properties appear on the child nodes representing > the PCI devices that correspond to the individual root ports. > > MSIs are handled by the PCIe controller and translated into "regular > interrupts". A range of 32 MSIs is provided. These 32 MSIs can be > distributed over the root ports as the OS sees fit by programming the > PCIe controller port registers. > > I still hope to hear from Marc Zyngier on the way MSIs are represented > in this binding. > > Patch 2/2 of this series depends on the pinctrl series I sent earlier > and will probably go through Hector Martin's Apple M1 SoC tree. > > > Changelog: > > v3: - Remove unneeded include in example > > v2: - Adjust name for ECAM in "reg-names" > - Drop "phy" registers > - Expand description > - Add description for "interrupts" > - Fix incorrect minItems for "interrupts" > - Fix incorrect MaxItems for "reg-names" > - Document the use of "msi-controller", "msi-parent", "iommu-map" and > "iommu-map-mask" > - Fix "bus-range" and "iommu-map" properties in the example > > Mark Kettenis (2): > dt-bindings: pci: Add DT bindings for apple,pcie > arm64: apple: Add PCIe node > > .../devicetree/bindings/pci/apple,pcie.yaml | 166 ++++++++++++++++++ > MAINTAINERS | 1 + > arch/arm64/boot/dts/apple/t8103.dtsi | 63 +++++++ > 3 files changed, 230 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pci/apple,pcie.yaml Thanks a log for doing this! For the whole series: Reviewed-by: Marc Zyngier M. -- Without deviation from the norm, progress is not possible.