From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.0 required=3.0 tests=BAYES_00,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EE7FEC433ED for ; Sat, 24 Apr 2021 09:07:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C94E561467 for ; Sat, 24 Apr 2021 09:07:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237527AbhDXJHk (ORCPT ); Sat, 24 Apr 2021 05:07:40 -0400 Received: from mail.kernel.org ([198.145.29.99]:48724 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238055AbhDXJHU (ORCPT ); Sat, 24 Apr 2021 05:07:20 -0400 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 0349B61131; Sat, 24 Apr 2021 09:06:43 +0000 (UTC) Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94) (envelope-from ) id 1laEFM-009DDW-Pi; Sat, 24 Apr 2021 10:06:41 +0100 Date: Sat, 24 Apr 2021 10:06:39 +0100 Message-ID: <87r1j0rqzk.wl-maz@kernel.org> From: Marc Zyngier To: Krishna Reddy Cc: Sumit Gupta , Jean-Philippe Brucker , "eric.auger@redhat.com" , "alex.williamson@redhat.com" , "eric.auger.pro@gmail.com" , "iommu@lists.linux-foundation.org" , "jiangkunkun@huawei.com" , "joro@8bytes.org" , "kvm@vger.kernel.org" , "kvmarm@lists.cs.columbia.edu" , "linux-kernel@vger.kernel.org" , "lushenming@huawei.com" , "robin.murphy@arm.com" , "tn@semihalf.com" , "vivek.gautam@arm.com" , Vikram Sethi , "wangxingang5@huawei.com" , "will@kernel.org" , "zhangfei.gao@linaro.org" , "zhukeqian1@huawei.com" , Sachin Nikam , Bibek Basu , Shanker Donthineni Subject: Re: [PATCH v14 00/13] SMMUv3 Nested Stage Setup (IOMMU part) In-Reply-To: References: <1619103878-6664-1-git-send-email-sumitg@nvidia.com> <5a8825bc-286e-b316-515f-3bd3c9c70a80@nvidia.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: vdumpa@nvidia.com, sumitg@nvidia.com, jean-philippe@linaro.org, eric.auger@redhat.com, alex.williamson@redhat.com, eric.auger.pro@gmail.com, iommu@lists.linux-foundation.org, jiangkunkun@huawei.com, joro@8bytes.org, kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, linux-kernel@vger.kernel.org, lushenming@huawei.com, robin.murphy@arm.com, tn@semihalf.com, vivek.gautam@arm.com, vsethi@nvidia.com, wangxingang5@huawei.com, will@kernel.org, zhangfei.gao@linaro.org, zhukeqian1@huawei.com, Snikam@nvidia.com, bbasu@nvidia.com, sdonthineni@nvidia.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 23 Apr 2021 18:58:23 +0100, Krishna Reddy wrote: > > >> Did that patch cause any issue, or is it just not needed on your system? > >> It fixes an hypothetical problem with the way ATS is implemented. > >> Maybe I actually observed it on an old software model, I don't > >> remember. Either way it's unlikely to go upstream but I'd like to know > >> if I should drop it from my tree. > > > Had to revert same patch "mm: notify remote TLBs when dirtying a PTE" to > > avoid below crash[1]. I am not sure about the cause yet. > > I have noticed this issue earlier with patch pointed here and root > caused the issue as below. It happens after vfio_mmap request from > QEMU for the PCIe device and during the access of VA when PTE access > flags are updated. > > kvm_mmu_notifier_change_pte() --> kvm_set_spte_hve() --> > kvm_set_spte_hva() --> clean_dcache_guest_page() > > The validation model doesn't have FWB capability supported. > __clean_dcache_guest_page() attempts to perform dcache flush on pcie > bar address(not a valid_pfn()) through page_address(), which doesn't > have page table mapping and leads to exception. > > I have worked around the issue by filtering out the request if the > pfn is not valid in __clean_dcache_guest_page(). As the patch > wasn't posted in the community, reverted it as well. That's papering over the real issue, and this mapping path needs fixing as it was only ever expected to be called for CoW. Can you please try the following patch and let me know if that fixes the issue for good? Thanks, M. diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c index 77cb2d28f2a4..b62dd40a4083 100644 --- a/arch/arm64/kvm/mmu.c +++ b/arch/arm64/kvm/mmu.c @@ -1147,7 +1147,8 @@ int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte) * We've moved a page around, probably through CoW, so let's treat it * just like a translation fault and clean the cache to the PoC. */ - clean_dcache_guest_page(pfn, PAGE_SIZE); + if (!kvm_is_device_pfn(pfn)) + clean_dcache_guest_page(pfn, PAGE_SIZE); handle_hva_to_gpa(kvm, hva, end, &kvm_set_spte_handler, &pfn); return 0; } -- Without deviation from the norm, progress is not possible.