From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED96AC46467 for ; Sun, 1 Jan 2023 22:46:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231208AbjAAWqF (ORCPT ); Sun, 1 Jan 2023 17:46:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39420 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229447AbjAAWqB (ORCPT ); Sun, 1 Jan 2023 17:46:01 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3591B1144; Sun, 1 Jan 2023 14:45:58 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id A6E7860E83; Sun, 1 Jan 2023 22:45:57 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 05DBBC433D2; Sun, 1 Jan 2023 22:45:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1672613157; bh=puCrFpi65CZPLTug1sTI/K7FXDEL7ysdynSiNUjiHjM=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=lLuv2sI0twxXXwFtob+q3T/m/TaGKcrYXNijV3Yd+gxuCFoTlwB4RqPisvZ8VjxmT +KBsHScrw7VSVqr/YaZPUB26i9YBmBMeonrZOZNCWQapTLT2PryaksSlfu9P3w9JLr XVFvBCAjOFlMoQaPwqJBDN9z2c3aNlyTJu30Meg/9AFlRKZ+Oob1jYFMz5iXcUZFJ2 glY/2+LvhrNXADNQIAroHgiiSCo6CAsX8aabbdOynUdlG6xkcqypvupo5h9/vlN2q7 gjbKK4wxKab8YVZYIbelu350fB+b2nefUkky888RkJouJkQ1koy4ZcFd2Ct8o/kBti 48PFeHB2b/ZgA== Received: from sofa.misterjones.org ([185.219.108.64] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1pC75W-00GEJt-OM; Sun, 01 Jan 2023 22:45:54 +0000 Date: Sun, 01 Jan 2023 22:44:39 +0000 Message-ID: <87sfgteuy0.wl-maz@kernel.org> From: Marc Zyngier To: Bernhard =?UTF-8?B?Um9zZW5rcsOkbnplcg==?= Cc: linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, matthias.bgg@gmail.com, krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org, gregkh@linuxfoundation.org, chunfeng.yun@mediatek.com, linus.walleij@linaro.org, lee@kernel.org, tglx@linutronix.de, angelogioacchino.delregno@collabora.com Subject: Re: [PATCH v6 7/7] arm64: dts: mediatek: Initial mt8365-evk support In-Reply-To: References: <20221230203541.146807-1-bero@baylibre.com> <20221230203541.146807-8-bero@baylibre.com> <87v8lsect3.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: bero@baylibre.com, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, matthias.bgg@gmail.com, krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org, gregkh@linuxfoundation.org, chunfeng.yun@mediatek.com, linus.walleij@linaro.org, lee@kernel.org, tglx@linutronix.de, angelogioacchino.delregno@collabora.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sun, 01 Jan 2023 21:57:58 +0000, Bernhard Rosenkr=C3=A4nzer wrote: >=20 > On Fri, Dec 30, 2022 at 11:41 PM Marc Zyngier wrote: > > > + gic: interrupt-controller@c000000 { > > > + compatible =3D "arm,gic-v3"; > > > + #interrupt-cells =3D <4>; > > > > Why 4 cells? All the SPIs routed via sysirq are perfectly happy with 3 > > cells, and all the PPIs have 0 for the 4th cell (none of them use any > > form of partitioning that'd require 4 cells). So where is this coming > > from? >=20 > It's coming from the SoC vendor kernel (and went unnoticed because > it happens to work). Will send an updated version that does the > right thing instead. I've been running it most of the day, so far > looking good. >=20 > > > + interrupt-parent =3D <&gic>; > > > + interrupt-controller; > > > + reg =3D <0 0x0c000000 0 0x80000>, <0 0x0c080000= 0 0x80000>; > > > + > > > > The first region is obviously wrong (512kB for the distributor? > > that's... most generous, but the architecture states that it is 64kB, > > and that's wasteful enough). > > > > This is also missing the GICC/GICH/GICV regions that Cortex-A53 > > implements, and that must be provided as per the binding. >=20 > This was also taken from the vendor kernel; unfortunately neiter the > datasheet for the SoC not the vendor kernel specifies the addresses > for GICC/GICH/GICV. > I've "guessed" based on what's in similar SoCs (MT8183, MT7986a) in > v7; this seems to work (boots, kvm initializes hyp mode properly). Please don't "guess", because this adds zero value, and we might as well run with the vendor crap instead. Read CBAR_EL1, and use this value to construct the memory map, as per the A53 TRM. Just booting with KVM enabled means nothing, as this is solely used at VM run time. You need run a full VM with GIC-2 emulation. M. --=20 Without deviation from the norm, progress is not possible.