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[98.179.76.75]) by smtp.gmail.com with ESMTPSA id b197sm36856qkg.65.2020.12.01.15.53.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Dec 2020 15:53:27 -0800 (PST) References: <20201015025002.87997-1-suravee.suthikulpanit@amd.com> User-agent: mu4e 1.4.10; emacs 27.1 From: Jerry Snitselaar To: Suravee Suthikulpanit Cc: linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org Subject: Re: [PATCH] iommu/amd: Increase interrupt remapping table limit to 512 entries In-reply-to: <20201015025002.87997-1-suravee.suthikulpanit@amd.com> Date: Tue, 01 Dec 2020 16:53:25 -0700 Message-ID: <87sg8pkrre.fsf@redhat.com> MIME-Version: 1.0 Content-Type: text/plain Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Suravee Suthikulpanit @ 2020-10-14 19:50 MST: > Certain device drivers allocate IO queues on a per-cpu basis. > On AMD EPYC platform, which can support up-to 256 cpu threads, > this can exceed the current MAX_IRQ_PER_TABLE limit of 256, > and result in the error message: > > AMD-Vi: Failed to allocate IRTE > > This has been observed with certain NVME devices. > > AMD IOMMU hardware can actually support upto 512 interrupt > remapping table entries. Therefore, update the driver to > match the hardware limit. > > Please note that this also increases the size of interrupt remapping > table to 8KB per device when using the 128-bit IRTE format. > > Signed-off-by: Suravee Suthikulpanit > --- > drivers/iommu/amd/amd_iommu_types.h | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h > index 30a5d412255a..427484c45589 100644 > --- a/drivers/iommu/amd/amd_iommu_types.h > +++ b/drivers/iommu/amd/amd_iommu_types.h > @@ -406,7 +406,11 @@ extern bool amd_iommu_np_cache; > /* Only true if all IOMMUs support device IOTLBs */ > extern bool amd_iommu_iotlb_sup; > > -#define MAX_IRQS_PER_TABLE 256 > +/* > + * AMD IOMMU hardware only support 512 IRTEs despite > + * the architectural limitation of 2048 entries. > + */ > +#define MAX_IRQS_PER_TABLE 512 > #define IRQ_TABLE_ALIGNMENT 128 > > struct irq_remap_table { With this change should DTE_IRQ_TABLE_LEN be changed to 9? IIUC the spec correctly leaving it at 8 is saying the table is 256 entries long. Regards, Jerry