From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 01288C4332D for ; Tue, 9 Mar 2021 09:11:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B79D965134 for ; Tue, 9 Mar 2021 09:11:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229805AbhCIJKw (ORCPT ); Tue, 9 Mar 2021 04:10:52 -0500 Received: from mail.kernel.org ([198.145.29.99]:49678 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229641AbhCIJK2 (ORCPT ); Tue, 9 Mar 2021 04:10:28 -0500 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 3FF0F6510B; Tue, 9 Mar 2021 09:10:28 +0000 (UTC) Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94) (envelope-from ) id 1lJYNm-000VLd-7H; Tue, 09 Mar 2021 09:10:26 +0000 Date: Tue, 09 Mar 2021 09:10:25 +0000 Message-ID: <87wnugy9oe.wl-maz@kernel.org> From: Marc Zyngier To: Qing Zhang Cc: Huacai Chen , Jiaxun Yang , Thomas Bogendoerfer , Thomas Gleixner , linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, wangming01@loongson.cn Subject: Re: [PATCH v3 5/7] irqchip/loongson-liointc: irqchip add 2.0 version In-Reply-To: <20210306023633.9579-6-zhangqing@loongson.cn> References: <20210306023633.9579-1-zhangqing@loongson.cn> <20210306023633.9579-6-zhangqing@loongson.cn> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: zhangqing@loongson.cn, chenhuacai@kernel.org, jiaxun.yang@flygoat.com, tsbogend@alpha.franken.de, tglx@linutronix.de, linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, wangming01@loongson.cn X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sat, 06 Mar 2021 02:36:31 +0000, Qing Zhang wrote: > > Add IO interrupt controller support for Loongson 2k1000, different > from the 3a series is that 2K1000 has 64 interrupt sources, 0-31 > correspond to the device tree liointc0 device node, and the other > correspond to liointc1 node. > > Signed-off-by: Jiaxun Yang > Signed-off-by: Qing Zhang > --- > > v2-v3: No change > > drivers/irqchip/irq-loongson-liointc.c | 55 +++++++++++++++++++++----- > 1 file changed, 46 insertions(+), 9 deletions(-) > > diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-loongson-liointc.c > index 09b91b81851c..1c3c80f7f9f5 100644 > --- a/drivers/irqchip/irq-loongson-liointc.c > +++ b/drivers/irqchip/irq-loongson-liointc.c > @@ -20,6 +20,7 @@ > > #define LIOINTC_CHIP_IRQ 32 > #define LIOINTC_NUM_PARENT 4 > +#define LIOINTC_NUM_CORES 4 > > #define LIOINTC_INTC_CHIP_START 0x20 > > @@ -42,6 +43,7 @@ struct liointc_handler_data { > struct liointc_priv { > struct irq_chip_generic *gc; > struct liointc_handler_data handler[LIOINTC_NUM_PARENT]; > + void __iomem *core_isr[LIOINTC_NUM_CORES]; > u8 map_cache[LIOINTC_CHIP_IRQ]; > bool has_lpc_irq_errata; > }; > @@ -51,11 +53,12 @@ static void liointc_chained_handle_irq(struct irq_desc *desc) > struct liointc_handler_data *handler = irq_desc_get_handler_data(desc); > struct irq_chip *chip = irq_desc_get_chip(desc); > struct irq_chip_generic *gc = handler->priv->gc; > + int core = get_ebase_cpunum() % LIOINTC_NUM_CORES; > u32 pending; > > chained_irq_enter(chip, desc); > > - pending = readl(gc->reg_base + LIOINTC_REG_INTC_STATUS); > + pending = readl(handler->priv->core_isr[core]); > > if (!pending) { > /* Always blame LPC IRQ if we have that bug */ > @@ -141,6 +144,15 @@ static void liointc_resume(struct irq_chip_generic *gc) > } > > static const char * const parent_names[] = {"int0", "int1", "int2", "int3"}; > +static const char * const core_reg_names[] = {"isr0", "isr1", "isr2", "isr3"}; > + > +static void __iomem *liointc_get_reg_byname(struct device_node *node, > + const char *name) > +{ > + int index = of_property_match_string(node, "reg-names", name); > + > + return of_iomap(node, index); So if of_property_match_string() returns an error, you feed that error to of_iomap()? Somehow, I don't think that's a good idea. > +} > > static int __init liointc_of_init(struct device_node *node, > struct device_node *parent) > @@ -159,10 +171,28 @@ static int __init liointc_of_init(struct device_node *node, > if (!priv) > return -ENOMEM; > > - base = of_iomap(node, 0); > - if (!base) { > - err = -ENODEV; > - goto out_free_priv; > + if (of_device_is_compatible(node, "loongson,liointc-2.0")) { > + base = liointc_get_reg_byname(node, "main"); > + if (!base) { > + err = -ENODEV; > + goto out_free_priv; > + } > + for (i = 0; i < LIOINTC_NUM_CORES; i++) { > + priv->core_isr[i] = > + liointc_get_reg_byname(node, core_reg_names[i]); Please write assignments on a single line. Thanks, M. -- Without deviation from the norm, progress is not possible.