From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A0E10CCA483 for ; Sat, 25 Jun 2022 16:09:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233304AbiFYQJs (ORCPT ); Sat, 25 Jun 2022 12:09:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44140 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233244AbiFYQJq (ORCPT ); Sat, 25 Jun 2022 12:09:46 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A133E11C13; Sat, 25 Jun 2022 09:09:45 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 638F8B80BFA; Sat, 25 Jun 2022 16:09:44 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0A36FC3411C; Sat, 25 Jun 2022 16:09:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1656173383; bh=zeQJlckF+GQVuKDzuLhjpGZA1Gm7C6kzkQw+hlgHt/8=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=WwTGWO7YdqG4nEqUw1EAmJ1/Luabn1ghQTVNWZAuLNakAcS2xWsvX//5xwWZ0OEKL 7+4Gw+LYqrdP6mRf0JLzm/Nypwt21YFIhnwxwQvT7tpS7WtoYzu29aM+4E8w/sNhNt 5Yq+ASIM6etEvPlQEqUZBwsW3hbrab2crzZ6z4RRG+wxIsx20Ft5qjxlONXkchpScW Bb+icgXKiK56qy0K7yMwif2NmUPu+JtoMRNo/62grI6N2IHMXVBf1X5YQ9gjzM88cA EKIMHLDPdSIGIkLI1cVhoEoR+deEyrjKzvvyYgCt+DLxRcZ7vq0NpcRnxz8zNXnT3H w7PZqJfL102pg== Received: from sofa.misterjones.org ([185.219.108.64] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1o58Ls-0035Sf-TC; Sat, 25 Jun 2022 17:09:41 +0100 Date: Sat, 25 Jun 2022 17:09:46 +0100 Message-ID: <87y1xkencl.wl-maz@kernel.org> From: Marc Zyngier To: "Lad, Prabhakar" Cc: Lad Prabhakar , Geert Uytterhoeven , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Linus Walleij , Bartosz Golaszewski , Thierry Reding , Jonathan Hunter , Bjorn Andersson , Andy Gross , Philipp Zabel , Andy Shevchenko , "open list:GPIO SUBSYSTEM" , linux-tegra , linux-arm-msm , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , LKML , Linux-Renesas , Phil Edworthy , Biju Das Subject: Re: [PATCH v5 2/5] irqchip: Add RZ/G2L IA55 Interrupt Controller driver In-Reply-To: References: <20220523174238.28942-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20220523174238.28942-3-prabhakar.mahadev-lad.rj@bp.renesas.com> <871qvdf5tb.wl-maz@kernel.org> <87fsjt2bep.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: prabhakar.csengg@gmail.com, prabhakar.mahadev-lad.rj@bp.renesas.com, geert+renesas@glider.be, tglx@linutronix.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linus.walleij@linaro.org, brgl@bgdev.pl, thierry.reding@gmail.com, jonathanh@nvidia.com, bjorn.andersson@linaro.org, agross@kernel.org, p.zabel@pengutronix.de, andy.shevchenko@gmail.com, linux-gpio@vger.kernel.org, linux-tegra@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, phil.edworthy@renesas.com, biju.das.jz@bp.renesas.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sat, 25 Jun 2022 13:48:08 +0100, "Lad, Prabhakar" wrote: > > Hi Marc, > > On Sat, Jun 25, 2022 at 1:08 PM Marc Zyngier wrote: > > > > On Sat, 25 Jun 2022 11:54:44 +0100, > > "Lad, Prabhakar" wrote: > > > > > > Hi Marc, > > > > > > Thank you for the review. > > > > > > On Sat, Jun 25, 2022 at 10:30 AM Marc Zyngier wrote: > > > > > > > > On Mon, 23 May 2022 18:42:35 +0100, > > > > Lad Prabhakar wrote: > > > > > > > > > [...] > > > > > > > +static int rzg2l_irqc_alloc(struct irq_domain *domain, unsigned int virq, > > > > > + unsigned int nr_irqs, void *arg) > > > > > +{ > > > > > + struct rzg2l_irqc_priv *priv = domain->host_data; > > > > > + unsigned long *chip_data = NULL; > > > > > > > > Why the init to NULL? > > > > > > > Can be dropped. > > > > > > > > + struct irq_fwspec spec; > > > > > + irq_hw_number_t hwirq; > > > > > + int tint = -EINVAL; > > > > > + unsigned int type; > > > > > + unsigned int i; > > > > > + int ret; > > > > > + > > > > > + ret = irq_domain_translate_twocell(domain, arg, &hwirq, &type); > > > > > + if (ret) > > > > > + return ret; > > > > > + > > > > > + /* > > > > > + * For TINT interrupts ie where pinctrl driver is child of irqc domain > > > > > + * the hwirq and TINT are encoded in fwspec->param[0]. > > > > > + * hwirq for TINT range from 9-40, hwirq is embedded 0-15 bits and TINT > > > > > + * from 16-31 bits. TINT from the pinctrl driver needs to be programmed > > > > > + * in IRQC registers to enable a given gpio pin as interrupt. > > > > > + */ > > > > > + if (hwirq > IRQC_IRQ_COUNT) { > > > > > + tint = TINT_EXTRACT_GPIOINT(hwirq); > > > > > + hwirq = TINT_EXTRACT_HWIRQ(hwirq); > > > > > + > > > > > + if (hwirq < IRQC_TINT_START) > > > > > + return -EINVAL; > > > > > + } > > > > > + > > > > > + if (hwirq > (IRQC_NUM_IRQ - 1)) > > > > > + return -EINVAL; > > > > > + > > > > > + chip_data = kzalloc(sizeof(*chip_data), GFP_KERNEL); > > > > > > > > Are we really allocating an unsigned long for something that already > > > > fits in something that is pointer-sized? > > > > > > > I think I received some feedback to use unsigned long. Let me know > > > what you want me to use here. > > > > I think this is just a waste of memory, but I don't really care. > > > Is there any better way I can handle it? How about (shock, horror) a cast? > > > > > > > > > + if (!chip_data) > > > > > + return -ENOMEM; > > > > > + *chip_data = tint; > > > > > > > > So here, *chip_data can be set to -EINVAL if hwirq <= IRQC_IRQ_COUNT? > > > > This can't be right. > > > > > > > Yes *chip_data can be -EINVAL. IRQC block handles IRQ0-7 and > > > GPIOINT0-122. So the -EINVAL here is for IRQ0-7 case were dont > > > required the chip data in the call backs hence -EINVAL, Whereas for > > > GPIOINT0-122 we need chip_data in the callbacks as this value needs to > > > be programmed in the hardware registers. > > > > I can't see anything that checks it (let alone the difference in > > types). And if it isn't checked, this means that the allocation is > > pointless. > > > There are checks for example below: > > static void rzg2l_irqc_irq_enable(struct irq_data *d) > { > unsigned int hw_irq = irqd_to_hwirq(d); > > if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) { > struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); > unsigned long chip_data = *(unsigned long *)d->chip_data; > u32 offset = hw_irq - IRQC_TINT_START; > u32 tssr_offset = TSSR_OFFSET(offset); > u8 tssr_index = TSSR_INDEX(offset); > u32 reg; > > raw_spin_lock(&priv->lock); > reg = readl_relaxed(priv->base + TSSR(tssr_index)); > reg |= (TIEN | chip_data) << TSSEL_SHIFT(tssr_offset); > writel_relaxed(reg, priv->base + TSSR(tssr_index)); > raw_spin_unlock(&priv->lock); > } > irq_chip_enable_parent(d); > } > > This check hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ here > would mean its GPIOINT0-122 and then the chip data will be used. That doesn't check the content of chip_data if outside of this condition. Nonetheless, you allocate an unsigned long to store -EINVAL. Not only this is a pointless allocation, but you use it to store something that you never retrieve the first place. Don't you see the problem? M. -- Without deviation from the norm, progress is not possible.