From: Thomas Gleixner <tglx@linutronix.de>
To: Balbir Singh <sblbir@amazon.com>, linux-kernel@vger.kernel.org
Cc: jpoimboe@redhat.com, tony.luck@intel.com, keescook@chromium.org,
benh@kernel.crashing.org, x86@kernel.org, dave.hansen@intel.com,
Balbir Singh <sblbir@amazon.com>
Subject: Re: [PATCH v3 2/5] arch/x86: Refactor tlbflush and l1d flush
Date: Fri, 17 Apr 2020 15:03:26 +0200 [thread overview]
Message-ID: <87y2qul0wx.fsf@nanos.tec.linutronix.de> (raw)
In-Reply-To: <20200408090229.16467-3-sblbir@amazon.com>
Balbir Singh <sblbir@amazon.com> writes:
> +void populate_tlb_with_flush_pages(void *l1d_flush_pages);
> +void flush_l1d_cache_sw(void *l1d_flush_pages);
> +int flush_l1d_cache_hw(void);
l1d_flush_populate_pages();
l1d_flush_sw()
l1d_flush_hw()
Hmm?
> +void populate_tlb_with_flush_pages(void *l1d_flush_pages)
> +{
> + int size = PAGE_SIZE << L1D_CACHE_ORDER;
> +
> + asm volatile(
> + /* First ensure the pages are in the TLB */
> + "xorl %%eax, %%eax\n"
> + ".Lpopulate_tlb:\n\t"
> + "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
> + "addl $4096, %%eax\n\t"
> + "cmpl %%eax, %[size]\n\t"
> + "jne .Lpopulate_tlb\n\t"
> + "xorl %%eax, %%eax\n\t"
> + "cpuid\n\t"
> + :: [flush_pages] "r" (l1d_flush_pages),
> + [size] "r" (size)
> + : "eax", "ebx", "ecx", "edx");
> +}
> +EXPORT_SYMBOL_GPL(populate_tlb_with_flush_pages);
I probably missed the fine print in the change log why this is separate
from the SW flush function.
> +int flush_l1d_cache_hw(void)
> +{
> + if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
> + wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
> + return 0;
> + }
> + return -ENOTSUPP;
> +}
> +EXPORT_SYMBOL_GPL(flush_l1d_cache_hw);
along with the explanation why this needs to be two functions.
> - if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
> - wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
> + if (flush_l1d_cache_hw() == 0)
> return;
> - }
if (!l1d_flush_hw())
return;
> - asm volatile(
> - /* First ensure the pages are in the TLB */
> - "xorl %%eax, %%eax\n"
> - ".Lpopulate_tlb:\n\t"
> - "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
> - "addl $4096, %%eax\n\t"
> - "cmpl %%eax, %[size]\n\t"
> - "jne .Lpopulate_tlb\n\t"
> - "xorl %%eax, %%eax\n\t"
> - "cpuid\n\t"
> - /* Now fill the cache */
> - "xorl %%eax, %%eax\n"
> - ".Lfill_cache:\n"
> - "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
> - "addl $64, %%eax\n\t"
> - "cmpl %%eax, %[size]\n\t"
> - "jne .Lfill_cache\n\t"
> - "lfence\n"
> - :: [flush_pages] "r" (vmx_l1d_flush_pages),
> - [size] "r" (size)
> - : "eax", "ebx", "ecx", "edx");
> + preempt_disable();
> + populate_tlb_with_flush_pages(vmx_l1d_flush_pages);
> + flush_l1d_cache_sw(vmx_l1d_flush_pages);
> + preempt_enable();
The preempt_disable/enable was not there before, right? Why do we need
that now? If this is a fix, then that should be a separate patch.
Thanks,
tglx
next prev parent reply other threads:[~2020-04-17 13:03 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-08 9:02 [PATCH v3 0/5] Optionally flush L1D on context switch Balbir Singh
2020-04-08 9:02 ` [PATCH v3 1/5] arch/x86/kvm: Refactor l1d flush lifecycle management Balbir Singh
2020-04-17 12:57 ` Thomas Gleixner
2020-04-17 22:34 ` Singh, Balbir
2020-04-08 9:02 ` [PATCH v3 2/5] arch/x86: Refactor tlbflush and l1d flush Balbir Singh
2020-04-17 13:03 ` Thomas Gleixner [this message]
2020-04-17 22:58 ` Singh, Balbir
2020-04-08 9:02 ` [PATCH v3 3/5] arch/x86/mm: Refactor cond_ibpb() to support other use cases Balbir Singh
2020-04-17 13:07 ` Thomas Gleixner
2020-04-17 23:02 ` Singh, Balbir
2020-04-18 9:59 ` Thomas Gleixner
2020-04-21 3:46 ` Singh, Balbir
2020-04-21 9:02 ` Thomas Gleixner
2020-04-08 9:02 ` [PATCH v3 4/5] arch/x86: Optionally flush L1D on context switch Balbir Singh
2020-04-17 14:41 ` Thomas Gleixner
2020-04-18 1:30 ` Singh, Balbir
2020-04-18 10:17 ` Thomas Gleixner
2020-04-20 0:24 ` Singh, Balbir
2020-04-08 9:02 ` [PATCH v3 5/5] arch/x86: Add L1D flushing Documentation Balbir Singh
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