From: Jianmin Lv <lvjianmin@loongson.cn>
To: Huacai Chen <chenhuacai@kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>,
Marc Zyngier <maz@kernel.org>,
LKML <linux-kernel@vger.kernel.org>,
loongarch@lists.linux.dev, Hanjun Guo <guohanjun@huawei.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Jiaxun Yang <jiaxun.yang@flygoat.com>,
Huacai Chen <chenhuacai@loongson.cn>
Subject: Re: [PATCH V16 09/14] irqchip/loongson-pch-msi: Add ACPI init support
Date: Tue, 19 Jul 2022 21:40:48 +0800 [thread overview]
Message-ID: <88a83517-cb6a-b833-8282-051bacfcb110@loongson.cn> (raw)
In-Reply-To: <CAAhV-H5SVZV5RKhegWNOovSQN9ez_qZKuPUD8NkXwy-xd2MWRQ@mail.gmail.com>
On 2022/7/19 上午10:40, Huacai Chen wrote:
> Hi, Jianmin,
>
> On Mon, Jul 18, 2022 at 10:21 PM Jianmin Lv <lvjianmin@loongson.cn> wrote:
>>
>> From: Huacai Chen <chenhuacai@loongson.cn>
>>
>> PCH-PIC/PCH-MSI stands for "Interrupt Controller" that described in
>> Section 5 of "Loongson 7A1000 Bridge User Manual". For more information
>> please refer Documentation/loongarch/irq-chip-model.rst.
>>
>> Co-developed-by: Jianmin Lv <lvjianmin@loongson.cn>
>> Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
>> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
>> ---
>> arch/loongarch/include/asm/irq.h | 12 ++-
>> arch/loongarch/kernel/irq.c | 1 -
>> drivers/irqchip/irq-loongson-pch-msi.c | 131 ++++++++++++++++++++++-----------
>> 3 files changed, 99 insertions(+), 45 deletions(-)
>>
>> diff --git a/arch/loongarch/include/asm/irq.h b/arch/loongarch/include/asm/irq.h
>> index 74fef60..3e61824 100644
>> --- a/arch/loongarch/include/asm/irq.h
>> +++ b/arch/loongarch/include/asm/irq.h
>> @@ -106,11 +106,20 @@ struct irq_domain *htvec_acpi_init(struct irq_domain *parent,
>> struct acpi_madt_ht_pic *acpi_htvec);
>> int pch_lpc_acpi_init(struct irq_domain *parent,
>> struct acpi_madt_lpc_pic *acpi_pchlpc);
>> -struct irq_domain *pch_msi_acpi_init(struct irq_domain *parent,
>> +#if IS_ENABLED(CONFIG_LOONGSON_PCH_MSI)
>> +int pch_msi_acpi_init(struct irq_domain *parent,
>> struct acpi_madt_msi_pic *acpi_pchmsi);
>> +#else
>> +static inline int pch_msi_acpi_init(struct irq_domain *parent,
>> + struct acpi_madt_msi_pic *acpi_pchmsi)
>> +{
>> + return 0;
>> +}
>> +#endif
>> int pch_pic_acpi_init(struct irq_domain *parent,
>> struct acpi_madt_bio_pic *acpi_pchpic);
>> int find_pch_pic(u32 gsi);
>> +struct fwnode_handle *get_pch_msi_handle(int pci_segment);
>>
>> extern struct acpi_madt_lio_pic *acpi_liointc;
>> extern struct acpi_madt_eio_pic *acpi_eiointc[MAX_IO_PICS];
>> @@ -123,7 +132,6 @@ int pch_pic_acpi_init(struct irq_domain *parent,
>> extern struct irq_domain *cpu_domain;
>> extern struct irq_domain *liointc_domain;
>> extern struct fwnode_handle *pch_lpc_handle;
>> -extern struct irq_domain *pch_msi_domain[MAX_IO_PICS];
>> extern struct fwnode_handle *pch_pic_handle[MAX_IO_PICS];
>>
>> extern irqreturn_t loongson3_ipi_interrupt(int irq, void *dev);
>> diff --git a/arch/loongarch/kernel/irq.c b/arch/loongarch/kernel/irq.c
>> index 866b2ee..ce21281 100644
>> --- a/arch/loongarch/kernel/irq.c
>> +++ b/arch/loongarch/kernel/irq.c
>> @@ -27,7 +27,6 @@
>>
>> struct irq_domain *cpu_domain;
>> struct irq_domain *liointc_domain;
>> -struct irq_domain *pch_msi_domain[MAX_IO_PICS];
>>
>> /*
>> * 'what should we do if we get a hw irq event on an illegal vector'.
>> diff --git a/drivers/irqchip/irq-loongson-pch-msi.c b/drivers/irqchip/irq-loongson-pch-msi.c
>> index e3801c4..b3f1f8e 100644
>> --- a/drivers/irqchip/irq-loongson-pch-msi.c
>> +++ b/drivers/irqchip/irq-loongson-pch-msi.c
>> @@ -15,6 +15,8 @@
>> #include <linux/pci.h>
>> #include <linux/slab.h>
>>
>> +static int nr_pics;
>> +
>> struct pch_msi_data {
>> struct mutex msi_map_lock;
>> phys_addr_t doorbell;
>> @@ -23,6 +25,8 @@ struct pch_msi_data {
>> unsigned long *msi_map;
>> };
>>
>> +static struct fwnode_handle *pch_msi_handle[MAX_IO_PICS];
>> +
>> static void pch_msi_mask_msi_irq(struct irq_data *d)
>> {
>> pci_msi_mask_irq(d);
>> @@ -154,12 +158,12 @@ static void pch_msi_middle_domain_free(struct irq_domain *domain,
>> };
>>
>> static int pch_msi_init_domains(struct pch_msi_data *priv,
>> - struct device_node *node,
>> - struct irq_domain *parent)
>> + struct irq_domain *parent,
>> + struct fwnode_handle *domain_handle)
>> {
>> struct irq_domain *middle_domain, *msi_domain;
>>
>> - middle_domain = irq_domain_create_linear(of_node_to_fwnode(node),
>> + middle_domain = irq_domain_create_linear(domain_handle,
>> priv->num_irqs,
>> &pch_msi_middle_domain_ops,
>> priv);
>> @@ -171,7 +175,7 @@ static int pch_msi_init_domains(struct pch_msi_data *priv,
>> middle_domain->parent = parent;
>> irq_domain_update_bus_token(middle_domain, DOMAIN_BUS_NEXUS);
>>
>> - msi_domain = pci_msi_create_irq_domain(of_node_to_fwnode(node),
>> + msi_domain = pci_msi_create_irq_domain(domain_handle,
>> &pch_msi_domain_info,
>> middle_domain);
>> if (!msi_domain) {
>> @@ -183,19 +187,11 @@ static int pch_msi_init_domains(struct pch_msi_data *priv,
>> return 0;
>> }
>>
>> -static int pch_msi_init(struct device_node *node,
>> - struct device_node *parent)
>> +static int pch_msi_init(phys_addr_t msg_address, int irq_base, int irq_count,
>> + struct irq_domain *parent_domain, struct fwnode_handle *domain_handle)
>> {
>> - struct pch_msi_data *priv;
>> - struct irq_domain *parent_domain;
>> - struct resource res;
>> int ret;
>> -
>> - parent_domain = irq_find_host(parent);
>> - if (!parent_domain) {
>> - pr_err("Failed to find the parent domain\n");
>> - return -ENXIO;
>> - }
>> + struct pch_msi_data *priv;
>>
>> priv = kzalloc(sizeof(*priv), GFP_KERNEL);
>> if (!priv)
>> @@ -203,48 +199,99 @@ static int pch_msi_init(struct device_node *node,
>>
>> mutex_init(&priv->msi_map_lock);
>>
>> - ret = of_address_to_resource(node, 0, &res);
>> - if (ret) {
>> - pr_err("Failed to allocate resource\n");
>> - goto err_priv;
>> - }
>> -
>> - priv->doorbell = res.start;
>> -
>> - if (of_property_read_u32(node, "loongson,msi-base-vec",
>> - &priv->irq_first)) {
>> - pr_err("Unable to parse MSI vec base\n");
>> - ret = -EINVAL;
>> - goto err_priv;
>> - }
>> -
>> - if (of_property_read_u32(node, "loongson,msi-num-vecs",
>> - &priv->num_irqs)) {
>> - pr_err("Unable to parse MSI vec number\n");
>> - ret = -EINVAL;
>> - goto err_priv;
>> - }
>> + priv->doorbell = msg_address;
>> + priv->irq_first = irq_base;
>> + priv->num_irqs = irq_count;
>>
>> priv->msi_map = bitmap_zalloc(priv->num_irqs, GFP_KERNEL);
>> - if (!priv->msi_map) {
>> - ret = -ENOMEM;
>> + if (!priv->msi_map)
>> goto err_priv;
>> - }
>>
>> pr_debug("Registering %d MSIs, starting at %d\n",
>> priv->num_irqs, priv->irq_first);
>>
>> - ret = pch_msi_init_domains(priv, node, parent_domain);
>> + ret = pch_msi_init_domains(priv, parent_domain, domain_handle);
>> if (ret)
>> goto err_map;
>>
>> + pch_msi_handle[nr_pics++] = domain_handle;
>> return 0;
>>
>> err_map:
>> bitmap_free(priv->msi_map);
>> err_priv:
>> kfree(priv);
>> - return ret;
>> +
>> + return -EINVAL;
>> +}
>> +
>> +#ifdef CONFIG_OF
>> +static int pch_msi_of_init(struct device_node *node, struct device_node *parent)
>> +{
>> + int err;
>> + int irq_base, irq_count;
>> + struct resource res;
>> + struct irq_domain *parent_domain;
>> +
>> + parent_domain = irq_find_host(parent);
>> + if (!parent_domain) {
>> + pr_err("Failed to find the parent domain\n");
>> + return -ENXIO;
>> + }
>> +
>> + if (of_address_to_resource(node, 0, &res)) {
>> + pr_err("Failed to allocate resource\n");
>> + return -EINVAL;
>> + }
>> +
>> + if (of_property_read_u32(node, "loongson,msi-base-vec", &irq_base)) {
>> + pr_err("Unable to parse MSI vec base\n");
>> + return -EINVAL;
>> + }
>> +
>> + if (of_property_read_u32(node, "loongson,msi-num-vecs", &irq_count)) {
>> + pr_err("Unable to parse MSI vec number\n");
>> + return -EINVAL;
>> + }
>> +
>> + err = pch_msi_init(res.start, irq_base, irq_count, parent_domain, of_node_to_fwnode(node));
>> + if (err < 0)
>> + return err;
>> +
>> + return 0;
>> +}
>> +
>> +IRQCHIP_DECLARE(pch_msi, "loongson,pch-msi-1.0", pch_msi_of_init);
>> +#endif
>> +
>> +#ifdef CONFIG_ACPI
>> +struct fwnode_handle *get_pch_msi_handle(int pci_segment)
>> +{
>> + int i;
>> +
>> + for (i = 0; i < MAX_IO_PICS; i++) {
>> + if (msi_group[i].pci_segment == pci_segment)
>> + return pch_msi_handle[i];
>> + }
>> + return NULL;
>> }
> Not sure, but it seems this function should not be ACPI-specific.
>
We only support multiple bridges for ACPI on LoongArch machine, so
it's ACPI-specific.
> Huacai
>>
>> -IRQCHIP_DECLARE(pch_msi, "loongson,pch-msi-1.0", pch_msi_init);
>> +int __init pch_msi_acpi_init(struct irq_domain *parent,
>> + struct acpi_madt_msi_pic *acpi_pchmsi)
>> +{
>> + int ret;
>> + struct fwnode_handle *domain_handle;
>> +
>> + if (!acpi_pchmsi)
>> + return -EINVAL;
>> +
>> + domain_handle = irq_domain_alloc_fwnode((phys_addr_t *)acpi_pchmsi);
>> +
>> + ret = pch_msi_init(acpi_pchmsi->msg_address, acpi_pchmsi->start,
>> + acpi_pchmsi->count, parent, domain_handle);
>> + if (ret < 0)
>> + irq_domain_free_fwnode(domain_handle);
>> +
>> + return ret;
>> +}
>> +#endif
>> --
>> 1.8.3.1
>>
>>
next prev parent reply other threads:[~2022-07-19 14:21 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-18 14:13 [PATCH V16 00/14] irqchip: Add LoongArch-related irqchip drivers Jianmin Lv
2022-07-18 14:13 ` [PATCH V16 01/14] LoongArch: Provisionally add ACPICA data structures Jianmin Lv
2022-07-18 14:13 ` [PATCH V16 02/14] APCI: irq: Add support for multiple GSI domains Jianmin Lv
2022-07-18 14:13 ` [PATCH V16 03/14] ACPI: irq: Allow acpi_gsi_to_irq() to have an arch-specific fallback Jianmin Lv
2022-07-18 14:13 ` [PATCH V16 04/14] genirq/generic_chip: export irq_unmap_generic_chip Jianmin Lv
2022-07-18 14:13 ` [PATCH V16 05/14] LoongArch: Use ACPI_GENERIC_GSI for gsi handling Jianmin Lv
2022-07-18 15:19 ` Huacai Chen
2022-07-18 14:13 ` [PATCH V16 06/14] irqchip: Add Loongson PCH LPC controller support Jianmin Lv
2022-07-18 14:13 ` [PATCH V16 07/14] irqchip: remove COMPILE_TEST for pch-pic and pch-msi Jianmin Lv
2022-07-19 1:06 ` Huacai Chen
2022-07-19 13:42 ` Jianmin Lv
2022-07-18 14:13 ` [PATCH V16 08/14] irqchip/loongson-pch-pic: Add ACPI init support Jianmin Lv
2022-07-18 15:27 ` Huacai Chen
2022-07-19 13:42 ` Jianmin Lv
2022-07-19 3:15 ` Huacai Chen
2022-07-19 13:37 ` Jianmin Lv
2022-07-18 14:13 ` [PATCH V16 09/14] irqchip/loongson-pch-msi: " Jianmin Lv
2022-07-19 2:40 ` Huacai Chen
2022-07-19 13:40 ` Jianmin Lv [this message]
2022-07-18 14:13 ` [PATCH V16 10/14] irqchip/loongson-liointc: " Jianmin Lv
2022-07-18 14:13 ` [PATCH V16 11/14] LoongArch: prepare to support multiple pch-pic and pch-msi irqdomain Jianmin Lv
2022-07-19 2:38 ` Huacai Chen
2022-07-19 13:41 ` Jianmin Lv
2022-07-18 14:13 ` [PATCH V16 12/14] irqchip: Add Loongson Extended I/O interrupt controller support Jianmin Lv
2022-07-18 14:13 ` [PATCH V16 13/14] irqchip: Add LoongArch CPU " Jianmin Lv
2022-07-18 15:21 ` Huacai Chen
2022-07-19 13:43 ` Jianmin Lv
2022-07-18 14:13 ` [PATCH V16 14/14] irqchip / ACPI: Introduce ACPI_IRQ_MODEL_LPIC for LoongArch Jianmin Lv
2022-07-19 2:25 ` Huacai Chen
2022-07-19 13:41 ` Jianmin Lv
2022-07-19 22:40 ` kernel test robot
2022-07-19 1:12 ` [PATCH V16 00/14] irqchip: Add LoongArch-related irqchip drivers Huacai Chen
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