RE: [PATCH 1/1] x86: Change mov $0, %reg with xor %reg, %reg

From: David Laight <David.Laight@ACULAB.COM>
To: "'H. Peter Anvin'" <hpa@zytor.com>,
	'Kanna Scarlet' <knscarlet@gnuweeb.org>,
	Borislav Petkov <bp@alien8.de>
Cc: Thomas Gleixner <tglx@linutronix.de>,
	Ingo Molnar <mingo@redhat.com>,
	"Dave Hansen" <dave.hansen@linux.intel.com>,
	"x86@kernel.org" <x86@kernel.org>,
	"Ard Biesheuvel" <ardb@kernel.org>,
	Bill Metzenthen <billm@melbpc.org.au>,
	"Brijesh Singh" <brijesh.singh@amd.com>,
	Joerg Roedel <jroedel@suse.de>,
	Josh Poimboeuf <jpoimboe@kernel.org>,
	"Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>,
	Mark Rutland <mark.rutland@arm.com>,
	Michael Roth <michael.roth@amd.com>,
	Peter Zijlstra <peterz@infradead.org>,
	Sean Christopherson <seanjc@google.com>,
	Steven Rostedt <rostedt@goodmis.org>,
	Ammar Faizi <ammarfaizi2@gnuweeb.org>,
	"GNU/Weeb Mailing List" <gwml@vger.gnuweeb.org>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
Subject: RE: [PATCH 1/1] x86: Change mov $0, %reg with xor %reg, %reg
Date: Tue, 9 Aug 2022 07:38:35 +0000	[thread overview]
Message-ID: <88f681a6c18944588676f93be10ba1b2@AcuMS.aculab.com> (raw)
In-Reply-To: <b71d4c4a-10be-a1f5-a95c-90b36e57230a@zytor.com>

From: H. Peter Anvin
> Sent: 08 August 2022 20:00
> 
> On August 5, 2022 2:26:02 AM PDT, David Laight <David.Laight@ACULAB.COM>
> wrote:
> >From: Kanna Scarlet
> >> Sent: 04 August 2022 19:08
> >>
> >> On 8/4/22 10:53 PM, Borislav Petkov wrote:
> >> > Bonus points if you find out what other advantage
> >> >
> >> > XOR reg,reg
> >> >
> >> > has when it comes to clearing integer registers.
> >>
> >> Hello sir Borislav,
> >>
> >> Thank you for your response. I tried to find out other advantages of
> >> xor reg,reg on Google and found this:
> >> https://stackoverflow.com/a/33668295/7275114
> >>
> >>   "xor (being a recognized zeroing idiom, unlike mov reg, 0) has some
> >>   obvious and some subtle advantages:
> >>
> >>   1. smaller code-size than mov reg,0. (All CPUs)
> >>   2. avoids partial-register penalties for later code.
> >>      (Intel P6-family and SnB-family).
> >>   3. doesn't use an execution unit, saving power and freeing up
> >>      execution resources. (Intel SnB-family)
> >>   4. smaller uop (no immediate data) leaves room in the uop cache-line
> >>      for nearby instructions to borrow if needed. (Intel SnB-family).
> >>   5. doesn't use up entries in the physical register file. (Intel
> >>      SnB-family (and P4) at least, possibly AMD as well since they use
> >>      a similar PRF design instead of keeping register state in the ROB
> >>      like Intel P6-family microarchitectures.)"
> >
> >You missed one, and an additional change:
> >
> >Use "xor %rax,%rax" instead of "xor %eax,%eax" to save
> >the 'reg' prefix.
> >
> >	David
> >
> >-
> >Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, UK
> >Registration No: 1397386 (Wales)
> >
> >
> 
> You mean the other way around...

Maybe :-(
The 32bit versions are best.
Somehow the register naming convention ended up getting sort of 'backwards'.
'register' is bigger than 'extended'.
I've 'only' been writing x86 asm since 1982!

	David

-
Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, UK
Registration No: 1397386 (Wales)