From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.3 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A, SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F3EC5C83014 for ; Wed, 2 Dec 2020 13:00:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B42912222C for ; Wed, 2 Dec 2020 13:00:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730027AbgLBNAy (ORCPT ); Wed, 2 Dec 2020 08:00:54 -0500 Received: from szxga06-in.huawei.com ([45.249.212.32]:8495 "EHLO szxga06-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727531AbgLBNAx (ORCPT ); Wed, 2 Dec 2020 08:00:53 -0500 Received: from DGGEMS410-HUB.china.huawei.com (unknown [172.30.72.58]) by szxga06-in.huawei.com (SkyGuard) with ESMTP id 4CmJw55c63zhlpC; Wed, 2 Dec 2020 20:59:49 +0800 (CST) Received: from [10.174.185.226] (10.174.185.226) by DGGEMS410-HUB.china.huawei.com (10.3.19.210) with Microsoft SMTP Server id 14.3.487.0; Wed, 2 Dec 2020 21:00:01 +0800 To: Auger Eric CC: , , , , , , , , , , , , , References: <20201118112151.25412-8-eric.auger@redhat.com> <1606829590-25924-1-git-send-email-wangxingang5@huawei.com> <2e69adf5-8207-64f7-fa8e-9f2bd3a3c4e3@redhat.com> From: Wang Xingang Subject: Re: [PATCH v13 07/15] iommu/smmuv3: Allow stage 1 invalidation with unmanaged ASIDs Message-ID: <8cf8fa21-41e3-f3f9-81e4-90f0bfc26fc0@huawei.com> Date: Wed, 2 Dec 2020 20:59:52 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.5.1 MIME-Version: 1.0 In-Reply-To: <2e69adf5-8207-64f7-fa8e-9f2bd3a3c4e3@redhat.com> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit X-Originating-IP: [10.174.185.226] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Thanks for your reply. We are testing vSVA, and will let you know if other problems are found. On 2020/12/1 21:58, Auger Eric wrote: > Hi Xingang, > > On 12/1/20 2:33 PM, Xingang Wang wrote: >> Hi Eric >> >> On Wed, 18 Nov 2020 12:21:43, Eric Auger wrote: >>> @@ -1710,7 +1710,11 @@ static void arm_smmu_tlb_inv_context(void *cookie) >>> * insertion to guarantee those are observed before the TLBI. Do be >>> * careful, 007. >>> */ >>> - if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) { >>> + if (ext_asid >= 0) { /* guest stage 1 invalidation */ >>> + cmd.opcode = CMDQ_OP_TLBI_NH_ASID; >>> + cmd.tlbi.asid = ext_asid; >>> + cmd.tlbi.vmid = smmu_domain->s2_cfg.vmid; >>> + } else if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) { >> >> Found a problem here, the cmd for guest stage 1 invalidation is built, >> but it is not delivered to smmu. >> > > Thank you for the report. I will fix that soon. With that fixed, have > you been able to run vSVA on top of the series. Do you need other stuff > to be fixed at SMMU level? As I am going to respin soon, please let me > know what is the best branch to rebase to alleviate your integration. > > Best Regards > > Eric > > . >