From: Jonathan Marek <jonathan@marek.ca>
To: Akhil P Oommen <akhilpo@codeaurora.org>, freedreno@lists.freedesktop.org
Cc: Rob Clark <robdclark@gmail.com>, Sean Paul <sean@poorly.run>,
David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
Jordan Crouse <jordan@cosmicpenguin.net>,
Eric Anholt <eric@anholt.net>,
Sharat Masetty <smasetty@codeaurora.org>,
Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>,
Douglas Anderson <dianders@chromium.org>,
kbuild test robot <lkp@intel.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@somainline.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Shawn Guo <shawn.guo@linaro.org>,
Konrad Dybcio <konrad.dybcio@somainline.org>,
"open list:DRM DRIVER FOR MSM ADRENO GPU"
<linux-arm-msm@vger.kernel.org>,
"open list:DRM DRIVER FOR MSM ADRENO GPU"
<dri-devel@lists.freedesktop.org>,
open list <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 6/8] drm/msm/a6xx: add support for Adreno 660 GPU
Date: Tue, 8 Jun 2021 12:53:44 -0400 [thread overview]
Message-ID: <8dd37a7b-b58f-3cf6-346e-ca5add2a163c@marek.ca> (raw)
In-Reply-To: <055b924e-43fe-1b2b-7292-43a88f9798c2@codeaurora.org>
On 5/31/21 11:05 AM, Akhil P Oommen wrote:
> On 5/13/2021 10:44 PM, Jonathan Marek wrote:
...
>> @@ -519,7 +519,7 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
>> if (!pdcptr)
>> goto err;
>> - if (adreno_is_a650(adreno_gpu))
>> + if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu))
>
> why not adreno_is_a650_family() here?
>
Based on downstream, a620 is part of a650_family but does not have
pdc_in_aop flag.
>> @@ -751,7 +751,7 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu,
>> unsigned int state)
>> int ret;
>> u32 chipid;
> We need to program this register here:
> gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF, 1);
>
msm-4.19 does not have this write for a650, but msm-5.4 then adds it.
Will make it a separate change since it affects a650 and not just a660.
>> - if (adreno_is_a650(adreno_gpu))
>> + if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu))
>> gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF, 1);
>> if (state == GMU_WARM_BOOT) {
>> @@ -1494,12 +1494,28 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu,
>> struct device_node *node)
>> if (ret)
>> goto err_put_device;
>> +
>> + /* A660 now requires handling "prealloc requests" in GMU firmware
>> + * For now just hardcode allocations based on the known firmware.
>> + * note: there is no indication that these correspond to "dummy" or
>> + * "debug" regions, but this "guess" allows reusing these BOs which
>> + * are otherwise unused by a660.
>> + */
>> + gmu->dummy.size = SZ_4K;
>> + if (adreno_is_a660(adreno_gpu)) {
>> + ret = a6xx_gmu_memory_alloc(gmu, &gmu->debug, SZ_4K * 7,
>> 0x60400000);
>> + if (ret)
>> + goto err_memory;
>
> I think we can simply ignore this allocation for a660 because it was
> required for an unused feature. Do you see any issue if you ignore this
> allocation?
>
Yes, without it there will be an error:
arm-smmu 3da0000.iommu: Unhandled context fault: fsr=0x402,
iova=0x60400000, fsynr=0x32, cbfrsynra=0x5, cb=2
>> +
>> + gmu->dummy.size = SZ_8K;
>> + }
>> +
>> /* Allocate memory for the GMU dummy page */
>> - ret = a6xx_gmu_memory_alloc(gmu, &gmu->dummy, SZ_4K, 0x60000000);
>> + ret = a6xx_gmu_memory_alloc(gmu, &gmu->dummy, gmu->dummy.size,
>> 0x60000000);
>> if (ret)
>> goto err_memory;
>> - if (adreno_is_a650(adreno_gpu)) {
>> + if (adreno_is_a650_family(adreno_gpu)) {
>> ret = a6xx_gmu_memory_alloc(gmu, &gmu->icache,
>> SZ_16M - SZ_16K, 0x04000);
>> if (ret)
>> @@ -885,6 +937,13 @@ static int a6xx_hw_init(struct msm_gpu *gpu)
>> /* Protect registers from the CP */
>> a6xx_set_cp_protect(gpu);
>> + if (adreno_is_a660(adreno_gpu)) {
>> + gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, 0x1);
>> + gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x0);
>> + /* Set dualQ + disable afull for A660 GPU but not for A635 */
>> + gpu_write(gpu, REG_A6XX_UCHE_CMDQ_CONFIG, 0x66906);
>> + }
>> +
> gpu_rmw(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0, (1 << 9));
> We need this for a640, a650 and a660.
>
Will make this a separate patch too, since it affects non-a660 GPUs too.
>> /* Enable expanded apriv for targets that support it */
>> if (gpu->hw_apriv) {
>> gpu_write(gpu, REG_A6XX_CP_APRIV_CNTL,
>> +/* check for a650, a660, or any derivatives */
>> +static inline int adreno_is_a650_family(struct adreno_gpu *gpu)
>> +{
>> + return gpu->revn == 650 || gpu->revn == 620 ||
>> + gpu->revn == 660 || gpu->revn == 635;
> We can remove 635 references throughout since that is not a valid adreno
> chipid anymore.
>
> -Akhil
I will remove it for my patch (it can discussed when adding 635 support,
but I think you will need to have a 6xx ID for the GPU)
>> +}
>> +
>> int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t
>> *value);
>> const struct firmware *adreno_request_fw(struct adreno_gpu *adreno_gpu,
>> const char *fwname);
>>
next prev parent reply other threads:[~2021-06-08 16:56 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-13 17:13 [PATCH v2 0/8] drm/msm/a6xx: add support for Adreno 660 GPU Jonathan Marek
2021-05-13 17:13 ` [PATCH v2 1/8] drm/msm: remove unused icc_path/ocmem_icc_path Jonathan Marek
2021-05-31 7:26 ` Akhil P Oommen
2021-05-13 17:13 ` [PATCH v2 2/8] drm/msm/a6xx: use AOP-initialized PDC for a650 Jonathan Marek
2021-05-31 7:24 ` Akhil P Oommen
2021-06-08 15:54 ` Jonathan Marek
2021-05-13 17:13 ` [PATCH v2 3/8] drm/msm/a6xx: fix incorrectly set uavflagprd_inv field for A650 Jonathan Marek
2021-05-31 7:33 ` Akhil P Oommen
2021-05-13 17:13 ` [PATCH v2 4/8] drm/msm/a6xx: update/fix CP_PROTECT initialization Jonathan Marek
2021-05-31 8:09 ` Akhil P Oommen
2021-05-13 17:14 ` [PATCH v2 5/8] drm/msm/a6xx: avoid shadow NULL reference in failure path Jonathan Marek
2021-05-31 9:25 ` Akhil P Oommen
2021-05-13 17:14 ` [PATCH v2 6/8] drm/msm/a6xx: add support for Adreno 660 GPU Jonathan Marek
2021-05-31 15:05 ` Akhil P Oommen
2021-06-08 16:53 ` Jonathan Marek [this message]
2021-05-13 17:14 ` [PATCH v2 7/8] drm/msm/a6xx: update a6xx_ucode_check_version for a660 Jonathan Marek
2021-05-31 15:06 ` Akhil P Oommen
2021-05-13 17:14 ` [PATCH v2 8/8] drm/msm/a6xx: add a660 hwcg table Jonathan Marek
2021-05-31 15:10 ` Akhil P Oommen
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=8dd37a7b-b58f-3cf6-346e-ca5add2a163c@marek.ca \
--to=jonathan@marek.ca \
--cc=airlied@linux.ie \
--cc=akhilpo@codeaurora.org \
--cc=angelogioacchino.delregno@somainline.org \
--cc=bjorn.andersson@linaro.org \
--cc=daniel@ffwll.ch \
--cc=dianders@chromium.org \
--cc=dri-devel@lists.freedesktop.org \
--cc=eric@anholt.net \
--cc=freedreno@lists.freedesktop.org \
--cc=jordan@cosmicpenguin.net \
--cc=konrad.dybcio@somainline.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=lkp@intel.com \
--cc=robdclark@gmail.com \
--cc=saiprakash.ranjan@codeaurora.org \
--cc=sean@poorly.run \
--cc=shawn.guo@linaro.org \
--cc=smasetty@codeaurora.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).