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* [PATCH v4 00/20] Enable Qualcomm Crypto Engine on sm8250
@ 2021-10-13 10:55 Bhupesh Sharma
  2021-10-13 10:55 ` [PATCH v4 01/20] arm64/dts: qcom: Fix 'dma' & 'qcom,controlled-remotely' nodes in dts Bhupesh Sharma
                   ` (20 more replies)
  0 siblings, 21 replies; 52+ messages in thread
From: Bhupesh Sharma @ 2021-10-13 10:55 UTC (permalink / raw)
  To: linux-arm-msm, linux-crypto
  Cc: bhupesh.sharma, bhupesh.linux, linux-kernel, devicetree, robh+dt,
	agross, herbert, davem, Thara Gopinath, Bjorn Andersson

Sorry for a delayed v4, but I have been caught up with some other
patches.

Changes since v3:
=================
- v3 can be seen here: https://lore.kernel.org/linux-arm-msm/20210519143700.27392-1-bhupesh.sharma@linaro.org/
- Dropped a couple of patches from v3, on basis of the review comments:
   ~ [PATCH 13/17] crypto: qce: core: Make clocks optional
   ~ [PATCH 15/17] crypto: qce: Convert the device found dev_dbg() to dev_info()
- Addressed review comments from Thara, Rob and Stephan Gerhold.
- Collect Reviewed-by from Rob and Thara on some of the patches from the
  v3 patchset.

Changes since v2:
=================
- v2 can be seen here: https://lore.kernel.org/dmaengine/20210505213731.538612-1-bhupesh.sharma@linaro.org/
- Drop a couple of patches from v1, which tried to address the defered
  probing of qce driver in case bam dma driver is not yet probed.
  Replace it instead with a single (simpler) patch [PATCH 16/17].
- Convert bam dma and qce crypto dt-bindings to YAML.
- Addressed review comments from Thara, Bjorn, Vinod and Rob.

Changes since v1:
=================
- v1 can be seen here: https://lore.kernel.org/linux-arm-msm/20210310052503.3618486-1-bhupesh.sharma@linaro.org/ 
- v1 did not work well as reported earlier by Dmitry, so v2 contains the following
  changes/fixes:
  ~ Enable the interconnect path b/w BAM DMA and main memory first
    before trying to access the BAM DMA registers.
  ~ Enable the interconnect path b/w qce crytpo and main memory first
    before trying to access the qce crypto registers.
  ~ Make sure to document the required and optional properties for both
    BAM DMA and qce crypto drivers.
  ~ Add a few debug related print messages in case the qce crypto driver
    passes or fails to probe.
  ~ Convert the qce crypto driver probe to a defered one in case the BAM DMA
    or the interconnect driver(s) (needed on specific Qualcomm parts) are not
    yet probed.

Qualcomm crypto engine is also available on sm8250 SoC.
It supports hardware accelerated algorithms for encryption
and authentication. It also provides support for aes, des, 3des
encryption algorithms and sha1, sha256, hmac(sha1), hmac(sha256)
authentication algorithms.

Tested the enabled crypto algorithms with cryptsetup test utilities
on sm8250-mtp and RB5 board (see [1]) and also with crypto self-tests,
including the fuzz tests (CONFIG_CRYPTO_MANAGER_EXTRA_TESTS=y).

Note that this series is rebased on a SMMU related fix from Arnd applied
on either linus's tip of linux-next's tip (see [2]), without which
the sm8250 based boards fail to boot with the latest tip.

[1]. https://linux.die.net/man/8/cryptsetup
[2]. https://lore.kernel.org/linux-arm-kernel/CAA8EJpoD4Th1tdwYQLnZur2oA0xX0LojSrNFLyJqdi6+rnB3YQ@mail.gmail.com/T/

Cc: Thara Gopinath <thara.gopinath@linaro.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>

Bhupesh Sharma (17):
  arm64/dts: qcom: Fix 'dma' & 'qcom,controlled-remotely' nodes in dts
  arm64/dts: qcom: ipq6018: Remove unused 'qcom,config-pipe-trust-reg'
    property
  arm64/dts: qcom: ipq6018: Remove unused 'iface_clk' property from
    dma-controller node
  dt-bindings: qcom-bam: Convert binding to YAML
  dt-bindings: qcom-bam: Add 'interconnects' & 'interconnect-names' to
    optional properties
  dt-bindings: qcom-bam: Add 'iommus' to optional properties
  dt-bindings: qcom-qce: Convert bindings to yaml
  dt-bindings: qcom-qce: Add 'interconnects' and move 'clocks' to
    optional properties
  dt-bindings: qcom-qce: Add 'iommus' to optional properties
  arm64/dts: qcom: sdm845: Use RPMH_CE_CLK macro directly
  dt-bindings: crypto : Add new compatible strings for qcom-qce
  arm64/dts: qcom: Use new compatibles for crypto nodes
  crypto: qce: Add new compatibles for qce crypto driver
  crypto: qce: Print a failure msg in case probe() fails
  crypto: qce: Defer probing if BAM dma channel is not yet initialized
  crypto: qce: Add 'sm8250-qce' compatible string check
  arm64/dts: qcom: sm8250: Add dt entries to support crypto engine.

Thara Gopinath (3):
  dma: qcom: bam_dma: Add support to initialize interconnect path
  crypto: qce: core: Add support to initialize interconnect path
  crypto: qce: core: Make clocks optional

 .../devicetree/bindings/crypto/qcom-qce.yaml  |  90 +++++++++++++++
 .../devicetree/bindings/dma/qcom_bam_dma.txt  |  50 --------
 .../devicetree/bindings/dma/qcom_bam_dma.yaml | 107 ++++++++++++++++++
 arch/arm64/boot/dts/qcom/ipq6018.dtsi         |  10 +-
 arch/arm64/boot/dts/qcom/ipq8074.dtsi         |   4 +-
 arch/arm64/boot/dts/qcom/msm8996.dtsi         |   4 +-
 arch/arm64/boot/dts/qcom/msm8998.dtsi         |   2 +-
 arch/arm64/boot/dts/qcom/sdm845.dtsi          |  10 +-
 arch/arm64/boot/dts/qcom/sm8250.dtsi          |  28 +++++
 drivers/crypto/qce/core.c                     |  66 +++++++----
 drivers/crypto/qce/core.h                     |   1 +
 drivers/dma/qcom/bam_dma.c                    |  16 ++-
 12 files changed, 302 insertions(+), 86 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/crypto/qcom-qce.yaml
 delete mode 100644 Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
 create mode 100644 Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml

-- 
2.31.1


^ permalink raw reply	[flat|nested] 52+ messages in thread

* [PATCH v4 01/20] arm64/dts: qcom: Fix 'dma' & 'qcom,controlled-remotely' nodes in dts
  2021-10-13 10:55 [PATCH v4 00/20] Enable Qualcomm Crypto Engine on sm8250 Bhupesh Sharma
@ 2021-10-13 10:55 ` Bhupesh Sharma
  2021-10-13 10:55 ` [PATCH v4 02/20] arm64/dts: qcom: ipq6018: Remove unused 'qcom,config-pipe-trust-reg' property Bhupesh Sharma
                   ` (19 subsequent siblings)
  20 siblings, 0 replies; 52+ messages in thread
From: Bhupesh Sharma @ 2021-10-13 10:55 UTC (permalink / raw)
  To: linux-arm-msm, linux-crypto
  Cc: bhupesh.sharma, bhupesh.linux, linux-kernel, devicetree, robh+dt,
	agross, herbert, davem, Thara Gopinath, Bjorn Andersson

Preparatory patch for subsequent patch in this series which
converts the qcom_bam_dma device-tree binding into YAML format.

A few qcom device-tree files define dma-controller nodes
with non-standard 'node names' and also set
the bool property 'qcom,controlled-remotely' incorrectly, which
leads to following errors with 'make dtbs_check':

 $ arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dt.yaml:
     dma@1dc4000: $nodename:0: 'dma@1dc4000' does not match
     '^dma-controller(@.*)?$'

 $ arch/arm64/boot/dts/qcom/sm8250-mtp.dt.yaml:
     dma@1dc4000: qcom,controlled-remotely: 'oneOf' conditional
     failed, one must be fixed:
	[[1]] is not of type 'boolean'
	True was expected
	[[1]] is not of type 'null'

Fix the same.

Cc: Thara Gopinath <thara.gopinath@linaro.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
 arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +-
 arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++--
 arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 ++--
 arch/arm64/boot/dts/qcom/msm8998.dtsi | 2 +-
 arch/arm64/boot/dts/qcom/sdm845.dtsi  | 4 ++--
 5 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
index d2fe58e0eb7a..7b6205c180df 100644
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -200,7 +200,7 @@ cryptobam: dma-controller@704000 {
 			clock-names = "bam_clk";
 			#dma-cells = <1>;
 			qcom,ee = <1>;
-			qcom,controlled-remotely = <1>;
+			qcom,controlled-remotely;
 			qcom,config-pipe-trust-reg = <0>;
 		};
 
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index db333001df4d..99668e84953e 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -212,7 +212,7 @@ prng: rng@e3000 {
 			status = "disabled";
 		};
 
-		cryptobam: dma@704000 {
+		cryptobam: dma-controller@704000 {
 			compatible = "qcom,bam-v1.7.0";
 			reg = <0x00704000 0x20000>;
 			interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
@@ -220,7 +220,7 @@ cryptobam: dma@704000 {
 			clock-names = "bam_clk";
 			#dma-cells = <1>;
 			qcom,ee = <1>;
-			qcom,controlled-remotely = <1>;
+			qcom,controlled-remotely;
 			status = "disabled";
 		};
 
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 52df22ab3f6a..390468e1b62e 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -2686,7 +2686,7 @@ sdhc2: sdhci@74a4900 {
 			status = "disabled";
 		 };
 
-		blsp1_dma: dma@7544000 {
+		blsp1_dma: dma-controller@7544000 {
 			compatible = "qcom,bam-v1.7.0";
 			reg = <0x07544000 0x2b000>;
 			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
@@ -2743,7 +2743,7 @@ blsp1_i2c3: i2c@7577000 {
 			status = "disabled";
 		};
 
-		blsp2_dma: dma@7584000 {
+		blsp2_dma: dma-controller@7584000 {
 			compatible = "qcom,bam-v1.7.0";
 			reg = <0x07584000 0x2b000>;
 			interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
index 34039b5c8017..a46838f1e310 100644
--- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
@@ -2187,7 +2187,7 @@ blsp1_i2c6: i2c@c17a000 {
 			#size-cells = <0>;
 		};
 
-		blsp2_dma: dma@c184000 {
+		blsp2_dma: dma-controller@c184000 {
 			compatible = "qcom,bam-v1.7.0";
 			reg = <0x0c184000 0x25000>;
 			interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index b3b911926184..72ec48c4e03c 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -2312,7 +2312,7 @@ ufs_mem_phy_lanes: lanes@1d87400 {
 			};
 		};
 
-		cryptobam: dma@1dc4000 {
+		cryptobam: dma-controller@1dc4000 {
 			compatible = "qcom,bam-v1.7.0";
 			reg = <0 0x01dc4000 0 0x24000>;
 			interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
@@ -2320,7 +2320,7 @@ cryptobam: dma@1dc4000 {
 			clock-names = "bam_clk";
 			#dma-cells = <1>;
 			qcom,ee = <0>;
-			qcom,controlled-remotely = <1>;
+			qcom,controlled-remotely;
 			iommus = <&apps_smmu 0x704 0x1>,
 				 <&apps_smmu 0x706 0x1>,
 				 <&apps_smmu 0x714 0x1>,
-- 
2.31.1


^ permalink raw reply related	[flat|nested] 52+ messages in thread

* [PATCH v4 02/20] arm64/dts: qcom: ipq6018: Remove unused 'qcom,config-pipe-trust-reg' property
  2021-10-13 10:55 [PATCH v4 00/20] Enable Qualcomm Crypto Engine on sm8250 Bhupesh Sharma
  2021-10-13 10:55 ` [PATCH v4 01/20] arm64/dts: qcom: Fix 'dma' & 'qcom,controlled-remotely' nodes in dts Bhupesh Sharma
@ 2021-10-13 10:55 ` Bhupesh Sharma
  2021-10-13 10:55 ` [PATCH v4 03/20] arm64/dts: qcom: ipq6018: Remove unused 'iface_clk' property from dma-controller node Bhupesh Sharma
                   ` (18 subsequent siblings)
  20 siblings, 0 replies; 52+ messages in thread
From: Bhupesh Sharma @ 2021-10-13 10:55 UTC (permalink / raw)
  To: linux-arm-msm, linux-crypto
  Cc: bhupesh.sharma, bhupesh.linux, linux-kernel, devicetree, robh+dt,
	agross, herbert, davem, Thara Gopinath, Bjorn Andersson

'qcom,config-pipe-trust-reg' property doesn't seem to be
used by the qcom, bam_dma driver, so remove the same
from 'ipq6018' dts.

This is a preparatory patch for subsequent patch in
this series which converts the qcom_bam_dma device-tree
binding into YAML format.

Without this change, 'make dtbs_check' leads to the following
error:
 $ arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dt.yaml:
     dma-controller@704000: 'qcom,config-pipe-trust-reg' does not match
     any of the regexes: 'pinctrl-[0-9]+'

Fix the same.

Cc: Thara Gopinath <thara.gopinath@linaro.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
 arch/arm64/boot/dts/qcom/ipq6018.dtsi | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
index 7b6205c180df..6a05ee82547f 100644
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -201,7 +201,6 @@ cryptobam: dma-controller@704000 {
 			#dma-cells = <1>;
 			qcom,ee = <1>;
 			qcom,controlled-remotely;
-			qcom,config-pipe-trust-reg = <0>;
 		};
 
 		crypto: crypto@73a000 {
-- 
2.31.1


^ permalink raw reply related	[flat|nested] 52+ messages in thread

* [PATCH v4 03/20] arm64/dts: qcom: ipq6018: Remove unused 'iface_clk' property from dma-controller node
  2021-10-13 10:55 [PATCH v4 00/20] Enable Qualcomm Crypto Engine on sm8250 Bhupesh Sharma
  2021-10-13 10:55 ` [PATCH v4 01/20] arm64/dts: qcom: Fix 'dma' & 'qcom,controlled-remotely' nodes in dts Bhupesh Sharma
  2021-10-13 10:55 ` [PATCH v4 02/20] arm64/dts: qcom: ipq6018: Remove unused 'qcom,config-pipe-trust-reg' property Bhupesh Sharma
@ 2021-10-13 10:55 ` Bhupesh Sharma
  2021-10-13 10:55 ` [PATCH v4 04/20] dt-bindings: qcom-bam: Convert binding to YAML Bhupesh Sharma
                   ` (17 subsequent siblings)
  20 siblings, 0 replies; 52+ messages in thread
From: Bhupesh Sharma @ 2021-10-13 10:55 UTC (permalink / raw)
  To: linux-arm-msm, linux-crypto
  Cc: bhupesh.sharma, bhupesh.linux, linux-kernel, devicetree, robh+dt,
	agross, herbert, davem, Thara Gopinath, Bjorn Andersson

'iface_clk' clock is not used by the
qcom, bam_dma driver, so remove the same from 'ipq6018' dts.

This is a preparatory patch for subsequent patch in
this series which converts the qcom_bam_dma device-tree
binding into YAML format.

Without this change, 'make dtbs_check' leads to the following
error:
 $ arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dt.yaml:
     dma-controller@7984000: clock-names: ['iface_clk', 'bam_clk']
     is too long

Fix the same.

Cc: Thara Gopinath <thara.gopinath@linaro.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
 arch/arm64/boot/dts/qcom/ipq6018.dtsi | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
index 6a05ee82547f..55c961b5f1ab 100644
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -346,9 +346,8 @@ qpic_bam: dma-controller@7984000 {
 			compatible = "qcom,bam-v1.7.0";
 			reg = <0x0 0x07984000 0x0 0x1a000>;
 			interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&gcc GCC_QPIC_CLK>,
-				 <&gcc GCC_QPIC_AHB_CLK>;
-			clock-names = "iface_clk", "bam_clk";
+			clocks = <&gcc GCC_QPIC_AHB_CLK>;
+			clock-names = "bam_clk";
 			#dma-cells = <1>;
 			qcom,ee = <0>;
 			status = "disabled";
-- 
2.31.1


^ permalink raw reply related	[flat|nested] 52+ messages in thread

* [PATCH v4 04/20] dt-bindings: qcom-bam: Convert binding to YAML
  2021-10-13 10:55 [PATCH v4 00/20] Enable Qualcomm Crypto Engine on sm8250 Bhupesh Sharma
                   ` (2 preceding siblings ...)
  2021-10-13 10:55 ` [PATCH v4 03/20] arm64/dts: qcom: ipq6018: Remove unused 'iface_clk' property from dma-controller node Bhupesh Sharma
@ 2021-10-13 10:55 ` Bhupesh Sharma
  2021-10-13 12:56   ` Vladimir Zapolskiy
  2021-10-13 10:55 ` [PATCH v4 05/20] dt-bindings: qcom-bam: Add 'interconnects' & 'interconnect-names' to optional properties Bhupesh Sharma
                   ` (16 subsequent siblings)
  20 siblings, 1 reply; 52+ messages in thread
From: Bhupesh Sharma @ 2021-10-13 10:55 UTC (permalink / raw)
  To: linux-arm-msm, linux-crypto
  Cc: bhupesh.sharma, bhupesh.linux, linux-kernel, devicetree, robh+dt,
	agross, herbert, davem, Thara Gopinath, Bjorn Andersson

Convert Qualcomm BAM DMA devicetree binding to YAML.

Cc: Thara Gopinath <thara.gopinath@linaro.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
 .../devicetree/bindings/dma/qcom_bam_dma.txt  | 50 -----------
 .../devicetree/bindings/dma/qcom_bam_dma.yaml | 89 +++++++++++++++++++
 2 files changed, 89 insertions(+), 50 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
 create mode 100644 Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml

diff --git a/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt b/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
deleted file mode 100644
index cf5b9e44432c..000000000000
--- a/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
+++ /dev/null
@@ -1,50 +0,0 @@
-QCOM BAM DMA controller
-
-Required properties:
-- compatible: must be one of the following:
- * "qcom,bam-v1.4.0" for MSM8974, APQ8074 and APQ8084
- * "qcom,bam-v1.3.0" for APQ8064, IPQ8064 and MSM8960
- * "qcom,bam-v1.7.0" for MSM8916
-- reg: Address range for DMA registers
-- interrupts: Should contain the one interrupt shared by all channels
-- #dma-cells: must be <1>, the cell in the dmas property of the client device
-  represents the channel number
-- clocks: required clock
-- clock-names: must contain "bam_clk" entry
-- qcom,ee : indicates the active Execution Environment identifier (0-7) used in
-  the secure world.
-- qcom,controlled-remotely : optional, indicates that the bam is controlled by
-  remote proccessor i.e. execution environment.
-- num-channels : optional, indicates supported number of DMA channels in a
-  remotely controlled bam.
-- qcom,num-ees : optional, indicates supported number of Execution Environments
-  in a remotely controlled bam.
-
-Example:
-
-	uart-bam: dma@f9984000 = {
-		compatible = "qcom,bam-v1.4.0";
-		reg = <0xf9984000 0x15000>;
-		interrupts = <0 94 0>;
-		clocks = <&gcc GCC_BAM_DMA_AHB_CLK>;
-		clock-names = "bam_clk";
-		#dma-cells = <1>;
-		qcom,ee = <0>;
-	};
-
-DMA clients must use the format described in the dma.txt file, using a two cell
-specifier for each channel.
-
-Example:
-	serial@f991e000 {
-		compatible = "qcom,msm-uart";
-		reg = <0xf991e000 0x1000>
-			<0xf9944000 0x19000>;
-		interrupts = <0 108 0>;
-		clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
-			<&gcc GCC_BLSP1_AHB_CLK>;
-		clock-names = "core", "iface";
-
-		dmas = <&uart-bam 0>, <&uart-bam 1>;
-		dma-names = "rx", "tx";
-	};
diff --git a/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml b/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml
new file mode 100644
index 000000000000..32b47e3b7769
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml
@@ -0,0 +1,89 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/qcom_bam_dma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: QCOM BAM DMA controller binding
+
+maintainers:
+  - Bhupesh Sharma <bhupesh.sharma@linaro.org>
+
+description: |
+  This document defines the binding for the BAM DMA controller
+  found on Qualcomm parts.
+
+allOf:
+  - $ref: "dma-controller.yaml#"
+
+properties:
+  compatible:
+    enum:
+      - qcom,bam-v1.4.0 # for MSM8974, APQ8074 and APQ8084
+      - qcom,bam-v1.3.0 # for APQ8064, IPQ8064 and MSM8960
+      - qcom,bam-v1.7.0 # for MSM8916
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    const: bam_clk
+
+  interrupts:
+    minItems: 1
+    maxItems: 31
+
+  num-channels:
+    maximum: 31
+    description: |
+      Indicates supported number of DMA channels in a remotely controlled bam.
+
+  "#dma-cells":
+    const: 1
+    description: The single cell represents the channel index.
+
+  qcom,ee:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      Indicates the active Execution Environment identifier (0-7)
+      used in the secure world.
+
+  qcom,controlled-remotely:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      Indicates that the bam is controlled by remote proccessor i.e.
+      execution environment.
+
+  qcom,num-ees:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    minimum: 0
+    maximum: 31
+    default: 2
+    description:
+      Indicates supported number of Execution Environments in a
+      remotely controlled bam.
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - "#dma-cells"
+  - qcom,ee
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,gcc-msm8974.h>
+    dma-controller@f9984000 {
+        compatible = "qcom,bam-v1.4.0";
+        reg = <0xf9984000 0x15000>;
+        interrupts = <0 94 0>;
+        clocks = <&gcc GCC_BAM_DMA_AHB_CLK>;
+        clock-names = "bam_clk";
+        #dma-cells = <1>;
+        qcom,ee = <0>;
+    };
-- 
2.31.1


^ permalink raw reply related	[flat|nested] 52+ messages in thread

* [PATCH v4 05/20] dt-bindings: qcom-bam: Add 'interconnects' & 'interconnect-names' to optional properties
  2021-10-13 10:55 [PATCH v4 00/20] Enable Qualcomm Crypto Engine on sm8250 Bhupesh Sharma
                   ` (3 preceding siblings ...)
  2021-10-13 10:55 ` [PATCH v4 04/20] dt-bindings: qcom-bam: Convert binding to YAML Bhupesh Sharma
@ 2021-10-13 10:55 ` Bhupesh Sharma
  2021-10-13 13:03   ` Vladimir Zapolskiy
  2021-10-13 18:39   ` Rob Herring
  2021-10-13 10:55 ` [PATCH v4 06/20] dt-bindings: qcom-bam: Add 'iommus' " Bhupesh Sharma
                   ` (15 subsequent siblings)
  20 siblings, 2 replies; 52+ messages in thread
From: Bhupesh Sharma @ 2021-10-13 10:55 UTC (permalink / raw)
  To: linux-arm-msm, linux-crypto
  Cc: bhupesh.sharma, bhupesh.linux, linux-kernel, devicetree, robh+dt,
	agross, herbert, davem, Thara Gopinath, Bjorn Andersson

Add new optional properties - 'interconnects' and
'interconnect-names' to the device-tree binding documentation for
qcom-bam DMA IP.

These properties describe the interconnect path between bam and main
memory and the interconnect type respectively.

Cc: Thara Gopinath <thara.gopinath@linaro.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
 Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml b/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml
index 32b47e3b7769..602e68df971f 100644
--- a/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml
+++ b/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml
@@ -45,6 +45,14 @@ properties:
     const: 1
     description: The single cell represents the channel index.
 
+  interconnects:
+    maxItems: 1
+    description: |
+      Interconnect path between bam and main memory.
+
+  interconnect-names:
+    const: memory
+
   qcom,ee:
     $ref: /schemas/types.yaml#/definitions/uint32
     description:
-- 
2.31.1


^ permalink raw reply related	[flat|nested] 52+ messages in thread

* [PATCH v4 06/20] dt-bindings: qcom-bam: Add 'iommus' to optional properties
  2021-10-13 10:55 [PATCH v4 00/20] Enable Qualcomm Crypto Engine on sm8250 Bhupesh Sharma
                   ` (4 preceding siblings ...)
  2021-10-13 10:55 ` [PATCH v4 05/20] dt-bindings: qcom-bam: Add 'interconnects' & 'interconnect-names' to optional properties Bhupesh Sharma
@ 2021-10-13 10:55 ` Bhupesh Sharma
  2021-10-13 10:55 ` [PATCH v4 07/20] dt-bindings: qcom-qce: Convert bindings to yaml Bhupesh Sharma
                   ` (14 subsequent siblings)
  20 siblings, 0 replies; 52+ messages in thread
From: Bhupesh Sharma @ 2021-10-13 10:55 UTC (permalink / raw)
  To: linux-arm-msm, linux-crypto
  Cc: bhupesh.sharma, bhupesh.linux, linux-kernel, devicetree, robh+dt,
	agross, herbert, davem, Thara Gopinath, Bjorn Andersson

Add 'optional' property - 'iommus' to the
device-tree binding documentation for qcom-bam DMA IP.

This property describes the phandle(s) to apps_smmu node
with sid mask.

Cc: Thara Gopinath <thara.gopinath@linaro.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
 .../devicetree/bindings/dma/qcom_bam_dma.yaml          | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml b/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml
index 602e68df971f..7c046a281fcd 100644
--- a/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml
+++ b/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml
@@ -53,6 +53,12 @@ properties:
   interconnect-names:
     const: memory
 
+  iommus:
+    minItems: 1
+    maxItems: 8
+    description: |
+      phandle(s) to apps_smmu node with sid mask.
+
   qcom,ee:
     $ref: /schemas/types.yaml#/definitions/uint32
     description:
@@ -94,4 +100,8 @@ examples:
         clock-names = "bam_clk";
         #dma-cells = <1>;
         qcom,ee = <0>;
+        iommus = <&apps_smmu 0x584 0x0011>,
+                 <&apps_smmu 0x586 0x0011>,
+                 <&apps_smmu 0x594 0x0011>,
+                 <&apps_smmu 0x596 0x0011>;
     };
-- 
2.31.1


^ permalink raw reply related	[flat|nested] 52+ messages in thread

* [PATCH v4 07/20] dt-bindings: qcom-qce: Convert bindings to yaml
  2021-10-13 10:55 [PATCH v4 00/20] Enable Qualcomm Crypto Engine on sm8250 Bhupesh Sharma
                   ` (5 preceding siblings ...)
  2021-10-13 10:55 ` [PATCH v4 06/20] dt-bindings: qcom-bam: Add 'iommus' " Bhupesh Sharma
@ 2021-10-13 10:55 ` Bhupesh Sharma
  2021-10-13 13:05   ` Vladimir Zapolskiy
  2021-10-13 10:55 ` [PATCH v4 08/20] dt-bindings: qcom-qce: Add 'interconnects' and move 'clocks' to optional properties Bhupesh Sharma
                   ` (13 subsequent siblings)
  20 siblings, 1 reply; 52+ messages in thread
From: Bhupesh Sharma @ 2021-10-13 10:55 UTC (permalink / raw)
  To: linux-arm-msm, linux-crypto
  Cc: bhupesh.sharma, bhupesh.linux, linux-kernel, devicetree, robh+dt,
	agross, herbert, davem, Thara Gopinath, Bjorn Andersson,
	Rob Herring

Convert Qualcomm QCE crypto devicetree binding to YAML.

Cc: Thara Gopinath <thara.gopinath@linaro.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
 .../devicetree/bindings/crypto/qcom-qce.yaml  | 67 +++++++++++++++++++
 1 file changed, 67 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/crypto/qcom-qce.yaml

diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
new file mode 100644
index 000000000000..b7ae873dc943
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/crypto/qcom-qce.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm crypto engine driver
+
+maintainers:
+  - Bhupesh Sharma <bhupesh.sharma@linaro.org>
+
+description: |
+  This document defines the binding for the QCE crypto
+  controller found on Qualcomm parts.
+
+properties:
+  compatible:
+    const: qcom,crypto-v5.1
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: iface clocks register interface.
+      - description: bus clocks data transfer interface.
+      - description: core clocks rest of the crypto block.
+
+  clock-names:
+    items:
+      - const: iface
+      - const: bus
+      - const: core
+
+  dmas:
+    items:
+      - description: DMA specifiers for tx dma channel.
+      - description: DMA specifiers for rx dma channel.
+
+  dma-names:
+    items:
+      - const: rx
+      - const: tx
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - dmas
+  - dma-names
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,gcc-apq8084.h>
+    crypto-engine@fd45a000 {
+        compatible = "qcom,crypto-v5.1";
+        reg = <0xfd45a000 0x6000>;
+        clocks = <&gcc GCC_CE2_AHB_CLK>,
+                 <&gcc GCC_CE2_AXI_CLK>,
+                 <&gcc GCC_CE2_CLK>;
+        clock-names = "iface", "bus", "core";
+        dmas = <&cryptobam 2>, <&cryptobam 3>;
+        dma-names = "rx", "tx";
+    };
-- 
2.31.1


^ permalink raw reply related	[flat|nested] 52+ messages in thread

* [PATCH v4 08/20] dt-bindings: qcom-qce: Add 'interconnects' and move 'clocks' to optional properties
  2021-10-13 10:55 [PATCH v4 00/20] Enable Qualcomm Crypto Engine on sm8250 Bhupesh Sharma
                   ` (6 preceding siblings ...)
  2021-10-13 10:55 ` [PATCH v4 07/20] dt-bindings: qcom-qce: Convert bindings to yaml Bhupesh Sharma
@ 2021-10-13 10:55 ` Bhupesh Sharma
  2021-10-26 19:40   ` Rob Herring
  2021-10-13 10:55 ` [PATCH v4 09/20] dt-bindings: qcom-qce: Add 'iommus' " Bhupesh Sharma
                   ` (12 subsequent siblings)
  20 siblings, 1 reply; 52+ messages in thread
From: Bhupesh Sharma @ 2021-10-13 10:55 UTC (permalink / raw)
  To: linux-arm-msm, linux-crypto
  Cc: bhupesh.sharma, bhupesh.linux, linux-kernel, devicetree, robh+dt,
	agross, herbert, davem, Thara Gopinath, Bjorn Andersson

Add 'interconnects' and 'interconnect-names' as optional properties
to the device-tree binding documentation for qcom crypto IP.

These properties describe the interconnect path between crypto and main
memory and the interconnect type respectively.

Cc: Thara Gopinath <thara.gopinath@linaro.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
 Documentation/devicetree/bindings/crypto/qcom-qce.yaml | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
index b7ae873dc943..954f762090f3 100644
--- a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
+++ b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
@@ -32,6 +32,14 @@ properties:
       - const: bus
       - const: core
 
+  interconnects:
+    maxItems: 1
+    description: |
+      Interconnect path between qce crypto and main memory.
+
+  interconnect-names:
+    const: memory
+
   dmas:
     items:
       - description: DMA specifiers for tx dma channel.
@@ -45,8 +53,6 @@ properties:
 required:
   - compatible
   - reg
-  - clocks
-  - clock-names
   - dmas
   - dma-names
 
-- 
2.31.1


^ permalink raw reply related	[flat|nested] 52+ messages in thread

* [PATCH v4 09/20] dt-bindings: qcom-qce: Add 'iommus' to optional properties
  2021-10-13 10:55 [PATCH v4 00/20] Enable Qualcomm Crypto Engine on sm8250 Bhupesh Sharma
                   ` (7 preceding siblings ...)
  2021-10-13 10:55 ` [PATCH v4 08/20] dt-bindings: qcom-qce: Add 'interconnects' and move 'clocks' to optional properties Bhupesh Sharma
@ 2021-10-13 10:55 ` Bhupesh Sharma
  2021-10-26 19:40   ` Rob Herring
  2021-10-13 10:55 ` [PATCH v4 10/20] arm64/dts: qcom: sdm845: Use RPMH_CE_CLK macro directly Bhupesh Sharma
                   ` (11 subsequent siblings)
  20 siblings, 1 reply; 52+ messages in thread
From: Bhupesh Sharma @ 2021-10-13 10:55 UTC (permalink / raw)
  To: linux-arm-msm, linux-crypto
  Cc: bhupesh.sharma, bhupesh.linux, linux-kernel, devicetree, robh+dt,
	agross, herbert, davem, Thara Gopinath, Bjorn Andersson

Add the missing optional property - 'iommus' to the
device-tree binding documentation for qcom-qce crypto IP.

This property describes the phandle(s) to apps_smmu node with sid mask.

Cc: Thara Gopinath <thara.gopinath@linaro.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
 .../devicetree/bindings/crypto/qcom-qce.yaml          | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
index 954f762090f3..1134899b422f 100644
--- a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
+++ b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
@@ -32,6 +32,12 @@ properties:
       - const: bus
       - const: core
 
+  iommus:
+    minItems: 1
+    maxItems: 8
+    description: |
+      phandle to apps_smmu node with sid mask.
+
   interconnects:
     maxItems: 1
     description: |
@@ -70,4 +76,9 @@ examples:
         clock-names = "iface", "bus", "core";
         dmas = <&cryptobam 2>, <&cryptobam 3>;
         dma-names = "rx", "tx";
+        iommus = <&apps_smmu 0x584 0x0011>,
+                 <&apps_smmu 0x586 0x0011>,
+                 <&apps_smmu 0x594 0x0011>,
+                 <&apps_smmu 0x596 0x0011>;
+
     };
-- 
2.31.1


^ permalink raw reply related	[flat|nested] 52+ messages in thread

* [PATCH v4 10/20] arm64/dts: qcom: sdm845: Use RPMH_CE_CLK macro directly
  2021-10-13 10:55 [PATCH v4 00/20] Enable Qualcomm Crypto Engine on sm8250 Bhupesh Sharma
                   ` (8 preceding siblings ...)
  2021-10-13 10:55 ` [PATCH v4 09/20] dt-bindings: qcom-qce: Add 'iommus' " Bhupesh Sharma
@ 2021-10-13 10:55 ` Bhupesh Sharma
  2021-10-13 10:55 ` [PATCH v4 11/20] dt-bindings: crypto : Add new compatible strings for qcom-qce Bhupesh Sharma
                   ` (10 subsequent siblings)
  20 siblings, 0 replies; 52+ messages in thread
From: Bhupesh Sharma @ 2021-10-13 10:55 UTC (permalink / raw)
  To: linux-arm-msm, linux-crypto
  Cc: bhupesh.sharma, bhupesh.linux, linux-kernel, devicetree, robh+dt,
	agross, herbert, davem, Bjorn Andersson, Thara Gopinath

In commit 3e482859f1ef ("dts: qcom: sdm845: Add dt entries
to support crypto engine."), we decided to use the value indicated
by constant RPMH_CE_CLK rather than using it directly.

Now that the same RPMH clock value might be used for other
SoCs (in addition to sdm845), let's use the constant
RPMH_CE_CLK to make sure that this dtsi is compatible with the
other qcom ones.

Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Reviewed-by: Thara Gopinath <thara.gopinath@linaro.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
 arch/arm64/boot/dts/qcom/sdm845.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 72ec48c4e03c..a301ca7664c1 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -2316,7 +2316,7 @@ cryptobam: dma-controller@1dc4000 {
 			compatible = "qcom,bam-v1.7.0";
 			reg = <0 0x01dc4000 0 0x24000>;
 			interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rpmhcc 15>;
+			clocks = <&rpmhcc RPMH_CE_CLK>;
 			clock-names = "bam_clk";
 			#dma-cells = <1>;
 			qcom,ee = <0>;
@@ -2332,7 +2332,7 @@ crypto: crypto@1dfa000 {
 			reg = <0 0x01dfa000 0 0x6000>;
 			clocks = <&gcc GCC_CE1_AHB_CLK>,
 				 <&gcc GCC_CE1_AHB_CLK>,
-				 <&rpmhcc 15>;
+				 <&rpmhcc RPMH_CE_CLK>;
 			clock-names = "iface", "bus", "core";
 			dmas = <&cryptobam 6>, <&cryptobam 7>;
 			dma-names = "rx", "tx";
-- 
2.31.1


^ permalink raw reply related	[flat|nested] 52+ messages in thread

* [PATCH v4 11/20] dt-bindings: crypto : Add new compatible strings for qcom-qce
  2021-10-13 10:55 [PATCH v4 00/20] Enable Qualcomm Crypto Engine on sm8250 Bhupesh Sharma
                   ` (9 preceding siblings ...)
  2021-10-13 10:55 ` [PATCH v4 10/20] arm64/dts: qcom: sdm845: Use RPMH_CE_CLK macro directly Bhupesh Sharma
@ 2021-10-13 10:55 ` Bhupesh Sharma
  2021-10-18 18:26   ` Rob Herring
  2021-10-13 10:55 ` [PATCH v4 12/20] arm64/dts: qcom: Use new compatibles for crypto nodes Bhupesh Sharma
                   ` (9 subsequent siblings)
  20 siblings, 1 reply; 52+ messages in thread
From: Bhupesh Sharma @ 2021-10-13 10:55 UTC (permalink / raw)
  To: linux-arm-msm, linux-crypto
  Cc: bhupesh.sharma, bhupesh.linux, linux-kernel, devicetree, robh+dt,
	agross, herbert, davem, Thara Gopinath, Bjorn Andersson

Newer qcom chips support newer versions of the qce crypto IP, so add
soc specific compatible strings for qcom-qce instead of using crypto
IP version specific ones.

Keep the old strings for backward-compatibility, but mark them as
deprecated.

Cc: Thara Gopinath <thara.gopinath@linaro.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
 Documentation/devicetree/bindings/crypto/qcom-qce.yaml | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
index 1134899b422f..5ab9335219d9 100644
--- a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
+++ b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
@@ -15,7 +15,13 @@ description: |
 
 properties:
   compatible:
-    const: qcom,crypto-v5.1
+    enum:
+      - qcom,crypto-v5.1 # Deprecated. Kept only for backward compatibility
+      - qcom,ipq6018-qce
+      - qcom,sdm845-qce
+      - qcom,sm8150-qce
+      - qcom,sm8250-qce
+      - qcom,sm8350-qce
 
   reg:
     maxItems: 1
@@ -68,7 +74,7 @@ examples:
   - |
     #include <dt-bindings/clock/qcom,gcc-apq8084.h>
     crypto-engine@fd45a000 {
-        compatible = "qcom,crypto-v5.1";
+        compatible = "qcom,ipq6018-qce";
         reg = <0xfd45a000 0x6000>;
         clocks = <&gcc GCC_CE2_AHB_CLK>,
                  <&gcc GCC_CE2_AXI_CLK>,
-- 
2.31.1


^ permalink raw reply related	[flat|nested] 52+ messages in thread

* [PATCH v4 12/20] arm64/dts: qcom: Use new compatibles for crypto nodes
  2021-10-13 10:55 [PATCH v4 00/20] Enable Qualcomm Crypto Engine on sm8250 Bhupesh Sharma
                   ` (10 preceding siblings ...)
  2021-10-13 10:55 ` [PATCH v4 11/20] dt-bindings: crypto : Add new compatible strings for qcom-qce Bhupesh Sharma
@ 2021-10-13 10:55 ` Bhupesh Sharma
  2021-10-13 10:55 ` [PATCH v4 13/20] dma: qcom: bam_dma: Add support to initialize interconnect path Bhupesh Sharma
                   ` (8 subsequent siblings)
  20 siblings, 0 replies; 52+ messages in thread
From: Bhupesh Sharma @ 2021-10-13 10:55 UTC (permalink / raw)
  To: linux-arm-msm, linux-crypto
  Cc: bhupesh.sharma, bhupesh.linux, linux-kernel, devicetree, robh+dt,
	agross, herbert, davem, Thara Gopinath, Bjorn Andersson

Since we are using soc specific qce crypto IP compatibles
in the bindings now, use the same in the device tree files
which include the crypto nodes.

Cc: Thara Gopinath <thara.gopinath@linaro.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
 arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +-
 arch/arm64/boot/dts/qcom/sdm845.dtsi  | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
index 55c961b5f1ab..2078edd36212 100644
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -204,7 +204,7 @@ cryptobam: dma-controller@704000 {
 		};
 
 		crypto: crypto@73a000 {
-			compatible = "qcom,crypto-v5.1";
+			compatible = "qcom,ipq6018-qce";
 			reg = <0x0 0x0073a000 0x0 0x6000>;
 			clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
 				<&gcc GCC_CRYPTO_AXI_CLK>,
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index a301ca7664c1..575964f80b31 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -2328,7 +2328,7 @@ cryptobam: dma-controller@1dc4000 {
 		};
 
 		crypto: crypto@1dfa000 {
-			compatible = "qcom,crypto-v5.4";
+			compatible = "qcom,sdm845-qce";
 			reg = <0 0x01dfa000 0 0x6000>;
 			clocks = <&gcc GCC_CE1_AHB_CLK>,
 				 <&gcc GCC_CE1_AHB_CLK>,
-- 
2.31.1


^ permalink raw reply related	[flat|nested] 52+ messages in thread

* [PATCH v4 13/20] dma: qcom: bam_dma: Add support to initialize interconnect path
  2021-10-13 10:55 [PATCH v4 00/20] Enable Qualcomm Crypto Engine on sm8250 Bhupesh Sharma
                   ` (11 preceding siblings ...)
  2021-10-13 10:55 ` [PATCH v4 12/20] arm64/dts: qcom: Use new compatibles for crypto nodes Bhupesh Sharma
@ 2021-10-13 10:55 ` Bhupesh Sharma
  2021-10-13 19:15   ` Vladimir Zapolskiy
  2021-10-13 10:55 ` [PATCH v4 14/20] crypto: qce: core: " Bhupesh Sharma
                   ` (7 subsequent siblings)
  20 siblings, 1 reply; 52+ messages in thread
From: Bhupesh Sharma @ 2021-10-13 10:55 UTC (permalink / raw)
  To: linux-arm-msm, linux-crypto
  Cc: bhupesh.sharma, bhupesh.linux, linux-kernel, devicetree, robh+dt,
	agross, herbert, davem, Thara Gopinath, Bjorn Andersson

From: Thara Gopinath <thara.gopinath@linaro.org>

BAM dma engine associated with certain hardware blocks could require
relevant interconnect pieces be initialized prior to the dma engine
initialization. For e.g. crypto bam dma engine on sm8250. Such requirement
is passed on to the bam dma driver from dt via the "interconnects"
property.  Add support in bam_dma driver to check whether the interconnect
path is accessible/enabled prior to attempting driver intializations.

Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
[Make header file inclusion alphabetical]
Signed-off-by: Thara Gopinath <thara.gopinath@linaro.org>
---
 drivers/dma/qcom/bam_dma.c | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/dma/qcom/bam_dma.c b/drivers/dma/qcom/bam_dma.c
index c8a77b428b52..fc84ef42507d 100644
--- a/drivers/dma/qcom/bam_dma.c
+++ b/drivers/dma/qcom/bam_dma.c
@@ -26,6 +26,7 @@
 #include <linux/kernel.h>
 #include <linux/io.h>
 #include <linux/init.h>
+#include <linux/interconnect.h>
 #include <linux/slab.h>
 #include <linux/module.h>
 #include <linux/interrupt.h>
@@ -392,6 +393,7 @@ struct bam_device {
 	const struct reg_offset_data *layout;
 
 	struct clk *bamclk;
+	struct icc_path *mem_path;
 	int irq;
 
 	/* dma start transaction tasklet */
@@ -1284,9 +1286,18 @@ static int bam_dma_probe(struct platform_device *pdev)
 		return ret;
 	}
 
+	/* Ensure that interconnects are initialized */
+	bdev->mem_path = of_icc_get(bdev->dev, "memory");
+
+	if (IS_ERR(bdev->mem_path)) {
+		ret = PTR_ERR(bdev->mem_path);
+		dev_err(bdev->dev, "failed to acquire icc path %d\n", ret);
+		goto err_disable_clk;
+	}
+
 	ret = bam_init(bdev);
 	if (ret)
-		goto err_disable_clk;
+		goto err_icc_path_put;
 
 	tasklet_setup(&bdev->task, dma_tasklet);
 
@@ -1371,6 +1382,8 @@ static int bam_dma_probe(struct platform_device *pdev)
 		tasklet_kill(&bdev->channels[i].vc.task);
 err_tasklet_kill:
 	tasklet_kill(&bdev->task);
+err_icc_path_put:
+	icc_put(bdev->mem_path);
 err_disable_clk:
 	clk_disable_unprepare(bdev->bamclk);
 
@@ -1406,6 +1419,7 @@ static int bam_dma_remove(struct platform_device *pdev)
 
 	tasklet_kill(&bdev->task);
 
+	icc_put(bdev->mem_path);
 	clk_disable_unprepare(bdev->bamclk);
 
 	return 0;
-- 
2.31.1


^ permalink raw reply related	[flat|nested] 52+ messages in thread

* [PATCH v4 14/20] crypto: qce: core: Add support to initialize interconnect path
  2021-10-13 10:55 [PATCH v4 00/20] Enable Qualcomm Crypto Engine on sm8250 Bhupesh Sharma
                   ` (12 preceding siblings ...)
  2021-10-13 10:55 ` [PATCH v4 13/20] dma: qcom: bam_dma: Add support to initialize interconnect path Bhupesh Sharma
@ 2021-10-13 10:55 ` Bhupesh Sharma
  2021-10-13 19:19   ` Vladimir Zapolskiy
  2021-10-13 10:55 ` [PATCH v4 15/20] crypto: qce: Add new compatibles for qce crypto driver Bhupesh Sharma
                   ` (6 subsequent siblings)
  20 siblings, 1 reply; 52+ messages in thread
From: Bhupesh Sharma @ 2021-10-13 10:55 UTC (permalink / raw)
  To: linux-arm-msm, linux-crypto
  Cc: bhupesh.sharma, bhupesh.linux, linux-kernel, devicetree, robh+dt,
	agross, herbert, davem, Thara Gopinath, Bjorn Andersson

From: Thara Gopinath <thara.gopinath@linaro.org>

Crypto engine on certain Snapdragon processors like sm8150, sm8250, sm8350
etc. requires interconnect path between the engine and memory to be
explicitly enabled and bandwidth set prior to any operations. Add support
in the qce core to enable the interconnect path appropriately.

Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
[Make header file inclusion alphabetical]
Signed-off-by: Thara Gopinath <thara.gopinath@linaro.org>
---
 drivers/crypto/qce/core.c | 35 ++++++++++++++++++++++++++++-------
 drivers/crypto/qce/core.h |  1 +
 2 files changed, 29 insertions(+), 7 deletions(-)

diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c
index d3780be44a76..033c7278aa5d 100644
--- a/drivers/crypto/qce/core.c
+++ b/drivers/crypto/qce/core.c
@@ -5,6 +5,7 @@
 
 #include <linux/clk.h>
 #include <linux/dma-mapping.h>
+#include <linux/interconnect.h>
 #include <linux/interrupt.h>
 #include <linux/module.h>
 #include <linux/mod_devicetable.h>
@@ -22,6 +23,8 @@
 #define QCE_MAJOR_VERSION5	0x05
 #define QCE_QUEUE_LENGTH	1
 
+#define QCE_DEFAULT_MEM_BANDWIDTH	393600
+
 static const struct qce_algo_ops *qce_ops[] = {
 #ifdef CONFIG_CRYPTO_DEV_QCE_SKCIPHER
 	&skcipher_ops,
@@ -206,21 +209,35 @@ static int qce_crypto_probe(struct platform_device *pdev)
 	if (ret < 0)
 		return ret;
 
+	qce->mem_path = of_icc_get(qce->dev, "memory");
+	if (IS_ERR(qce->mem_path))
+		return PTR_ERR(qce->mem_path);
+
 	qce->core = devm_clk_get(qce->dev, "core");
-	if (IS_ERR(qce->core))
-		return PTR_ERR(qce->core);
+	if (IS_ERR(qce->core)) {
+		ret = PTR_ERR(qce->core);
+		goto err_mem_path_put;
+	}
 
 	qce->iface = devm_clk_get(qce->dev, "iface");
-	if (IS_ERR(qce->iface))
-		return PTR_ERR(qce->iface);
+	if (IS_ERR(qce->iface)) {
+		ret = PTR_ERR(qce->iface);
+		goto err_mem_path_put;
+	}
 
 	qce->bus = devm_clk_get(qce->dev, "bus");
-	if (IS_ERR(qce->bus))
-		return PTR_ERR(qce->bus);
+	if (IS_ERR(qce->bus)) {
+		ret = PTR_ERR(qce->bus);
+		goto err_mem_path_put;
+	}
+
+	ret = icc_set_bw(qce->mem_path, QCE_DEFAULT_MEM_BANDWIDTH, QCE_DEFAULT_MEM_BANDWIDTH);
+	if (ret)
+		goto err_mem_path_put;
 
 	ret = clk_prepare_enable(qce->core);
 	if (ret)
-		return ret;
+		goto err_mem_path_disable;
 
 	ret = clk_prepare_enable(qce->iface);
 	if (ret)
@@ -260,6 +277,10 @@ static int qce_crypto_probe(struct platform_device *pdev)
 	clk_disable_unprepare(qce->iface);
 err_clks_core:
 	clk_disable_unprepare(qce->core);
+err_mem_path_disable:
+	icc_set_bw(qce->mem_path, 0, 0);
+err_mem_path_put:
+	icc_put(qce->mem_path);
 	return ret;
 }
 
diff --git a/drivers/crypto/qce/core.h b/drivers/crypto/qce/core.h
index 085774cdf641..228fcd69ec51 100644
--- a/drivers/crypto/qce/core.h
+++ b/drivers/crypto/qce/core.h
@@ -35,6 +35,7 @@ struct qce_device {
 	void __iomem *base;
 	struct device *dev;
 	struct clk *core, *iface, *bus;
+	struct icc_path *mem_path;
 	struct qce_dma_data dma;
 	int burst_size;
 	unsigned int pipe_pair_id;
-- 
2.31.1


^ permalink raw reply related	[flat|nested] 52+ messages in thread

* [PATCH v4 15/20] crypto: qce: Add new compatibles for qce crypto driver
  2021-10-13 10:55 [PATCH v4 00/20] Enable Qualcomm Crypto Engine on sm8250 Bhupesh Sharma
                   ` (13 preceding siblings ...)
  2021-10-13 10:55 ` [PATCH v4 14/20] crypto: qce: core: " Bhupesh Sharma
@ 2021-10-13 10:55 ` Bhupesh Sharma
  2021-10-13 19:22   ` Vladimir Zapolskiy
  2021-10-20 14:07   ` Thara Gopinath
  2021-10-13 10:55 ` [PATCH v4 16/20] crypto: qce: core: Make clocks optional Bhupesh Sharma
                   ` (5 subsequent siblings)
  20 siblings, 2 replies; 52+ messages in thread
From: Bhupesh Sharma @ 2021-10-13 10:55 UTC (permalink / raw)
  To: linux-arm-msm, linux-crypto
  Cc: bhupesh.sharma, bhupesh.linux, linux-kernel, devicetree, robh+dt,
	agross, herbert, davem, Thara Gopinath, Bjorn Andersson

Since we decided to use soc specific compatibles for describing
the qce crypto IP nodes in the device-trees, adapt the driver
now to handle the same.

Cc: Thara Gopinath <thara.gopinath@linaro.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
 drivers/crypto/qce/core.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c
index 033c7278aa5d..2ab0b97d718c 100644
--- a/drivers/crypto/qce/core.c
+++ b/drivers/crypto/qce/core.c
@@ -298,8 +298,8 @@ static int qce_crypto_remove(struct platform_device *pdev)
 }
 
 static const struct of_device_id qce_crypto_of_match[] = {
-	{ .compatible = "qcom,crypto-v5.1", },
-	{ .compatible = "qcom,crypto-v5.4", },
+	{ .compatible = "qcom,ipq6018-qce", },
+	{ .compatible = "qcom,sdm845-qce", },
 	{}
 };
 MODULE_DEVICE_TABLE(of, qce_crypto_of_match);
-- 
2.31.1


^ permalink raw reply related	[flat|nested] 52+ messages in thread

* [PATCH v4 16/20] crypto: qce: core: Make clocks optional
  2021-10-13 10:55 [PATCH v4 00/20] Enable Qualcomm Crypto Engine on sm8250 Bhupesh Sharma
                   ` (14 preceding siblings ...)
  2021-10-13 10:55 ` [PATCH v4 15/20] crypto: qce: Add new compatibles for qce crypto driver Bhupesh Sharma
@ 2021-10-13 10:55 ` Bhupesh Sharma
  2021-10-13 19:23   ` Vladimir Zapolskiy
  2021-10-13 10:55 ` [PATCH v4 17/20] crypto: qce: Print a failure msg in case probe() fails Bhupesh Sharma
                   ` (4 subsequent siblings)
  20 siblings, 1 reply; 52+ messages in thread
From: Bhupesh Sharma @ 2021-10-13 10:55 UTC (permalink / raw)
  To: linux-arm-msm, linux-crypto
  Cc: bhupesh.sharma, bhupesh.linux, linux-kernel, devicetree, robh+dt,
	agross, herbert, davem, Thara Gopinath

From: Thara Gopinath <thara.gopinath@linaro.org>

On certain Snapdragon processors, the crypto engine clocks are enabled by
default by security firmware and the driver need not/ should not handle the
clocks. Make acquiring of all the clocks optional in crypto enginer driver
so that the driver intializes properly even if no clocks are specified in
the dt.

Signed-off-by: Thara Gopinath <thara.gopinath@linaro.org>
---
 drivers/crypto/qce/core.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c
index 2ab0b97d718c..576c416461f9 100644
--- a/drivers/crypto/qce/core.c
+++ b/drivers/crypto/qce/core.c
@@ -213,19 +213,19 @@ static int qce_crypto_probe(struct platform_device *pdev)
 	if (IS_ERR(qce->mem_path))
 		return PTR_ERR(qce->mem_path);
 
-	qce->core = devm_clk_get(qce->dev, "core");
+	qce->core = devm_clk_get_optional(qce->dev, "core");
 	if (IS_ERR(qce->core)) {
 		ret = PTR_ERR(qce->core);
 		goto err_mem_path_put;
 	}
 
-	qce->iface = devm_clk_get(qce->dev, "iface");
+	qce->iface = devm_clk_get_optional(qce->dev, "iface");
 	if (IS_ERR(qce->iface)) {
 		ret = PTR_ERR(qce->iface);
 		goto err_mem_path_put;
 	}
 
-	qce->bus = devm_clk_get(qce->dev, "bus");
+	qce->bus = devm_clk_get_optional(qce->dev, "bus");
 	if (IS_ERR(qce->bus)) {
 		ret = PTR_ERR(qce->bus);
 		goto err_mem_path_put;
-- 
2.31.1


^ permalink raw reply related	[flat|nested] 52+ messages in thread

* [PATCH v4 17/20] crypto: qce: Print a failure msg in case probe() fails
  2021-10-13 10:55 [PATCH v4 00/20] Enable Qualcomm Crypto Engine on sm8250 Bhupesh Sharma
                   ` (15 preceding siblings ...)
  2021-10-13 10:55 ` [PATCH v4 16/20] crypto: qce: core: Make clocks optional Bhupesh Sharma
@ 2021-10-13 10:55 ` Bhupesh Sharma
  2021-10-13 19:26   ` Vladimir Zapolskiy
  2021-10-13 10:55 ` [PATCH v4 18/20] crypto: qce: Defer probing if BAM dma channel is not yet initialized Bhupesh Sharma
                   ` (3 subsequent siblings)
  20 siblings, 1 reply; 52+ messages in thread
From: Bhupesh Sharma @ 2021-10-13 10:55 UTC (permalink / raw)
  To: linux-arm-msm, linux-crypto
  Cc: bhupesh.sharma, bhupesh.linux, linux-kernel, devicetree, robh+dt,
	agross, herbert, davem, Bjorn Andersson, Thara Gopinath

Print a failure message (dev_err) in case the qcom qce crypto
driver probe() fails.

Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Reviewed-by: Thara Gopinath <thara.gopinath@linaro.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
 drivers/crypto/qce/core.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c
index 576c416461f9..cb8c77709e1e 100644
--- a/drivers/crypto/qce/core.c
+++ b/drivers/crypto/qce/core.c
@@ -281,6 +281,8 @@ static int qce_crypto_probe(struct platform_device *pdev)
 	icc_set_bw(qce->mem_path, 0, 0);
 err_mem_path_put:
 	icc_put(qce->mem_path);
+
+	dev_err(dev, "%s failed : %d\n", __func__, ret);
 	return ret;
 }
 
-- 
2.31.1


^ permalink raw reply related	[flat|nested] 52+ messages in thread

* [PATCH v4 18/20] crypto: qce: Defer probing if BAM dma channel is not yet initialized
  2021-10-13 10:55 [PATCH v4 00/20] Enable Qualcomm Crypto Engine on sm8250 Bhupesh Sharma
                   ` (16 preceding siblings ...)
  2021-10-13 10:55 ` [PATCH v4 17/20] crypto: qce: Print a failure msg in case probe() fails Bhupesh Sharma
@ 2021-10-13 10:55 ` Bhupesh Sharma
  2021-10-13 20:49   ` Vladimir Zapolskiy
  2021-10-20 14:10   ` Thara Gopinath
  2021-10-13 10:55 ` [PATCH v4 19/20] crypto: qce: Add 'sm8250-qce' compatible string check Bhupesh Sharma
                   ` (2 subsequent siblings)
  20 siblings, 2 replies; 52+ messages in thread
From: Bhupesh Sharma @ 2021-10-13 10:55 UTC (permalink / raw)
  To: linux-arm-msm, linux-crypto
  Cc: bhupesh.sharma, bhupesh.linux, linux-kernel, devicetree, robh+dt,
	agross, herbert, davem, Thara Gopinath, Bjorn Andersson

Since the Qualcomm qce crypto driver needs the BAM dma driver to be
setup first (to allow crypto operations), it makes sense to defer
the qce crypto driver probing in case the BAM dma driver is not yet
probed.

Move the code leg requesting dma channels earlier in the
probe() flow. This fixes the qce probe failure issues when both qce
and BMA dma are compiled as static part of the kernel.

Cc: Thara Gopinath <thara.gopinath@linaro.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
 drivers/crypto/qce/core.c | 20 ++++++++++++--------
 1 file changed, 12 insertions(+), 8 deletions(-)

diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c
index cb8c77709e1e..c6f686126fc9 100644
--- a/drivers/crypto/qce/core.c
+++ b/drivers/crypto/qce/core.c
@@ -209,9 +209,19 @@ static int qce_crypto_probe(struct platform_device *pdev)
 	if (ret < 0)
 		return ret;
 
+	/* qce driver requires BAM dma driver to be setup first.
+	 * In case the dma channel are not set yet, this check
+	 * helps use to return -EPROBE_DEFER earlier.
+	 */
+	ret = qce_dma_request(qce->dev, &qce->dma);
+	if (ret)
+		return ret;
+
 	qce->mem_path = of_icc_get(qce->dev, "memory");
-	if (IS_ERR(qce->mem_path))
+	if (IS_ERR(qce->mem_path)) {
+		qce_dma_release(&qce->dma);
 		return PTR_ERR(qce->mem_path);
+	}
 
 	qce->core = devm_clk_get_optional(qce->dev, "core");
 	if (IS_ERR(qce->core)) {
@@ -247,10 +257,6 @@ static int qce_crypto_probe(struct platform_device *pdev)
 	if (ret)
 		goto err_clks_iface;
 
-	ret = qce_dma_request(qce->dev, &qce->dma);
-	if (ret)
-		goto err_clks;
-
 	ret = qce_check_version(qce);
 	if (ret)
 		goto err_clks;
@@ -265,12 +271,10 @@ static int qce_crypto_probe(struct platform_device *pdev)
 
 	ret = qce_register_algs(qce);
 	if (ret)
-		goto err_dma;
+		goto err_clks;
 
 	return 0;
 
-err_dma:
-	qce_dma_release(&qce->dma);
 err_clks:
 	clk_disable_unprepare(qce->bus);
 err_clks_iface:
-- 
2.31.1


^ permalink raw reply related	[flat|nested] 52+ messages in thread

* [PATCH v4 19/20] crypto: qce: Add 'sm8250-qce' compatible string check
  2021-10-13 10:55 [PATCH v4 00/20] Enable Qualcomm Crypto Engine on sm8250 Bhupesh Sharma
                   ` (17 preceding siblings ...)
  2021-10-13 10:55 ` [PATCH v4 18/20] crypto: qce: Defer probing if BAM dma channel is not yet initialized Bhupesh Sharma
@ 2021-10-13 10:55 ` Bhupesh Sharma
  2021-10-20 14:11   ` Thara Gopinath
  2021-10-13 10:55 ` [PATCH v4 20/20] arm64/dts: qcom: sm8250: Add dt entries to support crypto engine Bhupesh Sharma
  2021-10-20 14:03 ` [PATCH v4 00/20] Enable Qualcomm Crypto Engine on sm8250 Thara Gopinath
  20 siblings, 1 reply; 52+ messages in thread
From: Bhupesh Sharma @ 2021-10-13 10:55 UTC (permalink / raw)
  To: linux-arm-msm, linux-crypto
  Cc: bhupesh.sharma, bhupesh.linux, linux-kernel, devicetree, robh+dt,
	agross, herbert, davem, Thara Gopinath, Bjorn Andersson

Add 'sm8250-qce' compatible string check in qce crypto
driver as we add support for sm8250 crypto device in the
device-tree in the subsequent patch.

Cc: Thara Gopinath <thara.gopinath@linaro.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
 drivers/crypto/qce/core.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c
index c6f686126fc9..4c55eceb4e7f 100644
--- a/drivers/crypto/qce/core.c
+++ b/drivers/crypto/qce/core.c
@@ -306,6 +306,7 @@ static int qce_crypto_remove(struct platform_device *pdev)
 static const struct of_device_id qce_crypto_of_match[] = {
 	{ .compatible = "qcom,ipq6018-qce", },
 	{ .compatible = "qcom,sdm845-qce", },
+	{ .compatible = "qcom,sm8250-qce", },
 	{}
 };
 MODULE_DEVICE_TABLE(of, qce_crypto_of_match);
-- 
2.31.1


^ permalink raw reply related	[flat|nested] 52+ messages in thread

* [PATCH v4 20/20] arm64/dts: qcom: sm8250: Add dt entries to support crypto engine.
  2021-10-13 10:55 [PATCH v4 00/20] Enable Qualcomm Crypto Engine on sm8250 Bhupesh Sharma
                   ` (18 preceding siblings ...)
  2021-10-13 10:55 ` [PATCH v4 19/20] crypto: qce: Add 'sm8250-qce' compatible string check Bhupesh Sharma
@ 2021-10-13 10:55 ` Bhupesh Sharma
  2021-10-20 14:03 ` [PATCH v4 00/20] Enable Qualcomm Crypto Engine on sm8250 Thara Gopinath
  20 siblings, 0 replies; 52+ messages in thread
From: Bhupesh Sharma @ 2021-10-13 10:55 UTC (permalink / raw)
  To: linux-arm-msm, linux-crypto
  Cc: bhupesh.sharma, bhupesh.linux, linux-kernel, devicetree, robh+dt,
	agross, herbert, davem, Thara Gopinath, Bjorn Andersson

Add crypto engine (CE) and CE BAM related nodes and definitions to
"sm8250.dtsi".

Cc: Thara Gopinath <thara.gopinath@linaro.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Signed-off-by: Thara Gopinath <thara.gopinath@linaro.org>
---
 arch/arm64/boot/dts/qcom/sm8250.dtsi | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 8c15d9fed08f..66cfd0b9c7e3 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -4103,6 +4103,34 @@ cpufreq_hw: cpufreq@18591000 {
 
 			#freq-domain-cells = <1>;
 		};
+
+		cryptobam: dma-controller@1dc4000 {
+			compatible = "qcom,bam-v1.7.0";
+			reg = <0 0x01dc4000 0 0x24000>;
+			interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+			#dma-cells = <1>;
+			qcom,ee = <0>;
+			qcom,controlled-remotely;
+			iommus = <&apps_smmu 0x584 0x0011>,
+				 <&apps_smmu 0x586 0x0011>,
+				 <&apps_smmu 0x594 0x0011>,
+				 <&apps_smmu 0x596 0x0011>;
+			interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 &mc_virt SLAVE_EBI_CH0>;
+			interconnect-names = "memory";
+		};
+
+		crypto: crypto@1dfa000 {
+			compatible = "qcom,sm8250-qce";
+			reg = <0 0x01dfa000 0 0x6000>;
+			dmas = <&cryptobam 4>, <&cryptobam 5>;
+			dma-names = "rx", "tx";
+			iommus = <&apps_smmu 0x584 0x0011>,
+				 <&apps_smmu 0x586 0x0011>,
+				 <&apps_smmu 0x594 0x0011>,
+				 <&apps_smmu 0x596 0x0011>;
+			interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 &mc_virt SLAVE_EBI_CH0>;
+			interconnect-names = "memory";
+		};
 	};
 
 	timer {
-- 
2.31.1


^ permalink raw reply related	[flat|nested] 52+ messages in thread

* Re: [PATCH v4 04/20] dt-bindings: qcom-bam: Convert binding to YAML
  2021-10-13 10:55 ` [PATCH v4 04/20] dt-bindings: qcom-bam: Convert binding to YAML Bhupesh Sharma
@ 2021-10-13 12:56   ` Vladimir Zapolskiy
  2021-10-13 17:13     ` Bhupesh Sharma
  0 siblings, 1 reply; 52+ messages in thread
From: Vladimir Zapolskiy @ 2021-10-13 12:56 UTC (permalink / raw)
  To: Bhupesh Sharma, linux-arm-msm, linux-crypto
  Cc: bhupesh.linux, linux-kernel, devicetree, robh+dt, agross,
	herbert, davem, Thara Gopinath, Bjorn Andersson

Hi Bhupesh,

On 10/13/21 1:55 PM, Bhupesh Sharma wrote:
> Convert Qualcomm BAM DMA devicetree binding to YAML.
> 
> Cc: Thara Gopinath <thara.gopinath@linaro.org>
> Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
> ---
>   .../devicetree/bindings/dma/qcom_bam_dma.txt  | 50 -----------
>   .../devicetree/bindings/dma/qcom_bam_dma.yaml | 89 +++++++++++++++++++
>   2 files changed, 89 insertions(+), 50 deletions(-)
>   delete mode 100644 Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
>   create mode 100644 Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml
> 
> diff --git a/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt b/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
> deleted file mode 100644
> index cf5b9e44432c..000000000000
> --- a/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
> +++ /dev/null
> @@ -1,50 +0,0 @@
> -QCOM BAM DMA controller
> -
> -Required properties:
> -- compatible: must be one of the following:
> - * "qcom,bam-v1.4.0" for MSM8974, APQ8074 and APQ8084
> - * "qcom,bam-v1.3.0" for APQ8064, IPQ8064 and MSM8960
> - * "qcom,bam-v1.7.0" for MSM8916
> -- reg: Address range for DMA registers
> -- interrupts: Should contain the one interrupt shared by all channels
> -- #dma-cells: must be <1>, the cell in the dmas property of the client device
> -  represents the channel number
> -- clocks: required clock
> -- clock-names: must contain "bam_clk" entry
> -- qcom,ee : indicates the active Execution Environment identifier (0-7) used in
> -  the secure world.
> -- qcom,controlled-remotely : optional, indicates that the bam is controlled by
> -  remote proccessor i.e. execution environment.
> -- num-channels : optional, indicates supported number of DMA channels in a
> -  remotely controlled bam.
> -- qcom,num-ees : optional, indicates supported number of Execution Environments
> -  in a remotely controlled bam.
> -
> -Example:
> -
> -	uart-bam: dma@f9984000 = {
> -		compatible = "qcom,bam-v1.4.0";
> -		reg = <0xf9984000 0x15000>;
> -		interrupts = <0 94 0>;
> -		clocks = <&gcc GCC_BAM_DMA_AHB_CLK>;
> -		clock-names = "bam_clk";
> -		#dma-cells = <1>;
> -		qcom,ee = <0>;
> -	};
> -
> -DMA clients must use the format described in the dma.txt file, using a two cell
> -specifier for each channel.
> -
> -Example:
> -	serial@f991e000 {
> -		compatible = "qcom,msm-uart";
> -		reg = <0xf991e000 0x1000>
> -			<0xf9944000 0x19000>;
> -		interrupts = <0 108 0>;
> -		clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
> -			<&gcc GCC_BLSP1_AHB_CLK>;
> -		clock-names = "core", "iface";
> -
> -		dmas = <&uart-bam 0>, <&uart-bam 1>;
> -		dma-names = "rx", "tx";
> -	};
> diff --git a/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml b/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml
> new file mode 100644
> index 000000000000..32b47e3b7769
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml
> @@ -0,0 +1,89 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/dma/qcom_bam_dma.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: QCOM BAM DMA controller binding
> +
> +maintainers:
> +  - Bhupesh Sharma <bhupesh.sharma@linaro.org>
> +
> +description: |
> +  This document defines the binding for the BAM DMA controller
> +  found on Qualcomm parts.
> +
> +allOf:
> +  - $ref: "dma-controller.yaml#"
> +
> +properties:
> +  compatible:
> +    enum:
> +      - qcom,bam-v1.4.0 # for MSM8974, APQ8074 and APQ8084
> +      - qcom,bam-v1.3.0 # for APQ8064, IPQ8064 and MSM8960
> +      - qcom,bam-v1.7.0 # for MSM8916

would it be better to sort the list above by IP version?

> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    maxItems: 1
> +
> +  clock-names:
> +    const: bam_clk
> +
> +  interrupts:
> +    minItems: 1
> +    maxItems: 31
> +
> +  num-channels:
> +    maximum: 31
> +    description: |
> +      Indicates supported number of DMA channels in a remotely controlled bam.

A comment about YAML specifics, I'm not sure, if it makes sense to set a control
to enable literal style of the given multiline description, since it is a one-liner.

My main observation though is that all actually multi-line descriptions in the
schema are different and of the folded style ("pipe" symbol is not set).

Probably it's good enough just to remove the "pipe" above.

> +
> +  "#dma-cells":
> +    const: 1
> +    description: The single cell represents the channel index.
> +
> +  qcom,ee:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    description:
> +      Indicates the active Execution Environment identifier (0-7)
> +      used in the secure world.

Would it make sense to add here

   minimum: 0
   maximum: 7

?

> +
> +  qcom,controlled-remotely:
> +    $ref: /schemas/types.yaml#/definitions/flag
> +    description:
> +      Indicates that the bam is controlled by remote proccessor i.e.
> +      execution environment.
> +
> +  qcom,num-ees:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    minimum: 0
> +    maximum: 31
> +    default: 2
> +    description:
> +      Indicates supported number of Execution Environments in a
> +      remotely controlled bam.
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - "#dma-cells"
> +  - qcom,ee
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/qcom,gcc-msm8974.h>
> +    dma-controller@f9984000 {
> +        compatible = "qcom,bam-v1.4.0";
> +        reg = <0xf9984000 0x15000>;
> +        interrupts = <0 94 0>;
> +        clocks = <&gcc GCC_BAM_DMA_AHB_CLK>;
> +        clock-names = "bam_clk";
> +        #dma-cells = <1>;
> +        qcom,ee = <0>;
> +    };
> 

--
Best wishes,
Vladimir

^ permalink raw reply	[flat|nested] 52+ messages in thread

* Re: [PATCH v4 05/20] dt-bindings: qcom-bam: Add 'interconnects' & 'interconnect-names' to optional properties
  2021-10-13 10:55 ` [PATCH v4 05/20] dt-bindings: qcom-bam: Add 'interconnects' & 'interconnect-names' to optional properties Bhupesh Sharma
@ 2021-10-13 13:03   ` Vladimir Zapolskiy
  2021-10-13 17:14     ` Bhupesh Sharma
  2021-10-13 18:39   ` Rob Herring
  1 sibling, 1 reply; 52+ messages in thread
From: Vladimir Zapolskiy @ 2021-10-13 13:03 UTC (permalink / raw)
  To: Bhupesh Sharma, linux-arm-msm, linux-crypto
  Cc: bhupesh.linux, linux-kernel, devicetree, robh+dt, agross,
	herbert, davem, Thara Gopinath, Bjorn Andersson

Hi Bhupesh,

On 10/13/21 1:55 PM, Bhupesh Sharma wrote:
> Add new optional properties - 'interconnects' and
> 'interconnect-names' to the device-tree binding documentation for
> qcom-bam DMA IP.
> 
> These properties describe the interconnect path between bam and main
> memory and the interconnect type respectively.
> 
> Cc: Thara Gopinath <thara.gopinath@linaro.org>
> Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
> ---
>   Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml | 8 ++++++++
>   1 file changed, 8 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml b/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml
> index 32b47e3b7769..602e68df971f 100644
> --- a/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml
> +++ b/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml
> @@ -45,6 +45,14 @@ properties:
>       const: 1
>       description: The single cell represents the channel index.
>   
> +  interconnects:
> +    maxItems: 1
> +    description: |

here I have the same comment about the set literal style of the
multi-line description, which is one-line, likely the specifier
is not needed...

> +      Interconnect path between bam and main memory.
> +
> +  interconnect-names:
> +    const: memory
> +
>     qcom,ee:
>       $ref: /schemas/types.yaml#/definitions/uint32
>       description:
> 

--
Best wishes,
Vladimir

^ permalink raw reply	[flat|nested] 52+ messages in thread

* Re: [PATCH v4 07/20] dt-bindings: qcom-qce: Convert bindings to yaml
  2021-10-13 10:55 ` [PATCH v4 07/20] dt-bindings: qcom-qce: Convert bindings to yaml Bhupesh Sharma
@ 2021-10-13 13:05   ` Vladimir Zapolskiy
  2021-10-13 17:15     ` Bhupesh Sharma
  0 siblings, 1 reply; 52+ messages in thread
From: Vladimir Zapolskiy @ 2021-10-13 13:05 UTC (permalink / raw)
  To: Bhupesh Sharma, linux-arm-msm, linux-crypto
  Cc: bhupesh.linux, linux-kernel, devicetree, robh+dt, agross,
	herbert, davem, Thara Gopinath, Bjorn Andersson, Rob Herring

Hi Bhupesh,

On 10/13/21 1:55 PM, Bhupesh Sharma wrote:
> Convert Qualcomm QCE crypto devicetree binding to YAML.
> 
> Cc: Thara Gopinath <thara.gopinath@linaro.org>
> Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> Reviewed-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
> ---
>   .../devicetree/bindings/crypto/qcom-qce.yaml  | 67 +++++++++++++++++++
>   1 file changed, 67 insertions(+)
>   create mode 100644 Documentation/devicetree/bindings/crypto/qcom-qce.yaml
> 
> diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
> new file mode 100644
> index 000000000000..b7ae873dc943
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
> @@ -0,0 +1,67 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/crypto/qcom-qce.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm crypto engine driver
> +
> +maintainers:
> +  - Bhupesh Sharma <bhupesh.sharma@linaro.org>
> +
> +description: |
> +  This document defines the binding for the QCE crypto
> +  controller found on Qualcomm parts.
> +
> +properties:
> +  compatible:
> +    const: qcom,crypto-v5.1
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    items:
> +      - description: iface clocks register interface.
> +      - description: bus clocks data transfer interface.
> +      - description: core clocks rest of the crypto block.
> +
> +  clock-names:
> +    items:
> +      - const: iface
> +      - const: bus
> +      - const: core
> +
> +  dmas:
> +    items:
> +      - description: DMA specifiers for tx dma channel.
> +      - description: DMA specifiers for rx dma channel.

Please consider to swap the description lines, so that they'll
be matching the dma-names below and a regular order found in
dts files.

> +
> +  dma-names:
> +    items:
> +      - const: rx
> +      - const: tx
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - clock-names
> +  - dmas
> +  - dma-names
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/qcom,gcc-apq8084.h>
> +    crypto-engine@fd45a000 {
> +        compatible = "qcom,crypto-v5.1";
> +        reg = <0xfd45a000 0x6000>;
> +        clocks = <&gcc GCC_CE2_AHB_CLK>,
> +                 <&gcc GCC_CE2_AXI_CLK>,
> +                 <&gcc GCC_CE2_CLK>;
> +        clock-names = "iface", "bus", "core";
> +        dmas = <&cryptobam 2>, <&cryptobam 3>;
> +        dma-names = "rx", "tx";
> +    };
> 

--
Best wishes,
Vladimir

^ permalink raw reply	[flat|nested] 52+ messages in thread

* Re: [PATCH v4 04/20] dt-bindings: qcom-bam: Convert binding to YAML
  2021-10-13 12:56   ` Vladimir Zapolskiy
@ 2021-10-13 17:13     ` Bhupesh Sharma
  0 siblings, 0 replies; 52+ messages in thread
From: Bhupesh Sharma @ 2021-10-13 17:13 UTC (permalink / raw)
  To: Vladimir Zapolskiy
  Cc: MSM, linux-crypto, bhupesh.linux, Linux Kernel Mailing List,
	devicetree, Rob Herring, Andy Gross, Herbert Xu,
	David S . Miller, Thara Gopinath, Bjorn Andersson

Hi Vladimir,

Thanks for your review.
Please see my replies inline:

On Wed, 13 Oct 2021 at 18:26, Vladimir Zapolskiy
<vladimir.zapolskiy@linaro.org> wrote:
>
> Hi Bhupesh,
>
> On 10/13/21 1:55 PM, Bhupesh Sharma wrote:
> > Convert Qualcomm BAM DMA devicetree binding to YAML.
> >
> > Cc: Thara Gopinath <thara.gopinath@linaro.org>
> > Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> > Cc: Rob Herring <robh+dt@kernel.org>
> > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
> > ---
> >   .../devicetree/bindings/dma/qcom_bam_dma.txt  | 50 -----------
> >   .../devicetree/bindings/dma/qcom_bam_dma.yaml | 89 +++++++++++++++++++
> >   2 files changed, 89 insertions(+), 50 deletions(-)
> >   delete mode 100644 Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
> >   create mode 100644 Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt b/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
> > deleted file mode 100644
> > index cf5b9e44432c..000000000000
> > --- a/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
> > +++ /dev/null
> > @@ -1,50 +0,0 @@
> > -QCOM BAM DMA controller
> > -
> > -Required properties:
> > -- compatible: must be one of the following:
> > - * "qcom,bam-v1.4.0" for MSM8974, APQ8074 and APQ8084
> > - * "qcom,bam-v1.3.0" for APQ8064, IPQ8064 and MSM8960
> > - * "qcom,bam-v1.7.0" for MSM8916
> > -- reg: Address range for DMA registers
> > -- interrupts: Should contain the one interrupt shared by all channels
> > -- #dma-cells: must be <1>, the cell in the dmas property of the client device
> > -  represents the channel number
> > -- clocks: required clock
> > -- clock-names: must contain "bam_clk" entry
> > -- qcom,ee : indicates the active Execution Environment identifier (0-7) used in
> > -  the secure world.
> > -- qcom,controlled-remotely : optional, indicates that the bam is controlled by
> > -  remote proccessor i.e. execution environment.
> > -- num-channels : optional, indicates supported number of DMA channels in a
> > -  remotely controlled bam.
> > -- qcom,num-ees : optional, indicates supported number of Execution Environments
> > -  in a remotely controlled bam.
> > -
> > -Example:
> > -
> > -     uart-bam: dma@f9984000 = {
> > -             compatible = "qcom,bam-v1.4.0";
> > -             reg = <0xf9984000 0x15000>;
> > -             interrupts = <0 94 0>;
> > -             clocks = <&gcc GCC_BAM_DMA_AHB_CLK>;
> > -             clock-names = "bam_clk";
> > -             #dma-cells = <1>;
> > -             qcom,ee = <0>;
> > -     };
> > -
> > -DMA clients must use the format described in the dma.txt file, using a two cell
> > -specifier for each channel.
> > -
> > -Example:
> > -     serial@f991e000 {
> > -             compatible = "qcom,msm-uart";
> > -             reg = <0xf991e000 0x1000>
> > -                     <0xf9944000 0x19000>;
> > -             interrupts = <0 108 0>;
> > -             clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
> > -                     <&gcc GCC_BLSP1_AHB_CLK>;
> > -             clock-names = "core", "iface";
> > -
> > -             dmas = <&uart-bam 0>, <&uart-bam 1>;
> > -             dma-names = "rx", "tx";
> > -     };
> > diff --git a/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml b/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml
> > new file mode 100644
> > index 000000000000..32b47e3b7769
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml
> > @@ -0,0 +1,89 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/dma/qcom_bam_dma.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: QCOM BAM DMA controller binding
> > +
> > +maintainers:
> > +  - Bhupesh Sharma <bhupesh.sharma@linaro.org>
> > +
> > +description: |
> > +  This document defines the binding for the BAM DMA controller
> > +  found on Qualcomm parts.
> > +
> > +allOf:
> > +  - $ref: "dma-controller.yaml#"
> > +
> > +properties:
> > +  compatible:
> > +    enum:
> > +      - qcom,bam-v1.4.0 # for MSM8974, APQ8074 and APQ8084
> > +      - qcom,bam-v1.3.0 # for APQ8064, IPQ8064 and MSM8960
> > +      - qcom,bam-v1.7.0 # for MSM8916
>
> would it be better to sort the list above by IP version?

Sure, I did not want to alter the ordering kept in the .txt version of
the device-tree bindings, but I have no strong objection to changing
and keeping the above sorted as per IP version  as well.

> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  clocks:
> > +    maxItems: 1
> > +
> > +  clock-names:
> > +    const: bam_clk
> > +
> > +  interrupts:
> > +    minItems: 1
> > +    maxItems: 31
> > +
> > +  num-channels:
> > +    maximum: 31
> > +    description: |
> > +      Indicates supported number of DMA channels in a remotely controlled bam.
>
> A comment about YAML specifics, I'm not sure, if it makes sense to set a control
> to enable literal style of the given multiline description, since it is a one-liner.
>
> My main observation though is that all actually multi-line descriptions in the
> schema are different and of the folded style ("pipe" symbol is not set).
>
> Probably it's good enough just to remove the "pipe" above.

Ok.

> > +
> > +  "#dma-cells":
> > +    const: 1
> > +    description: The single cell represents the channel index.
> > +
> > +  qcom,ee:
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> > +    description:
> > +      Indicates the active Execution Environment identifier (0-7)
> > +      used in the secure world.
>
> Would it make sense to add here
>
>    minimum: 0
>    maximum: 7

Ok, will try and if it passes 'make dtbs_check', will fix in v5.

Regards,
Bhupesh

> > +
> > +  qcom,controlled-remotely:
> > +    $ref: /schemas/types.yaml#/definitions/flag
> > +    description:
> > +      Indicates that the bam is controlled by remote proccessor i.e.
> > +      execution environment.
> > +
> > +  qcom,num-ees:
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> > +    minimum: 0
> > +    maximum: 31
> > +    default: 2
> > +    description:
> > +      Indicates supported number of Execution Environments in a
> > +      remotely controlled bam.
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - interrupts
> > +  - "#dma-cells"
> > +  - qcom,ee
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    #include <dt-bindings/clock/qcom,gcc-msm8974.h>
> > +    dma-controller@f9984000 {
> > +        compatible = "qcom,bam-v1.4.0";
> > +        reg = <0xf9984000 0x15000>;
> > +        interrupts = <0 94 0>;
> > +        clocks = <&gcc GCC_BAM_DMA_AHB_CLK>;
> > +        clock-names = "bam_clk";
> > +        #dma-cells = <1>;
> > +        qcom,ee = <0>;
> > +    };
> >
>
> --
> Best wishes,
> Vladimir

^ permalink raw reply	[flat|nested] 52+ messages in thread

* Re: [PATCH v4 05/20] dt-bindings: qcom-bam: Add 'interconnects' & 'interconnect-names' to optional properties
  2021-10-13 13:03   ` Vladimir Zapolskiy
@ 2021-10-13 17:14     ` Bhupesh Sharma
  0 siblings, 0 replies; 52+ messages in thread
From: Bhupesh Sharma @ 2021-10-13 17:14 UTC (permalink / raw)
  To: Vladimir Zapolskiy
  Cc: MSM, linux-crypto, bhupesh.linux, Linux Kernel Mailing List,
	devicetree, Rob Herring, Andy Gross, Herbert Xu,
	David S . Miller, Thara Gopinath, Bjorn Andersson

Hi Vladimir,

On Wed, 13 Oct 2021 at 18:33, Vladimir Zapolskiy
<vladimir.zapolskiy@linaro.org> wrote:
>
> Hi Bhupesh,
>
> On 10/13/21 1:55 PM, Bhupesh Sharma wrote:
> > Add new optional properties - 'interconnects' and
> > 'interconnect-names' to the device-tree binding documentation for
> > qcom-bam DMA IP.
> >
> > These properties describe the interconnect path between bam and main
> > memory and the interconnect type respectively.
> >
> > Cc: Thara Gopinath <thara.gopinath@linaro.org>
> > Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> > Cc: Rob Herring <robh+dt@kernel.org>
> > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
> > ---
> >   Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml | 8 ++++++++
> >   1 file changed, 8 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml b/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml
> > index 32b47e3b7769..602e68df971f 100644
> > --- a/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml
> > +++ b/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml
> > @@ -45,6 +45,14 @@ properties:
> >       const: 1
> >       description: The single cell represents the channel index.
> >
> > +  interconnects:
> > +    maxItems: 1
> > +    description: |
>
> here I have the same comment about the set literal style of the
> multi-line description, which is one-line, likely the specifier
> is not needed...

Ok, I will fix it in v5.

Regards,
Bhupesh

> > +      Interconnect path between bam and main memory.
> > +
> > +  interconnect-names:
> > +    const: memory
> > +
> >     qcom,ee:
> >       $ref: /schemas/types.yaml#/definitions/uint32
> >       description:
> >
>
> --
> Best wishes,
> Vladimir

^ permalink raw reply	[flat|nested] 52+ messages in thread

* Re: [PATCH v4 07/20] dt-bindings: qcom-qce: Convert bindings to yaml
  2021-10-13 13:05   ` Vladimir Zapolskiy
@ 2021-10-13 17:15     ` Bhupesh Sharma
  0 siblings, 0 replies; 52+ messages in thread
From: Bhupesh Sharma @ 2021-10-13 17:15 UTC (permalink / raw)
  To: Vladimir Zapolskiy
  Cc: MSM, linux-crypto, bhupesh.linux, Linux Kernel Mailing List,
	devicetree, Rob Herring, Andy Gross, Herbert Xu,
	David S . Miller, Thara Gopinath, Bjorn Andersson, Rob Herring

Hi Vladimir,

On Wed, 13 Oct 2021 at 18:35, Vladimir Zapolskiy
<vladimir.zapolskiy@linaro.org> wrote:
>
> Hi Bhupesh,
>
> On 10/13/21 1:55 PM, Bhupesh Sharma wrote:
> > Convert Qualcomm QCE crypto devicetree binding to YAML.
> >
> > Cc: Thara Gopinath <thara.gopinath@linaro.org>
> > Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> > Reviewed-by: Rob Herring <robh@kernel.org>
> > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
> > ---
> >   .../devicetree/bindings/crypto/qcom-qce.yaml  | 67 +++++++++++++++++++
> >   1 file changed, 67 insertions(+)
> >   create mode 100644 Documentation/devicetree/bindings/crypto/qcom-qce.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
> > new file mode 100644
> > index 000000000000..b7ae873dc943
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
> > @@ -0,0 +1,67 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/crypto/qcom-qce.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Qualcomm crypto engine driver
> > +
> > +maintainers:
> > +  - Bhupesh Sharma <bhupesh.sharma@linaro.org>
> > +
> > +description: |
> > +  This document defines the binding for the QCE crypto
> > +  controller found on Qualcomm parts.
> > +
> > +properties:
> > +  compatible:
> > +    const: qcom,crypto-v5.1
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  clocks:
> > +    items:
> > +      - description: iface clocks register interface.
> > +      - description: bus clocks data transfer interface.
> > +      - description: core clocks rest of the crypto block.
> > +
> > +  clock-names:
> > +    items:
> > +      - const: iface
> > +      - const: bus
> > +      - const: core
> > +
> > +  dmas:
> > +    items:
> > +      - description: DMA specifiers for tx dma channel.
> > +      - description: DMA specifiers for rx dma channel.
>
> Please consider to swap the description lines, so that they'll
> be matching the dma-names below and a regular order found in
> dts files.

Ok, I will fix it in v5.

Regards,
Bhupesh

> > +
> > +  dma-names:
> > +    items:
> > +      - const: rx
> > +      - const: tx
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - clocks
> > +  - clock-names
> > +  - dmas
> > +  - dma-names
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    #include <dt-bindings/clock/qcom,gcc-apq8084.h>
> > +    crypto-engine@fd45a000 {
> > +        compatible = "qcom,crypto-v5.1";
> > +        reg = <0xfd45a000 0x6000>;
> > +        clocks = <&gcc GCC_CE2_AHB_CLK>,
> > +                 <&gcc GCC_CE2_AXI_CLK>,
> > +                 <&gcc GCC_CE2_CLK>;
> > +        clock-names = "iface", "bus", "core";
> > +        dmas = <&cryptobam 2>, <&cryptobam 3>;
> > +        dma-names = "rx", "tx";
> > +    };
> >
>
> --
> Best wishes,
> Vladimir

^ permalink raw reply	[flat|nested] 52+ messages in thread

* Re: [PATCH v4 05/20] dt-bindings: qcom-bam: Add 'interconnects' & 'interconnect-names' to optional properties
  2021-10-13 10:55 ` [PATCH v4 05/20] dt-bindings: qcom-bam: Add 'interconnects' & 'interconnect-names' to optional properties Bhupesh Sharma
  2021-10-13 13:03   ` Vladimir Zapolskiy
@ 2021-10-13 18:39   ` Rob Herring
  2021-10-14  7:03     ` Bhupesh Sharma
  1 sibling, 1 reply; 52+ messages in thread
From: Rob Herring @ 2021-10-13 18:39 UTC (permalink / raw)
  To: Bhupesh Sharma
  Cc: herbert, devicetree, robh+dt, Thara Gopinath, bhupesh.linux,
	agross, linux-arm-msm, linux-crypto, davem, Bjorn Andersson,
	linux-kernel

On Wed, 13 Oct 2021 16:25:26 +0530, Bhupesh Sharma wrote:
> Add new optional properties - 'interconnects' and
> 'interconnect-names' to the device-tree binding documentation for
> qcom-bam DMA IP.
> 
> These properties describe the interconnect path between bam and main
> memory and the interconnect type respectively.
> 
> Cc: Thara Gopinath <thara.gopinath@linaro.org>
> Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
> ---
>  Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 

Running 'make dtbs_check' with the schema in this patch gives the
following warnings. Consider if they are expected or the schema is
incorrect. These may not be new warnings.

Note that it is not yet a requirement to have 0 warnings for dtbs_check.
This will change in the future.

Full log is available here: https://patchwork.ozlabs.org/patch/1540390


dma@12142000: $nodename:0: 'dma@12142000' does not match '^dma-controller(@.*)?$'
	arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dt.yaml

dma@12182000: $nodename:0: 'dma@12182000' does not match '^dma-controller(@.*)?$'
	arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dt.yaml
	arch/arm/boot/dts/qcom-apq8064-cm-qs600.dt.yaml
	arch/arm/boot/dts/qcom-apq8064-ifc6410.dt.yaml
	arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dt.yaml
	arch/arm/boot/dts/qcom-ipq8064-ap148.dt.yaml
	arch/arm/boot/dts/qcom-ipq8064-rb3011.dt.yaml
	arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dt.yaml

dma@121c2000: $nodename:0: 'dma@121c2000' does not match '^dma-controller(@.*)?$'
	arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dt.yaml
	arch/arm/boot/dts/qcom-apq8064-cm-qs600.dt.yaml
	arch/arm/boot/dts/qcom-apq8064-ifc6410.dt.yaml
	arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dt.yaml

dma@12402000: $nodename:0: 'dma@12402000' does not match '^dma-controller(@.*)?$'
	arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dt.yaml
	arch/arm/boot/dts/qcom-apq8064-cm-qs600.dt.yaml
	arch/arm/boot/dts/qcom-apq8064-ifc6410.dt.yaml
	arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dt.yaml
	arch/arm/boot/dts/qcom-ipq8064-ap148.dt.yaml
	arch/arm/boot/dts/qcom-ipq8064-rb3011.dt.yaml

dma@1dc4000: $nodename:0: 'dma@1dc4000' does not match '^dma-controller(@.*)?$'
	arch/arm64/boot/dts/qcom/sdm845-cheza-r1.dt.yaml
	arch/arm64/boot/dts/qcom/sdm845-cheza-r2.dt.yaml
	arch/arm64/boot/dts/qcom/sdm845-cheza-r3.dt.yaml
	arch/arm64/boot/dts/qcom/sdm845-db845c.dt.yaml
	arch/arm64/boot/dts/qcom/sdm845-mtp.dt.yaml
	arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dt.yaml
	arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dt.yaml
	arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dt.yaml
	arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dt.yaml

dma@1dc4000: 'iommus' does not match any of the regexes: 'pinctrl-[0-9]+'
	arch/arm64/boot/dts/qcom/sdm845-cheza-r1.dt.yaml
	arch/arm64/boot/dts/qcom/sdm845-cheza-r2.dt.yaml
	arch/arm64/boot/dts/qcom/sdm845-cheza-r3.dt.yaml
	arch/arm64/boot/dts/qcom/sdm845-db845c.dt.yaml
	arch/arm64/boot/dts/qcom/sdm845-mtp.dt.yaml
	arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dt.yaml
	arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dt.yaml
	arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dt.yaml
	arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dt.yaml

dma@1dc4000: qcom,controlled-remotely: 'oneOf' conditional failed, one must be fixed:
	arch/arm64/boot/dts/qcom/sdm845-cheza-r1.dt.yaml
	arch/arm64/boot/dts/qcom/sdm845-cheza-r2.dt.yaml
	arch/arm64/boot/dts/qcom/sdm845-cheza-r3.dt.yaml
	arch/arm64/boot/dts/qcom/sdm845-db845c.dt.yaml
	arch/arm64/boot/dts/qcom/sdm845-mtp.dt.yaml
	arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dt.yaml
	arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dt.yaml
	arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dt.yaml
	arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dt.yaml

dma@704000: $nodename:0: 'dma@704000' does not match '^dma-controller(@.*)?$'
	arch/arm64/boot/dts/qcom/ipq8074-hk01.dt.yaml
	arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dt.yaml
	arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dt.yaml

dma@704000: qcom,controlled-remotely: 'oneOf' conditional failed, one must be fixed:
	arch/arm64/boot/dts/qcom/ipq8074-hk01.dt.yaml
	arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dt.yaml
	arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dt.yaml

dma@7544000: $nodename:0: 'dma@7544000' does not match '^dma-controller(@.*)?$'
	arch/arm64/boot/dts/qcom/apq8096-db820c.dt.yaml
	arch/arm64/boot/dts/qcom/apq8096-ifc6640.dt.yaml
	arch/arm64/boot/dts/qcom/msm8996-mtp.dt.yaml
	arch/arm64/boot/dts/qcom/msm8996-pmi8996-sony-xperia-tone-dora.dt.yaml
	arch/arm64/boot/dts/qcom/msm8996-pmi8996-sony-xperia-tone-kagura.dt.yaml
	arch/arm64/boot/dts/qcom/msm8996-pmi8996-sony-xperia-tone-keyaki.dt.yaml
	arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone-dora.dt.yaml
	arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone-kagura.dt.yaml
	arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone-keyaki.dt.yaml

dma@7584000: $nodename:0: 'dma@7584000' does not match '^dma-controller(@.*)?$'
	arch/arm64/boot/dts/qcom/apq8096-db820c.dt.yaml
	arch/arm64/boot/dts/qcom/apq8096-ifc6640.dt.yaml
	arch/arm64/boot/dts/qcom/msm8996-mtp.dt.yaml
	arch/arm64/boot/dts/qcom/msm8996-pmi8996-sony-xperia-tone-dora.dt.yaml
	arch/arm64/boot/dts/qcom/msm8996-pmi8996-sony-xperia-tone-kagura.dt.yaml
	arch/arm64/boot/dts/qcom/msm8996-pmi8996-sony-xperia-tone-keyaki.dt.yaml
	arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone-dora.dt.yaml
	arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone-kagura.dt.yaml
	arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone-keyaki.dt.yaml

dma@7884000: $nodename:0: 'dma@7884000' does not match '^dma-controller(@.*)?$'
	arch/arm/boot/dts/qcom-ipq4018-ap120c-ac-bit.dt.yaml
	arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dt.yaml
	arch/arm/boot/dts/qcom-ipq4018-jalapeno.dt.yaml
	arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dt.yaml
	arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dt.yaml
	arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dt.yaml
	arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dt.yaml
	arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dt.yaml

dma@7984000: $nodename:0: 'dma@7984000' does not match '^dma-controller(@.*)?$'
	arch/arm/boot/dts/qcom-ipq4018-ap120c-ac-bit.dt.yaml
	arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dt.yaml
	arch/arm/boot/dts/qcom-ipq4018-jalapeno.dt.yaml
	arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dt.yaml
	arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dt.yaml
	arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dt.yaml
	arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dt.yaml
	arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dt.yaml

dma@8e04000: $nodename:0: 'dma@8e04000' does not match '^dma-controller(@.*)?$'
	arch/arm/boot/dts/qcom-ipq4018-ap120c-ac-bit.dt.yaml
	arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dt.yaml
	arch/arm/boot/dts/qcom-ipq4018-jalapeno.dt.yaml
	arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dt.yaml
	arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dt.yaml
	arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dt.yaml
	arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dt.yaml
	arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dt.yaml

dma@c184000: $nodename:0: 'dma@c184000' does not match '^dma-controller(@.*)?$'
	arch/arm64/boot/dts/qcom/msm8998-asus-novago-tp370ql.dt.yaml
	arch/arm64/boot/dts/qcom/msm8998-hp-envy-x2.dt.yaml
	arch/arm64/boot/dts/qcom/msm8998-lenovo-miix-630.dt.yaml
	arch/arm64/boot/dts/qcom/msm8998-mtp.dt.yaml
	arch/arm64/boot/dts/qcom/msm8998-oneplus-cheeseburger.dt.yaml
	arch/arm64/boot/dts/qcom/msm8998-oneplus-dumpling.dt.yaml

dma-controller@17184000: 'iommus' does not match any of the regexes: 'pinctrl-[0-9]+'
	arch/arm64/boot/dts/qcom/sdm845-cheza-r1.dt.yaml
	arch/arm64/boot/dts/qcom/sdm845-cheza-r2.dt.yaml
	arch/arm64/boot/dts/qcom/sdm845-cheza-r3.dt.yaml
	arch/arm64/boot/dts/qcom/sdm845-db845c.dt.yaml
	arch/arm64/boot/dts/qcom/sdm845-mtp.dt.yaml
	arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dt.yaml
	arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dt.yaml
	arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dt.yaml
	arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dt.yaml

dma-controller@704000: 'qcom,config-pipe-trust-reg' does not match any of the regexes: 'pinctrl-[0-9]+'
	arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dt.yaml

dma-controller@704000: qcom,controlled-remotely: 'oneOf' conditional failed, one must be fixed:
	arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dt.yaml

dma-controller@7984000: clock-names:0: 'bam_clk' was expected
	arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dt.yaml

dma-controller@7984000: clock-names: Additional items are not allowed ('bam_clk' was unexpected)
	arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dt.yaml

dma-controller@7984000: clock-names: ['iface_clk', 'bam_clk'] is too long
	arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dt.yaml

dma-controller@7984000: clocks: [[9, 138], [9, 137]] is too long
	arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dt.yaml


^ permalink raw reply	[flat|nested] 52+ messages in thread

* Re: [PATCH v4 13/20] dma: qcom: bam_dma: Add support to initialize interconnect path
  2021-10-13 10:55 ` [PATCH v4 13/20] dma: qcom: bam_dma: Add support to initialize interconnect path Bhupesh Sharma
@ 2021-10-13 19:15   ` Vladimir Zapolskiy
  2021-10-24 13:53     ` Bhupesh Sharma
  0 siblings, 1 reply; 52+ messages in thread
From: Vladimir Zapolskiy @ 2021-10-13 19:15 UTC (permalink / raw)
  To: Bhupesh Sharma, linux-arm-msm, linux-crypto
  Cc: bhupesh.linux, linux-kernel, devicetree, robh+dt, agross,
	herbert, davem, Thara Gopinath, Bjorn Andersson

Hi Bhupesh, Thara,

On 10/13/21 1:55 PM, Bhupesh Sharma wrote:
> From: Thara Gopinath <thara.gopinath@linaro.org>
> 
> BAM dma engine associated with certain hardware blocks could require
> relevant interconnect pieces be initialized prior to the dma engine
> initialization. For e.g. crypto bam dma engine on sm8250. Such requirement
> is passed on to the bam dma driver from dt via the "interconnects"
> property.  Add support in bam_dma driver to check whether the interconnect
> path is accessible/enabled prior to attempting driver intializations.
> 
> Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
> [Make header file inclusion alphabetical]
> Signed-off-by: Thara Gopinath <thara.gopinath@linaro.org>
> ---
>   drivers/dma/qcom/bam_dma.c | 16 +++++++++++++++-
>   1 file changed, 15 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/dma/qcom/bam_dma.c b/drivers/dma/qcom/bam_dma.c
> index c8a77b428b52..fc84ef42507d 100644
> --- a/drivers/dma/qcom/bam_dma.c
> +++ b/drivers/dma/qcom/bam_dma.c
> @@ -26,6 +26,7 @@
>   #include <linux/kernel.h>
>   #include <linux/io.h>
>   #include <linux/init.h>
> +#include <linux/interconnect.h>
>   #include <linux/slab.h>
>   #include <linux/module.h>
>   #include <linux/interrupt.h>
> @@ -392,6 +393,7 @@ struct bam_device {
>   	const struct reg_offset_data *layout;
>   
>   	struct clk *bamclk;
> +	struct icc_path *mem_path;
>   	int irq;
>   
>   	/* dma start transaction tasklet */
> @@ -1284,9 +1286,18 @@ static int bam_dma_probe(struct platform_device *pdev)
>   		return ret;
>   	}
>   
> +	/* Ensure that interconnects are initialized */
> +	bdev->mem_path = of_icc_get(bdev->dev, "memory");

I suppose devm_of_icc_get() usage could leave the error path and
bam_dma_remove() intact.

> +
> +	if (IS_ERR(bdev->mem_path)) {
> +		ret = PTR_ERR(bdev->mem_path);
> +		dev_err(bdev->dev, "failed to acquire icc path %d\n", ret);
> +		goto err_disable_clk;
> +	}
> +
>   	ret = bam_init(bdev);
>   	if (ret)
> -		goto err_disable_clk;
> +		goto err_icc_path_put;
>   
>   	tasklet_setup(&bdev->task, dma_tasklet);
>   
> @@ -1371,6 +1382,8 @@ static int bam_dma_probe(struct platform_device *pdev)
>   		tasklet_kill(&bdev->channels[i].vc.task);
>   err_tasklet_kill:
>   	tasklet_kill(&bdev->task);
> +err_icc_path_put:
> +	icc_put(bdev->mem_path);
>   err_disable_clk:
>   	clk_disable_unprepare(bdev->bamclk);
>   
> @@ -1406,6 +1419,7 @@ static int bam_dma_remove(struct platform_device *pdev)
>   
>   	tasklet_kill(&bdev->task);
>   
> +	icc_put(bdev->mem_path);
>   	clk_disable_unprepare(bdev->bamclk);
>   
>   	return 0;
> 

--
Best wishes,
Vladimir

^ permalink raw reply	[flat|nested] 52+ messages in thread

* Re: [PATCH v4 14/20] crypto: qce: core: Add support to initialize interconnect path
  2021-10-13 10:55 ` [PATCH v4 14/20] crypto: qce: core: " Bhupesh Sharma
@ 2021-10-13 19:19   ` Vladimir Zapolskiy
  2021-10-24 13:53     ` Bhupesh Sharma
  0 siblings, 1 reply; 52+ messages in thread
From: Vladimir Zapolskiy @ 2021-10-13 19:19 UTC (permalink / raw)
  To: Bhupesh Sharma, linux-arm-msm, linux-crypto
  Cc: bhupesh.linux, linux-kernel, devicetree, robh+dt, agross,
	herbert, davem, Thara Gopinath, Bjorn Andersson

Hi Bhupesh,

On 10/13/21 1:55 PM, Bhupesh Sharma wrote:
> From: Thara Gopinath <thara.gopinath@linaro.org>
> 
> Crypto engine on certain Snapdragon processors like sm8150, sm8250, sm8350
> etc. requires interconnect path between the engine and memory to be
> explicitly enabled and bandwidth set prior to any operations. Add support
> in the qce core to enable the interconnect path appropriately.
> 
> Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
> [Make header file inclusion alphabetical]
> Signed-off-by: Thara Gopinath <thara.gopinath@linaro.org>
> ---
>   drivers/crypto/qce/core.c | 35 ++++++++++++++++++++++++++++-------
>   drivers/crypto/qce/core.h |  1 +
>   2 files changed, 29 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c
> index d3780be44a76..033c7278aa5d 100644
> --- a/drivers/crypto/qce/core.c
> +++ b/drivers/crypto/qce/core.c
> @@ -5,6 +5,7 @@
>   
>   #include <linux/clk.h>
>   #include <linux/dma-mapping.h>
> +#include <linux/interconnect.h>
>   #include <linux/interrupt.h>
>   #include <linux/module.h>
>   #include <linux/mod_devicetable.h>
> @@ -22,6 +23,8 @@
>   #define QCE_MAJOR_VERSION5	0x05
>   #define QCE_QUEUE_LENGTH	1
>   
> +#define QCE_DEFAULT_MEM_BANDWIDTH	393600
> +
>   static const struct qce_algo_ops *qce_ops[] = {
>   #ifdef CONFIG_CRYPTO_DEV_QCE_SKCIPHER
>   	&skcipher_ops,
> @@ -206,21 +209,35 @@ static int qce_crypto_probe(struct platform_device *pdev)
>   	if (ret < 0)
>   		return ret;
>   
> +	qce->mem_path = of_icc_get(qce->dev, "memory");

Please consider to use devm_of_icc_get() here also.

> +	if (IS_ERR(qce->mem_path))
> +		return PTR_ERR(qce->mem_path);
> +
>   	qce->core = devm_clk_get(qce->dev, "core");
> -	if (IS_ERR(qce->core))
> -		return PTR_ERR(qce->core);
> +	if (IS_ERR(qce->core)) {
> +		ret = PTR_ERR(qce->core);
> +		goto err_mem_path_put;
> +	}
>   
>   	qce->iface = devm_clk_get(qce->dev, "iface");
> -	if (IS_ERR(qce->iface))
> -		return PTR_ERR(qce->iface);
> +	if (IS_ERR(qce->iface)) {
> +		ret = PTR_ERR(qce->iface);
> +		goto err_mem_path_put;
> +	}
>   
>   	qce->bus = devm_clk_get(qce->dev, "bus");
> -	if (IS_ERR(qce->bus))
> -		return PTR_ERR(qce->bus);
> +	if (IS_ERR(qce->bus)) {
> +		ret = PTR_ERR(qce->bus);
> +		goto err_mem_path_put;
> +	}
> +
> +	ret = icc_set_bw(qce->mem_path, QCE_DEFAULT_MEM_BANDWIDTH, QCE_DEFAULT_MEM_BANDWIDTH);
> +	if (ret)
> +		goto err_mem_path_put;
>   
>   	ret = clk_prepare_enable(qce->core);
>   	if (ret)
> -		return ret;
> +		goto err_mem_path_disable;
>   
>   	ret = clk_prepare_enable(qce->iface);
>   	if (ret)
> @@ -260,6 +277,10 @@ static int qce_crypto_probe(struct platform_device *pdev)
>   	clk_disable_unprepare(qce->iface);
>   err_clks_core:
>   	clk_disable_unprepare(qce->core);
> +err_mem_path_disable:
> +	icc_set_bw(qce->mem_path, 0, 0);
> +err_mem_path_put:
> +	icc_put(qce->mem_path);
>   	return ret;
>   }
>   
> diff --git a/drivers/crypto/qce/core.h b/drivers/crypto/qce/core.h
> index 085774cdf641..228fcd69ec51 100644
> --- a/drivers/crypto/qce/core.h
> +++ b/drivers/crypto/qce/core.h
> @@ -35,6 +35,7 @@ struct qce_device {
>   	void __iomem *base;
>   	struct device *dev;
>   	struct clk *core, *iface, *bus;
> +	struct icc_path *mem_path;
>   	struct qce_dma_data dma;
>   	int burst_size;
>   	unsigned int pipe_pair_id;
> 

--
Best wishes,
Vladimir

^ permalink raw reply	[flat|nested] 52+ messages in thread

* Re: [PATCH v4 15/20] crypto: qce: Add new compatibles for qce crypto driver
  2021-10-13 10:55 ` [PATCH v4 15/20] crypto: qce: Add new compatibles for qce crypto driver Bhupesh Sharma
@ 2021-10-13 19:22   ` Vladimir Zapolskiy
  2021-10-20 14:07   ` Thara Gopinath
  1 sibling, 0 replies; 52+ messages in thread
From: Vladimir Zapolskiy @ 2021-10-13 19:22 UTC (permalink / raw)
  To: Bhupesh Sharma, linux-arm-msm, linux-crypto
  Cc: bhupesh.linux, linux-kernel, devicetree, robh+dt, agross,
	herbert, davem, Thara Gopinath, Bjorn Andersson

Hi Bhupesh,

On 10/13/21 1:55 PM, Bhupesh Sharma wrote:
> Since we decided to use soc specific compatibles for describing
> the qce crypto IP nodes in the device-trees, adapt the driver
> now to handle the same.
> 
> Cc: Thara Gopinath <thara.gopinath@linaro.org>
> Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
> ---
>   drivers/crypto/qce/core.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c
> index 033c7278aa5d..2ab0b97d718c 100644
> --- a/drivers/crypto/qce/core.c
> +++ b/drivers/crypto/qce/core.c
> @@ -298,8 +298,8 @@ static int qce_crypto_remove(struct platform_device *pdev)
>   }
>   
>   static const struct of_device_id qce_crypto_of_match[] = {
> -	{ .compatible = "qcom,crypto-v5.1", },
> -	{ .compatible = "qcom,crypto-v5.4", },

This breaks backward compatibility with old/not updated dtbs, I'm not sure, if
that common rule has to be kept here, but at least it's worth to be mentioned.

> +	{ .compatible = "qcom,ipq6018-qce", },
> +	{ .compatible = "qcom,sdm845-qce", },
>   	{}
>   };
>   MODULE_DEVICE_TABLE(of, qce_crypto_of_match);
> 

--
Best wishes,
Vladimir

^ permalink raw reply	[flat|nested] 52+ messages in thread

* Re: [PATCH v4 16/20] crypto: qce: core: Make clocks optional
  2021-10-13 10:55 ` [PATCH v4 16/20] crypto: qce: core: Make clocks optional Bhupesh Sharma
@ 2021-10-13 19:23   ` Vladimir Zapolskiy
  2021-10-24 13:34     ` Bhupesh Sharma
  0 siblings, 1 reply; 52+ messages in thread
From: Vladimir Zapolskiy @ 2021-10-13 19:23 UTC (permalink / raw)
  To: Bhupesh Sharma, linux-arm-msm, linux-crypto
  Cc: bhupesh.linux, linux-kernel, devicetree, robh+dt, agross,
	herbert, davem, Thara Gopinath

Hi Bhupesh,

On 10/13/21 1:55 PM, Bhupesh Sharma wrote:
> From: Thara Gopinath <thara.gopinath@linaro.org>
> 
> On certain Snapdragon processors, the crypto engine clocks are enabled by
> default by security firmware and the driver need not/ should not handle the
> clocks. Make acquiring of all the clocks optional in crypto enginer driver

typo, s/enginer/engine/

> so that the driver intializes properly even if no clocks are specified in

typo, s/intializes/initializes/

> the dt.
> 
> Signed-off-by: Thara Gopinath <thara.gopinath@linaro.org>
> ---
>   drivers/crypto/qce/core.c | 6 +++---
>   1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c
> index 2ab0b97d718c..576c416461f9 100644
> --- a/drivers/crypto/qce/core.c
> +++ b/drivers/crypto/qce/core.c
> @@ -213,19 +213,19 @@ static int qce_crypto_probe(struct platform_device *pdev)
>   	if (IS_ERR(qce->mem_path))
>   		return PTR_ERR(qce->mem_path);
>   
> -	qce->core = devm_clk_get(qce->dev, "core");
> +	qce->core = devm_clk_get_optional(qce->dev, "core");
>   	if (IS_ERR(qce->core)) {
>   		ret = PTR_ERR(qce->core);
>   		goto err_mem_path_put;
>   	}
>   
> -	qce->iface = devm_clk_get(qce->dev, "iface");
> +	qce->iface = devm_clk_get_optional(qce->dev, "iface");
>   	if (IS_ERR(qce->iface)) {
>   		ret = PTR_ERR(qce->iface);
>   		goto err_mem_path_put;
>   	}
>   
> -	qce->bus = devm_clk_get(qce->dev, "bus");
> +	qce->bus = devm_clk_get_optional(qce->dev, "bus");
>   	if (IS_ERR(qce->bus)) {
>   		ret = PTR_ERR(qce->bus);
>   		goto err_mem_path_put;
> 

--
Best wishes,
Vladimir

^ permalink raw reply	[flat|nested] 52+ messages in thread

* Re: [PATCH v4 17/20] crypto: qce: Print a failure msg in case probe() fails
  2021-10-13 10:55 ` [PATCH v4 17/20] crypto: qce: Print a failure msg in case probe() fails Bhupesh Sharma
@ 2021-10-13 19:26   ` Vladimir Zapolskiy
  2021-10-24 13:33     ` Bhupesh Sharma
  0 siblings, 1 reply; 52+ messages in thread
From: Vladimir Zapolskiy @ 2021-10-13 19:26 UTC (permalink / raw)
  To: Bhupesh Sharma, linux-arm-msm, linux-crypto
  Cc: bhupesh.linux, linux-kernel, devicetree, robh+dt, agross,
	herbert, davem, Bjorn Andersson, Thara Gopinath

Hi Bhupesh,

On 10/13/21 1:55 PM, Bhupesh Sharma wrote:
> Print a failure message (dev_err) in case the qcom qce crypto
> driver probe() fails.
> 
> Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Reviewed-by: Thara Gopinath <thara.gopinath@linaro.org>
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
> ---
>   drivers/crypto/qce/core.c | 2 ++
>   1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c
> index 576c416461f9..cb8c77709e1e 100644
> --- a/drivers/crypto/qce/core.c
> +++ b/drivers/crypto/qce/core.c
> @@ -281,6 +281,8 @@ static int qce_crypto_probe(struct platform_device *pdev)
>   	icc_set_bw(qce->mem_path, 0, 0);
>   err_mem_path_put:
>   	icc_put(qce->mem_path);
> +
> +	dev_err(dev, "%s failed : %d\n", __func__, ret);
>   	return ret;
>   }
>   

As for me the rationale of this change is quite non-obvious, a user is well
informed, if a driver probe fails. I would rather ask you to consider to
drop this change.

--
Best wishes,
Vladimir

^ permalink raw reply	[flat|nested] 52+ messages in thread

* Re: [PATCH v4 18/20] crypto: qce: Defer probing if BAM dma channel is not yet initialized
  2021-10-13 10:55 ` [PATCH v4 18/20] crypto: qce: Defer probing if BAM dma channel is not yet initialized Bhupesh Sharma
@ 2021-10-13 20:49   ` Vladimir Zapolskiy
  2021-10-14  7:40     ` Bhupesh Sharma
  2021-10-20 14:10   ` Thara Gopinath
  1 sibling, 1 reply; 52+ messages in thread
From: Vladimir Zapolskiy @ 2021-10-13 20:49 UTC (permalink / raw)
  To: Bhupesh Sharma, linux-arm-msm, linux-crypto
  Cc: bhupesh.linux, linux-kernel, devicetree, robh+dt, agross,
	herbert, davem, Thara Gopinath, Bjorn Andersson

Hi Bhupesh,

On 10/13/21 1:55 PM, Bhupesh Sharma wrote:
> Since the Qualcomm qce crypto driver needs the BAM dma driver to be
> setup first (to allow crypto operations), it makes sense to defer
> the qce crypto driver probing in case the BAM dma driver is not yet
> probed.
> 
> Move the code leg requesting dma channels earlier in the
> probe() flow. This fixes the qce probe failure issues when both qce
> and BMA dma are compiled as static part of the kernel.
> 
> Cc: Thara Gopinath <thara.gopinath@linaro.org>
> Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
> ---
>   drivers/crypto/qce/core.c | 20 ++++++++++++--------
>   1 file changed, 12 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c
> index cb8c77709e1e..c6f686126fc9 100644
> --- a/drivers/crypto/qce/core.c
> +++ b/drivers/crypto/qce/core.c
> @@ -209,9 +209,19 @@ static int qce_crypto_probe(struct platform_device *pdev)
>   	if (ret < 0)
>   		return ret;
>   
> +	/* qce driver requires BAM dma driver to be setup first.

I believe a multi-line block of comments should be started with '/*' line,
for reference please take a look at Documentation/process/coding-style.rst

> +	 * In case the dma channel are not set yet, this check
> +	 * helps use to return -EPROBE_DEFER earlier.
> +	 */
> +	ret = qce_dma_request(qce->dev, &qce->dma);
> +	if (ret)
> +		return ret;
> +
>   	qce->mem_path = of_icc_get(qce->dev, "memory");
> -	if (IS_ERR(qce->mem_path))
> +	if (IS_ERR(qce->mem_path)) {
> +		qce_dma_release(&qce->dma);
>   		return PTR_ERR(qce->mem_path);
> +	}
>   
>   	qce->core = devm_clk_get_optional(qce->dev, "core");
>   	if (IS_ERR(qce->core)) {
> @@ -247,10 +257,6 @@ static int qce_crypto_probe(struct platform_device *pdev)
>   	if (ret)
>   		goto err_clks_iface;
>   
> -	ret = qce_dma_request(qce->dev, &qce->dma);
> -	if (ret)
> -		goto err_clks;
> -
>   	ret = qce_check_version(qce);
>   	if (ret)
>   		goto err_clks;
> @@ -265,12 +271,10 @@ static int qce_crypto_probe(struct platform_device *pdev)
>   
>   	ret = qce_register_algs(qce);
>   	if (ret)
> -		goto err_dma;
> +		goto err_clks;
>   
>   	return 0;
>   
> -err_dma:
> -	qce_dma_release(&qce->dma);
>   err_clks:
>   	clk_disable_unprepare(qce->bus);
>   err_clks_iface:
> 

--
Best wishes,
Vladimir

^ permalink raw reply	[flat|nested] 52+ messages in thread

* Re: [PATCH v4 05/20] dt-bindings: qcom-bam: Add 'interconnects' & 'interconnect-names' to optional properties
  2021-10-13 18:39   ` Rob Herring
@ 2021-10-14  7:03     ` Bhupesh Sharma
  2021-10-24 13:55       ` Bhupesh Sharma
  0 siblings, 1 reply; 52+ messages in thread
From: Bhupesh Sharma @ 2021-10-14  7:03 UTC (permalink / raw)
  To: Rob Herring
  Cc: Herbert Xu, devicetree, Rob Herring, Thara Gopinath,
	bhupesh.linux, Andy Gross, MSM, linux-crypto, David S . Miller,
	Bjorn Andersson, Linux Kernel Mailing List

Hello Rob,

Thanks for your review.
These issues are already fixed via patches within this series itself
(as some dts also need correction to pass the 'make dtbs_check'
check). I am not sure, but it seems the check was run without applying
other patches from this series.

See details below:

On Thu, 14 Oct 2021 at 00:09, Rob Herring <robh@kernel.org> wrote:
>
> On Wed, 13 Oct 2021 16:25:26 +0530, Bhupesh Sharma wrote:
> > Add new optional properties - 'interconnects' and
> > 'interconnect-names' to the device-tree binding documentation for
> > qcom-bam DMA IP.
> >
> > These properties describe the interconnect path between bam and main
> > memory and the interconnect type respectively.
> >
> > Cc: Thara Gopinath <thara.gopinath@linaro.org>
> > Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> > Cc: Rob Herring <robh+dt@kernel.org>
> > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
> > ---
> >  Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml | 8 ++++++++
> >  1 file changed, 8 insertions(+)
> >
>
> Running 'make dtbs_check' with the schema in this patch gives the
> following warnings. Consider if they are expected or the schema is
> incorrect. These may not be new warnings.
>
> Note that it is not yet a requirement to have 0 warnings for dtbs_check.
> This will change in the future.
>
> Full log is available here: https://patchwork.ozlabs.org/patch/1540390
>
>
> dma@12142000: $nodename:0: 'dma@12142000' does not match '^dma-controller(@.*)?$'
>         arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dt.yaml
>
> dma@12182000: $nodename:0: 'dma@12182000' does not match '^dma-controller(@.*)?$'
>         arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dt.yaml
>         arch/arm/boot/dts/qcom-apq8064-cm-qs600.dt.yaml
>         arch/arm/boot/dts/qcom-apq8064-ifc6410.dt.yaml
>         arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dt.yaml
>         arch/arm/boot/dts/qcom-ipq8064-ap148.dt.yaml
>         arch/arm/boot/dts/qcom-ipq8064-rb3011.dt.yaml
>         arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dt.yaml
>
> dma@121c2000: $nodename:0: 'dma@121c2000' does not match '^dma-controller(@.*)?$'
>         arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dt.yaml
>         arch/arm/boot/dts/qcom-apq8064-cm-qs600.dt.yaml
>         arch/arm/boot/dts/qcom-apq8064-ifc6410.dt.yaml
>         arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dt.yaml
>
> dma@12402000: $nodename:0: 'dma@12402000' does not match '^dma-controller(@.*)?$'
>         arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dt.yaml
>         arch/arm/boot/dts/qcom-apq8064-cm-qs600.dt.yaml
>         arch/arm/boot/dts/qcom-apq8064-ifc6410.dt.yaml
>         arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dt.yaml
>         arch/arm/boot/dts/qcom-ipq8064-ap148.dt.yaml
>         arch/arm/boot/dts/qcom-ipq8064-rb3011.dt.yaml
>
> dma@1dc4000: $nodename:0: 'dma@1dc4000' does not match '^dma-controller(@.*)?$'
>         arch/arm64/boot/dts/qcom/sdm845-cheza-r1.dt.yaml
>         arch/arm64/boot/dts/qcom/sdm845-cheza-r2.dt.yaml
>         arch/arm64/boot/dts/qcom/sdm845-cheza-r3.dt.yaml
>         arch/arm64/boot/dts/qcom/sdm845-db845c.dt.yaml
>         arch/arm64/boot/dts/qcom/sdm845-mtp.dt.yaml
>         arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dt.yaml
>         arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dt.yaml
>         arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dt.yaml
>         arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dt.yaml

All the above will be fixed by '[PATCH 01/20] arm64/dts: qcom: Fix 'dma' &
 'qcom,controlled-remotely' nodes in dts' in this series. See the git
log of the this patch for details:

'A few qcom device-tree files define dma-controller nodes
with non-standard 'node names' and also set
the bool property 'qcom,controlled-remotely' incorrectly, which
leads to following errors with 'make dtbs_check':

 $ arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dt.yaml:
     dma@1dc4000: $nodename:0: 'dma@1dc4000' does not match
     '^dma-controller(@.*)?$'

 $ arch/arm64/boot/dts/qcom/sm8250-mtp.dt.yaml:
     dma@1dc4000: qcom,controlled-remotely: 'oneOf' conditional
     failed, one must be fixed:
    [[1]] is not of type 'boolean'
    True was expected
    [[1]] is not of type 'null'

Fix the same.
'

> dma@1dc4000: 'iommus' does not match any of the regexes: 'pinctrl-[0-9]+'
>         arch/arm64/boot/dts/qcom/sdm845-cheza-r1.dt.yaml
>         arch/arm64/boot/dts/qcom/sdm845-cheza-r2.dt.yaml
>         arch/arm64/boot/dts/qcom/sdm845-cheza-r3.dt.yaml
>         arch/arm64/boot/dts/qcom/sdm845-db845c.dt.yaml
>         arch/arm64/boot/dts/qcom/sdm845-mtp.dt.yaml
>         arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dt.yaml
>         arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dt.yaml
>         arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dt.yaml
>         arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dt.yaml

Fixed by ' [PATCH 06/20] dt-bindings: qcom-bam: Add 'iommus' to optional
 properties ' in this series.

> dma@1dc4000: qcom,controlled-remotely: 'oneOf' conditional failed, one must be fixed:
>         arch/arm64/boot/dts/qcom/sdm845-cheza-r1.dt.yaml
>         arch/arm64/boot/dts/qcom/sdm845-cheza-r2.dt.yaml
>         arch/arm64/boot/dts/qcom/sdm845-cheza-r3.dt.yaml
>         arch/arm64/boot/dts/qcom/sdm845-db845c.dt.yaml
>         arch/arm64/boot/dts/qcom/sdm845-mtp.dt.yaml
>         arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dt.yaml
>         arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dt.yaml
>         arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dt.yaml
>         arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dt.yaml

Again this would be fixed by '[PATCH 01/20] arm64/dts: qcom: Fix 'dma' &
 'qcom,controlled-remotely' nodes in dts' in this series.

> dma@704000: $nodename:0: 'dma@704000' does not match '^dma-controller(@.*)?$'
>         arch/arm64/boot/dts/qcom/ipq8074-hk01.dt.yaml
>         arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dt.yaml
>         arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dt.yaml

Fixed by '[PATCH 01/20] arm64/dts: qcom: Fix 'dma' &
'qcom,controlled-remotely' nodes in dts' in this series

> dma@704000: qcom,controlled-remotely: 'oneOf' conditional failed, one must be fixed:
>         arch/arm64/boot/dts/qcom/ipq8074-hk01.dt.yaml
>         arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dt.yaml
>         arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dt.yaml

Fixed by '[PATCH 01/20] arm64/dts: qcom: Fix 'dma' &
'qcom,controlled-remotely' nodes in dts' in this series

> dma@7544000: $nodename:0: 'dma@7544000' does not match '^dma-controller(@.*)?$'
>         arch/arm64/boot/dts/qcom/apq8096-db820c.dt.yaml
>         arch/arm64/boot/dts/qcom/apq8096-ifc6640.dt.yaml
>         arch/arm64/boot/dts/qcom/msm8996-mtp.dt.yaml
>         arch/arm64/boot/dts/qcom/msm8996-pmi8996-sony-xperia-tone-dora.dt.yaml
>         arch/arm64/boot/dts/qcom/msm8996-pmi8996-sony-xperia-tone-kagura.dt.yaml
>         arch/arm64/boot/dts/qcom/msm8996-pmi8996-sony-xperia-tone-keyaki.dt.yaml
>         arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone-dora.dt.yaml
>         arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone-kagura.dt.yaml
>         arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone-keyaki.dt.yaml
>
> dma@7584000: $nodename:0: 'dma@7584000' does not match '^dma-controller(@.*)?$'
>         arch/arm64/boot/dts/qcom/apq8096-db820c.dt.yaml
>         arch/arm64/boot/dts/qcom/apq8096-ifc6640.dt.yaml
>         arch/arm64/boot/dts/qcom/msm8996-mtp.dt.yaml
>         arch/arm64/boot/dts/qcom/msm8996-pmi8996-sony-xperia-tone-dora.dt.yaml
>         arch/arm64/boot/dts/qcom/msm8996-pmi8996-sony-xperia-tone-kagura.dt.yaml
>         arch/arm64/boot/dts/qcom/msm8996-pmi8996-sony-xperia-tone-keyaki.dt.yaml
>         arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone-dora.dt.yaml
>         arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone-kagura.dt.yaml
>         arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone-keyaki.dt.yaml
>
> dma@7884000: $nodename:0: 'dma@7884000' does not match '^dma-controller(@.*)?$'
>         arch/arm/boot/dts/qcom-ipq4018-ap120c-ac-bit.dt.yaml
>         arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dt.yaml
>         arch/arm/boot/dts/qcom-ipq4018-jalapeno.dt.yaml
>         arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dt.yaml
>         arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dt.yaml
>         arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dt.yaml
>         arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dt.yaml
>         arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dt.yaml
>
> dma@7984000: $nodename:0: 'dma@7984000' does not match '^dma-controller(@.*)?$'
>         arch/arm/boot/dts/qcom-ipq4018-ap120c-ac-bit.dt.yaml
>         arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dt.yaml
>         arch/arm/boot/dts/qcom-ipq4018-jalapeno.dt.yaml
>         arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dt.yaml
>         arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dt.yaml
>         arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dt.yaml
>         arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dt.yaml
>         arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dt.yaml
>
> dma@8e04000: $nodename:0: 'dma@8e04000' does not match '^dma-controller(@.*)?$'
>         arch/arm/boot/dts/qcom-ipq4018-ap120c-ac-bit.dt.yaml
>         arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dt.yaml
>         arch/arm/boot/dts/qcom-ipq4018-jalapeno.dt.yaml
>         arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dt.yaml
>         arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dt.yaml
>         arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dt.yaml
>         arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dt.yaml
>         arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dt.yaml
>
> dma@c184000: $nodename:0: 'dma@c184000' does not match '^dma-controller(@.*)?$'
>         arch/arm64/boot/dts/qcom/msm8998-asus-novago-tp370ql.dt.yaml
>         arch/arm64/boot/dts/qcom/msm8998-hp-envy-x2.dt.yaml
>         arch/arm64/boot/dts/qcom/msm8998-lenovo-miix-630.dt.yaml
>         arch/arm64/boot/dts/qcom/msm8998-mtp.dt.yaml
>         arch/arm64/boot/dts/qcom/msm8998-oneplus-cheeseburger.dt.yaml
>         arch/arm64/boot/dts/qcom/msm8998-oneplus-dumpling.dt.yaml

All the above 6 issues are fixed by '[PATCH 01/20] arm64/dts: qcom: Fix 'dma' &
 'qcom,controlled-remotely' nodes in dts' in this series.

> dma-controller@17184000: 'iommus' does not match any of the regexes: 'pinctrl-[0-9]+'
>         arch/arm64/boot/dts/qcom/sdm845-cheza-r1.dt.yaml
>         arch/arm64/boot/dts/qcom/sdm845-cheza-r2.dt.yaml
>         arch/arm64/boot/dts/qcom/sdm845-cheza-r3.dt.yaml
>         arch/arm64/boot/dts/qcom/sdm845-db845c.dt.yaml
>         arch/arm64/boot/dts/qcom/sdm845-mtp.dt.yaml
>         arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dt.yaml
>         arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dt.yaml
>         arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dt.yaml
>         arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dt.yaml

Fixed by ' [PATCH 06/20] dt-bindings: qcom-bam: Add 'iommus' to optional
 properties ' in this series.

> dma-controller@704000: 'qcom,config-pipe-trust-reg' does not match any of the regexes: 'pinctrl-[0-9]+'
>         arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dt.yaml

Fixed by '[PATCH 02/20] arm64/dts: qcom: ipq6018: Remove unused
 'qcom,config-pipe-trust-reg' property' in this series.

> dma-controller@704000: qcom,controlled-remotely: 'oneOf' conditional failed, one must be fixed:
>         arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dt.yaml

Fixed by '[PATCH 01/20] arm64/dts: qcom: Fix 'dma' &
''qcom,controlled-remotely' nodes in dts' in this series.

> dma-controller@7984000: clock-names:0: 'bam_clk' was expected
>         arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dt.yaml
>
> dma-controller@7984000: clock-names: Additional items are not allowed ('bam_clk' was unexpected)
>         arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dt.yaml
>
> dma-controller@7984000: clock-names: ['iface_clk', 'bam_clk'] is too long
>         arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dt.yaml
>
> dma-controller@7984000: clocks: [[9, 138], [9, 137]] is too long
>         arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dt.yaml

Fixed by '[PATCH 03/20] arm64/dts: qcom: ipq6018: Remove unused 'iface_clk'
property from dma-controller node' in this series.

In summary, I ran 'make dtbs_check' after applying this series on
linus's tip and linux-next's tip as well and saw no errors being
reported for 'Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml'.

Regards,
Bhupesh

^ permalink raw reply	[flat|nested] 52+ messages in thread

* Re: [PATCH v4 18/20] crypto: qce: Defer probing if BAM dma channel is not yet initialized
  2021-10-13 20:49   ` Vladimir Zapolskiy
@ 2021-10-14  7:40     ` Bhupesh Sharma
  2021-10-14  8:42       ` Vladimir Zapolskiy
  0 siblings, 1 reply; 52+ messages in thread
From: Bhupesh Sharma @ 2021-10-14  7:40 UTC (permalink / raw)
  To: Vladimir Zapolskiy
  Cc: MSM, linux-crypto, bhupesh.linux, Linux Kernel Mailing List,
	devicetree, Rob Herring, Andy Gross, Herbert Xu,
	David S . Miller, Thara Gopinath, Bjorn Andersson

Hi Vladimir,

On Thu, 14 Oct 2021 at 02:19, Vladimir Zapolskiy
<vladimir.zapolskiy@linaro.org> wrote:
>
> Hi Bhupesh,
>
> On 10/13/21 1:55 PM, Bhupesh Sharma wrote:
> > Since the Qualcomm qce crypto driver needs the BAM dma driver to be
> > setup first (to allow crypto operations), it makes sense to defer
> > the qce crypto driver probing in case the BAM dma driver is not yet
> > probed.
> >
> > Move the code leg requesting dma channels earlier in the
> > probe() flow. This fixes the qce probe failure issues when both qce
> > and BMA dma are compiled as static part of the kernel.
> >
> > Cc: Thara Gopinath <thara.gopinath@linaro.org>
> > Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
> > ---
> >   drivers/crypto/qce/core.c | 20 ++++++++++++--------
> >   1 file changed, 12 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c
> > index cb8c77709e1e..c6f686126fc9 100644
> > --- a/drivers/crypto/qce/core.c
> > +++ b/drivers/crypto/qce/core.c
> > @@ -209,9 +209,19 @@ static int qce_crypto_probe(struct platform_device *pdev)
> >       if (ret < 0)
> >               return ret;
> >
> > +     /* qce driver requires BAM dma driver to be setup first.
>
> I believe a multi-line block of comments should be started with '/*' line,
> for reference please take a look at Documentation/process/coding-style.rst

There are exceptions to this rule as well. For e.g. see most of the
networking drivers and the multi-line comment styles there :) .

There is a very interesting LWN article on the same :
https://lwn.net/Articles/694755/
Note that 'crypto/' and 'drivers/crypto' use these non-standard
multi-line comments quite often as well.

That said, I have no strong opinion on using either style. Although, I
found one of the points raised by the networking maintainer during one
of my patch reviews earlier quite useful - 'keeping the top line in a
multi-line comment blank, wastes precious screen space while reading
and reviewing the patch'.

Regards,
Bhupesh

> > +      * In case the dma channel are not set yet, this check
> > +      * helps use to return -EPROBE_DEFER earlier.
> > +      */
> > +     ret = qce_dma_request(qce->dev, &qce->dma);
> > +     if (ret)
> > +             return ret;
> > +
> >       qce->mem_path = of_icc_get(qce->dev, "memory");
> > -     if (IS_ERR(qce->mem_path))
> > +     if (IS_ERR(qce->mem_path)) {
> > +             qce_dma_release(&qce->dma);
> >               return PTR_ERR(qce->mem_path);
> > +     }
> >
> >       qce->core = devm_clk_get_optional(qce->dev, "core");
> >       if (IS_ERR(qce->core)) {
> > @@ -247,10 +257,6 @@ static int qce_crypto_probe(struct platform_device *pdev)
> >       if (ret)
> >               goto err_clks_iface;
> >
> > -     ret = qce_dma_request(qce->dev, &qce->dma);
> > -     if (ret)
> > -             goto err_clks;
> > -
> >       ret = qce_check_version(qce);
> >       if (ret)
> >               goto err_clks;
> > @@ -265,12 +271,10 @@ static int qce_crypto_probe(struct platform_device *pdev)
> >
> >       ret = qce_register_algs(qce);
> >       if (ret)
> > -             goto err_dma;
> > +             goto err_clks;
> >
> >       return 0;
> >
> > -err_dma:
> > -     qce_dma_release(&qce->dma);
> >   err_clks:
> >       clk_disable_unprepare(qce->bus);
> >   err_clks_iface:
> >
>
> --
> Best wishes,
> Vladimir

^ permalink raw reply	[flat|nested] 52+ messages in thread

* Re: [PATCH v4 18/20] crypto: qce: Defer probing if BAM dma channel is not yet initialized
  2021-10-14  7:40     ` Bhupesh Sharma
@ 2021-10-14  8:42       ` Vladimir Zapolskiy
  0 siblings, 0 replies; 52+ messages in thread
From: Vladimir Zapolskiy @ 2021-10-14  8:42 UTC (permalink / raw)
  To: Bhupesh Sharma
  Cc: MSM, linux-crypto, bhupesh.linux, Linux Kernel Mailing List,
	devicetree, Rob Herring, Andy Gross, Herbert Xu,
	David S . Miller, Thara Gopinath, Bjorn Andersson

Hi Bhupesh,

On 10/14/21 10:40 AM, Bhupesh Sharma wrote:
> Hi Vladimir,
> 
> On Thu, 14 Oct 2021 at 02:19, Vladimir Zapolskiy
> <vladimir.zapolskiy@linaro.org> wrote:
>>
>> Hi Bhupesh,
>>
>> On 10/13/21 1:55 PM, Bhupesh Sharma wrote:
>>> Since the Qualcomm qce crypto driver needs the BAM dma driver to be
>>> setup first (to allow crypto operations), it makes sense to defer
>>> the qce crypto driver probing in case the BAM dma driver is not yet
>>> probed.
>>>
>>> Move the code leg requesting dma channels earlier in the
>>> probe() flow. This fixes the qce probe failure issues when both qce
>>> and BMA dma are compiled as static part of the kernel.
>>>
>>> Cc: Thara Gopinath <thara.gopinath@linaro.org>
>>> Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
>>> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
>>> ---
>>>    drivers/crypto/qce/core.c | 20 ++++++++++++--------
>>>    1 file changed, 12 insertions(+), 8 deletions(-)
>>>
>>> diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c
>>> index cb8c77709e1e..c6f686126fc9 100644
>>> --- a/drivers/crypto/qce/core.c
>>> +++ b/drivers/crypto/qce/core.c
>>> @@ -209,9 +209,19 @@ static int qce_crypto_probe(struct platform_device *pdev)
>>>        if (ret < 0)
>>>                return ret;
>>>
>>> +     /* qce driver requires BAM dma driver to be setup first.
>>
>> I believe a multi-line block of comments should be started with '/*' line,
>> for reference please take a look at Documentation/process/coding-style.rst
> 
> There are exceptions to this rule as well. For e.g. see most of the
> networking drivers and the multi-line comment styles there :) .
> 
> There is a very interesting LWN article on the same :
> https://lwn.net/Articles/694755/
> Note that 'crypto/' and 'drivers/crypto' use these non-standard
> multi-line comments quite often as well.

Ah, yes, I agree here, thank you for the reminder! IIRC crypto drivers
kind of belong to netdev domain, at least in relation to the accepted
coding style.

> That said, I have no strong opinion on using either style. Although, I
> found one of the points raised by the networking maintainer during one
> of my patch reviews earlier quite useful - 'keeping the top line in a
> multi-line comment blank, wastes precious screen space while reading
> and reviewing the patch'.

--
Best wishes,
Vladimir

^ permalink raw reply	[flat|nested] 52+ messages in thread

* Re: [PATCH v4 11/20] dt-bindings: crypto : Add new compatible strings for qcom-qce
  2021-10-13 10:55 ` [PATCH v4 11/20] dt-bindings: crypto : Add new compatible strings for qcom-qce Bhupesh Sharma
@ 2021-10-18 18:26   ` Rob Herring
  0 siblings, 0 replies; 52+ messages in thread
From: Rob Herring @ 2021-10-18 18:26 UTC (permalink / raw)
  To: Bhupesh Sharma
  Cc: herbert, linux-crypto, davem, agross, devicetree, linux-arm-msm,
	linux-kernel, Thara Gopinath, Bjorn Andersson, robh+dt,
	bhupesh.linux

On Wed, 13 Oct 2021 16:25:32 +0530, Bhupesh Sharma wrote:
> Newer qcom chips support newer versions of the qce crypto IP, so add
> soc specific compatible strings for qcom-qce instead of using crypto
> IP version specific ones.
> 
> Keep the old strings for backward-compatibility, but mark them as
> deprecated.
> 
> Cc: Thara Gopinath <thara.gopinath@linaro.org>
> Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
> ---
>  Documentation/devicetree/bindings/crypto/qcom-qce.yaml | 10 ++++++++--
>  1 file changed, 8 insertions(+), 2 deletions(-)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 52+ messages in thread

* Re: [PATCH v4 00/20] Enable Qualcomm Crypto Engine on sm8250
  2021-10-13 10:55 [PATCH v4 00/20] Enable Qualcomm Crypto Engine on sm8250 Bhupesh Sharma
                   ` (19 preceding siblings ...)
  2021-10-13 10:55 ` [PATCH v4 20/20] arm64/dts: qcom: sm8250: Add dt entries to support crypto engine Bhupesh Sharma
@ 2021-10-20 14:03 ` Thara Gopinath
  2021-10-24 13:58   ` Bhupesh Sharma
  20 siblings, 1 reply; 52+ messages in thread
From: Thara Gopinath @ 2021-10-20 14:03 UTC (permalink / raw)
  To: Bhupesh Sharma, linux-arm-msm, linux-crypto
  Cc: bhupesh.linux, linux-kernel, devicetree, robh+dt, agross,
	herbert, davem, Bjorn Andersson



On 10/13/21 6:55 AM, Bhupesh Sharma wrote:
> Sorry for a delayed v4, but I have been caught up with some other
> patches.

Hi Bhupesh,

If possible, please consider splitting this series into 2. One with 
changes required to support crypto driver on
sm8250 and other with the generic fixes / fixing the dt-bindings et all.
It would be easier to review as well

-- 
Warm Regards
Thara (She/Her/Hers)

> 
> Changes since v3:
> =================
> - v3 can be seen here: https://lore.kernel.org/linux-arm-msm/20210519143700.27392-1-bhupesh.sharma@linaro.org/
> - Dropped a couple of patches from v3, on basis of the review comments:
>     ~ [PATCH 13/17] crypto: qce: core: Make clocks optional
>     ~ [PATCH 15/17] crypto: qce: Convert the device found dev_dbg() to dev_info()
> - Addressed review comments from Thara, Rob and Stephan Gerhold.
> - Collect Reviewed-by from Rob and Thara on some of the patches from the
>    v3 patchset.
> 
> Changes since v2:
> =================
> - v2 can be seen here: https://lore.kernel.org/dmaengine/20210505213731.538612-1-bhupesh.sharma@linaro.org/
> - Drop a couple of patches from v1, which tried to address the defered
>    probing of qce driver in case bam dma driver is not yet probed.
>    Replace it instead with a single (simpler) patch [PATCH 16/17].
> - Convert bam dma and qce crypto dt-bindings to YAML.
> - Addressed review comments from Thara, Bjorn, Vinod and Rob.
> 
> Changes since v1:
> =================
> - v1 can be seen here: https://lore.kernel.org/linux-arm-msm/20210310052503.3618486-1-bhupesh.sharma@linaro.org/
> - v1 did not work well as reported earlier by Dmitry, so v2 contains the following
>    changes/fixes:
>    ~ Enable the interconnect path b/w BAM DMA and main memory first
>      before trying to access the BAM DMA registers.
>    ~ Enable the interconnect path b/w qce crytpo and main memory first
>      before trying to access the qce crypto registers.
>    ~ Make sure to document the required and optional properties for both
>      BAM DMA and qce crypto drivers.
>    ~ Add a few debug related print messages in case the qce crypto driver
>      passes or fails to probe.
>    ~ Convert the qce crypto driver probe to a defered one in case the BAM DMA
>      or the interconnect driver(s) (needed on specific Qualcomm parts) are not
>      yet probed.
> 
> Qualcomm crypto engine is also available on sm8250 SoC.
> It supports hardware accelerated algorithms for encryption
> and authentication. It also provides support for aes, des, 3des
> encryption algorithms and sha1, sha256, hmac(sha1), hmac(sha256)
> authentication algorithms.
> 
> Tested the enabled crypto algorithms with cryptsetup test utilities
> on sm8250-mtp and RB5 board (see [1]) and also with crypto self-tests,
> including the fuzz tests (CONFIG_CRYPTO_MANAGER_EXTRA_TESTS=y).
> 
> Note that this series is rebased on a SMMU related fix from Arnd applied
> on either linus's tip of linux-next's tip (see [2]), without which
> the sm8250 based boards fail to boot with the latest tip.
> 
> [1]. https://linux.die.net/man/8/cryptsetup
> [2]. https://lore.kernel.org/linux-arm-kernel/CAA8EJpoD4Th1tdwYQLnZur2oA0xX0LojSrNFLyJqdi6+rnB3YQ@mail.gmail.com/T/
> 
> Cc: Thara Gopinath <thara.gopinath@linaro.org>
> Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> 
> Bhupesh Sharma (17):
>    arm64/dts: qcom: Fix 'dma' & 'qcom,controlled-remotely' nodes in dts
>    arm64/dts: qcom: ipq6018: Remove unused 'qcom,config-pipe-trust-reg'
>      property
>    arm64/dts: qcom: ipq6018: Remove unused 'iface_clk' property from
>      dma-controller node
>    dt-bindings: qcom-bam: Convert binding to YAML
>    dt-bindings: qcom-bam: Add 'interconnects' & 'interconnect-names' to
>      optional properties
>    dt-bindings: qcom-bam: Add 'iommus' to optional properties
>    dt-bindings: qcom-qce: Convert bindings to yaml
>    dt-bindings: qcom-qce: Add 'interconnects' and move 'clocks' to
>      optional properties
>    dt-bindings: qcom-qce: Add 'iommus' to optional properties
>    arm64/dts: qcom: sdm845: Use RPMH_CE_CLK macro directly
>    dt-bindings: crypto : Add new compatible strings for qcom-qce
>    arm64/dts: qcom: Use new compatibles for crypto nodes
>    crypto: qce: Add new compatibles for qce crypto driver
>    crypto: qce: Print a failure msg in case probe() fails
>    crypto: qce: Defer probing if BAM dma channel is not yet initialized
>    crypto: qce: Add 'sm8250-qce' compatible string check
>    arm64/dts: qcom: sm8250: Add dt entries to support crypto engine.
> 
> Thara Gopinath (3):
>    dma: qcom: bam_dma: Add support to initialize interconnect path
>    crypto: qce: core: Add support to initialize interconnect path
>    crypto: qce: core: Make clocks optional
> 
>   .../devicetree/bindings/crypto/qcom-qce.yaml  |  90 +++++++++++++++
>   .../devicetree/bindings/dma/qcom_bam_dma.txt  |  50 --------
>   .../devicetree/bindings/dma/qcom_bam_dma.yaml | 107 ++++++++++++++++++
>   arch/arm64/boot/dts/qcom/ipq6018.dtsi         |  10 +-
>   arch/arm64/boot/dts/qcom/ipq8074.dtsi         |   4 +-
>   arch/arm64/boot/dts/qcom/msm8996.dtsi         |   4 +-
>   arch/arm64/boot/dts/qcom/msm8998.dtsi         |   2 +-
>   arch/arm64/boot/dts/qcom/sdm845.dtsi          |  10 +-
>   arch/arm64/boot/dts/qcom/sm8250.dtsi          |  28 +++++
>   drivers/crypto/qce/core.c                     |  66 +++++++----
>   drivers/crypto/qce/core.h                     |   1 +
>   drivers/dma/qcom/bam_dma.c                    |  16 ++-
>   12 files changed, 302 insertions(+), 86 deletions(-)
>   create mode 100644 Documentation/devicetree/bindings/crypto/qcom-qce.yaml
>   delete mode 100644 Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
>   create mode 100644 Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml
> 



^ permalink raw reply	[flat|nested] 52+ messages in thread

* Re: [PATCH v4 15/20] crypto: qce: Add new compatibles for qce crypto driver
  2021-10-13 10:55 ` [PATCH v4 15/20] crypto: qce: Add new compatibles for qce crypto driver Bhupesh Sharma
  2021-10-13 19:22   ` Vladimir Zapolskiy
@ 2021-10-20 14:07   ` Thara Gopinath
  2021-10-24 13:52     ` Bhupesh Sharma
  1 sibling, 1 reply; 52+ messages in thread
From: Thara Gopinath @ 2021-10-20 14:07 UTC (permalink / raw)
  To: Bhupesh Sharma, linux-arm-msm, linux-crypto
  Cc: bhupesh.linux, linux-kernel, devicetree, robh+dt, agross,
	herbert, davem, Bjorn Andersson



On 10/13/21 6:55 AM, Bhupesh Sharma wrote:
> Since we decided to use soc specific compatibles for describing
> the qce crypto IP nodes in the device-trees, adapt the driver
> now to handle the same.
> 
> Cc: Thara Gopinath <thara.gopinath@linaro.org>
> Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
> ---
>   drivers/crypto/qce/core.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c
> index 033c7278aa5d..2ab0b97d718c 100644
> --- a/drivers/crypto/qce/core.c
> +++ b/drivers/crypto/qce/core.c
> @@ -298,8 +298,8 @@ static int qce_crypto_remove(struct platform_device *pdev)
>   }
>   
>   static const struct of_device_id qce_crypto_of_match[] = {
> -	{ .compatible = "qcom,crypto-v5.1", },
Hi Bhupesh,

I think we should keep the qcom,crypto-v5.1 here for backward 
compatibility. Since v5.4 was added only recently it might be okay to 
remove it.

-- 
Warm Regards
Thara (She/Her/Hers)


> -	{ .compatible = "qcom,crypto-v5.4", },
> +	{ .compatible = "qcom,ipq6018-qce", },
> +	{ .compatible = "qcom,sdm845-qce", },
>   	{}
>   };
>   MODULE_DEVICE_TABLE(of, qce_crypto_of_match);
> 



^ permalink raw reply	[flat|nested] 52+ messages in thread

* Re: [PATCH v4 18/20] crypto: qce: Defer probing if BAM dma channel is not yet initialized
  2021-10-13 10:55 ` [PATCH v4 18/20] crypto: qce: Defer probing if BAM dma channel is not yet initialized Bhupesh Sharma
  2021-10-13 20:49   ` Vladimir Zapolskiy
@ 2021-10-20 14:10   ` Thara Gopinath
  2021-10-24 14:05     ` Bhupesh Sharma
  1 sibling, 1 reply; 52+ messages in thread
From: Thara Gopinath @ 2021-10-20 14:10 UTC (permalink / raw)
  To: Bhupesh Sharma, linux-arm-msm, linux-crypto
  Cc: bhupesh.linux, linux-kernel, devicetree, robh+dt, agross,
	herbert, davem, Bjorn Andersson



On 10/13/21 6:55 AM, Bhupesh Sharma wrote:
> Since the Qualcomm qce crypto driver needs the BAM dma driver to be
> setup first (to allow crypto operations), it makes sense to defer
> the qce crypto driver probing in case the BAM dma driver is not yet
> probed.
> 
> Move the code leg requesting dma channels earlier in the
> probe() flow. This fixes the qce probe failure issues when both qce
> and BMA dma are compiled as static part of the kernel.

Hi Bhupesh,

I am quite curious to know the nature of probe failure you are seeing 
with the current sequence.  I am not against changing the sequence but 
for me when a driver is enabled, it is clocks first, interconnect next 
and then dma. Also I have tested the current sequence on sm8150 with 
both the modules built in as static and I have not seen the failure.

-- 
Warm Regards
Thara (She/Her/Hers)
> 
> Cc: Thara Gopinath <thara.gopinath@linaro.org>
> Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
> ---
>   drivers/crypto/qce/core.c | 20 ++++++++++++--------
>   1 file changed, 12 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c
> index cb8c77709e1e..c6f686126fc9 100644
> --- a/drivers/crypto/qce/core.c
> +++ b/drivers/crypto/qce/core.c
> @@ -209,9 +209,19 @@ static int qce_crypto_probe(struct platform_device *pdev)
>   	if (ret < 0)
>   		return ret;
>   
> +	/* qce driver requires BAM dma driver to be setup first.
> +	 * In case the dma channel are not set yet, this check
> +	 * helps use to return -EPROBE_DEFER earlier.
> +	 */
> +	ret = qce_dma_request(qce->dev, &qce->dma);
> +	if (ret)
> +		return ret;
> +
>   	qce->mem_path = of_icc_get(qce->dev, "memory");
> -	if (IS_ERR(qce->mem_path))
> +	if (IS_ERR(qce->mem_path)) {
> +		qce_dma_release(&qce->dma);
>   		return PTR_ERR(qce->mem_path);
> +	}
>   
>   	qce->core = devm_clk_get_optional(qce->dev, "core");
>   	if (IS_ERR(qce->core)) {
> @@ -247,10 +257,6 @@ static int qce_crypto_probe(struct platform_device *pdev)
>   	if (ret)
>   		goto err_clks_iface;
>   
> -	ret = qce_dma_request(qce->dev, &qce->dma);
> -	if (ret)
> -		goto err_clks;
> -
>   	ret = qce_check_version(qce);
>   	if (ret)
>   		goto err_clks;
> @@ -265,12 +271,10 @@ static int qce_crypto_probe(struct platform_device *pdev)
>   
>   	ret = qce_register_algs(qce);
>   	if (ret)
> -		goto err_dma;
> +		goto err_clks;
>   
>   	return 0;
>   
> -err_dma:
> -	qce_dma_release(&qce->dma);
>   err_clks:
>   	clk_disable_unprepare(qce->bus);
>   err_clks_iface:
> 



^ permalink raw reply	[flat|nested] 52+ messages in thread

* Re: [PATCH v4 19/20] crypto: qce: Add 'sm8250-qce' compatible string check
  2021-10-13 10:55 ` [PATCH v4 19/20] crypto: qce: Add 'sm8250-qce' compatible string check Bhupesh Sharma
@ 2021-10-20 14:11   ` Thara Gopinath
  0 siblings, 0 replies; 52+ messages in thread
From: Thara Gopinath @ 2021-10-20 14:11 UTC (permalink / raw)
  To: Bhupesh Sharma, linux-arm-msm, linux-crypto
  Cc: bhupesh.linux, linux-kernel, devicetree, robh+dt, agross,
	herbert, davem, Bjorn Andersson



On 10/13/21 6:55 AM, Bhupesh Sharma wrote:
> Add 'sm8250-qce' compatible string check in qce crypto
> driver as we add support for sm8250 crypto device in the
> device-tree in the subsequent patch.
> 
> Cc: Thara Gopinath <thara.gopinath@linaro.org>
> Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>

Reviewed-by: Thara Gopinath <thara.gopinath@linaro.org>

-- 
Warm Regards
Thara (She/Her/Hers)

> ---
>   drivers/crypto/qce/core.c | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c
> index c6f686126fc9..4c55eceb4e7f 100644
> --- a/drivers/crypto/qce/core.c
> +++ b/drivers/crypto/qce/core.c
> @@ -306,6 +306,7 @@ static int qce_crypto_remove(struct platform_device *pdev)
>   static const struct of_device_id qce_crypto_of_match[] = {
>   	{ .compatible = "qcom,ipq6018-qce", },
>   	{ .compatible = "qcom,sdm845-qce", },
> +	{ .compatible = "qcom,sm8250-qce", },
>   	{}
>   };
>   MODULE_DEVICE_TABLE(of, qce_crypto_of_match);
> 



^ permalink raw reply	[flat|nested] 52+ messages in thread

* Re: [PATCH v4 17/20] crypto: qce: Print a failure msg in case probe() fails
  2021-10-13 19:26   ` Vladimir Zapolskiy
@ 2021-10-24 13:33     ` Bhupesh Sharma
  0 siblings, 0 replies; 52+ messages in thread
From: Bhupesh Sharma @ 2021-10-24 13:33 UTC (permalink / raw)
  To: Vladimir Zapolskiy
  Cc: MSM, linux-crypto, bhupesh.linux, Linux Kernel Mailing List,
	devicetree, Rob Herring, Andy Gross, Herbert Xu,
	David S . Miller, Bjorn Andersson, Thara Gopinath

Hi Vladimir,

On Thu, 14 Oct 2021 at 00:56, Vladimir Zapolskiy
<vladimir.zapolskiy@linaro.org> wrote:
>
> Hi Bhupesh,
>
> On 10/13/21 1:55 PM, Bhupesh Sharma wrote:
> > Print a failure message (dev_err) in case the qcom qce crypto
> > driver probe() fails.
> >
> > Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> > Cc: Rob Herring <robh+dt@kernel.org>
> > Reviewed-by: Thara Gopinath <thara.gopinath@linaro.org>
> > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
> > ---
> >   drivers/crypto/qce/core.c | 2 ++
> >   1 file changed, 2 insertions(+)
> >
> > diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c
> > index 576c416461f9..cb8c77709e1e 100644
> > --- a/drivers/crypto/qce/core.c
> > +++ b/drivers/crypto/qce/core.c
> > @@ -281,6 +281,8 @@ static int qce_crypto_probe(struct platform_device *pdev)
> >       icc_set_bw(qce->mem_path, 0, 0);
> >   err_mem_path_put:
> >       icc_put(qce->mem_path);
> > +
> > +     dev_err(dev, "%s failed : %d\n", __func__, ret);
> >       return ret;
> >   }
> >
>
> As for me the rationale of this change is quite non-obvious, a user is well
> informed, if a driver probe fails. I would rather ask you to consider to
> drop this change.

Normally, when a driver probe fails, the kernel logging system does pretty
well to hold logs for the same and these can be referred to later for debugging.

However with crypto tests on arm machines, since the arm crypto interfaces are
also normally enabled by default, so boot-on crypto tests (enabled via
CRYPTO_MANAGER_EXTRA_TESTS), which normally take place at algorithm
registration,
it's sometimes difficult to check the qce driver probe errors /
failures, in case the board hangs or reboots while running the boot-on
crypto tests.

In such a case, if qce crypto driver probe fails, it is useful to see
a failure message on the serial console itself.

Regards,
Bhupesh

^ permalink raw reply	[flat|nested] 52+ messages in thread

* Re: [PATCH v4 16/20] crypto: qce: core: Make clocks optional
  2021-10-13 19:23   ` Vladimir Zapolskiy
@ 2021-10-24 13:34     ` Bhupesh Sharma
  0 siblings, 0 replies; 52+ messages in thread
From: Bhupesh Sharma @ 2021-10-24 13:34 UTC (permalink / raw)
  To: Vladimir Zapolskiy
  Cc: MSM, linux-crypto, bhupesh.linux, Linux Kernel Mailing List,
	devicetree, Rob Herring, Andy Gross, Herbert Xu,
	David S . Miller, Thara Gopinath

Hi Vladimir,

On Thu, 14 Oct 2021 at 00:53, Vladimir Zapolskiy
<vladimir.zapolskiy@linaro.org> wrote:
>
> Hi Bhupesh,
>
> On 10/13/21 1:55 PM, Bhupesh Sharma wrote:
> > From: Thara Gopinath <thara.gopinath@linaro.org>
> >
> > On certain Snapdragon processors, the crypto engine clocks are enabled by
> > default by security firmware and the driver need not/ should not handle the
> > clocks. Make acquiring of all the clocks optional in crypto enginer driver
>
> typo, s/enginer/engine/
>
> > so that the driver intializes properly even if no clocks are specified in
>
> typo, s/intializes/initializes/

Thanks, I will fix these typos in v5.

Regards,
Bhupesh

> > the dt.
> >
> > Signed-off-by: Thara Gopinath <thara.gopinath@linaro.org>
> > ---
> >   drivers/crypto/qce/core.c | 6 +++---
> >   1 file changed, 3 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c
> > index 2ab0b97d718c..576c416461f9 100644
> > --- a/drivers/crypto/qce/core.c
> > +++ b/drivers/crypto/qce/core.c
> > @@ -213,19 +213,19 @@ static int qce_crypto_probe(struct platform_device *pdev)
> >       if (IS_ERR(qce->mem_path))
> >               return PTR_ERR(qce->mem_path);
> >
> > -     qce->core = devm_clk_get(qce->dev, "core");
> > +     qce->core = devm_clk_get_optional(qce->dev, "core");
> >       if (IS_ERR(qce->core)) {
> >               ret = PTR_ERR(qce->core);
> >               goto err_mem_path_put;
> >       }
> >
> > -     qce->iface = devm_clk_get(qce->dev, "iface");
> > +     qce->iface = devm_clk_get_optional(qce->dev, "iface");
> >       if (IS_ERR(qce->iface)) {
> >               ret = PTR_ERR(qce->iface);
> >               goto err_mem_path_put;
> >       }
> >
> > -     qce->bus = devm_clk_get(qce->dev, "bus");
> > +     qce->bus = devm_clk_get_optional(qce->dev, "bus");
> >       if (IS_ERR(qce->bus)) {
> >               ret = PTR_ERR(qce->bus);
> >               goto err_mem_path_put;
> >
>
> --
> Best wishes,
> Vladimir

^ permalink raw reply	[flat|nested] 52+ messages in thread

* Re: [PATCH v4 15/20] crypto: qce: Add new compatibles for qce crypto driver
  2021-10-20 14:07   ` Thara Gopinath
@ 2021-10-24 13:52     ` Bhupesh Sharma
  0 siblings, 0 replies; 52+ messages in thread
From: Bhupesh Sharma @ 2021-10-24 13:52 UTC (permalink / raw)
  To: Thara Gopinath
  Cc: MSM, linux-crypto, bhupesh.linux, Linux Kernel Mailing List,
	devicetree, Rob Herring, Andy Gross, Herbert Xu,
	David S . Miller, Bjorn Andersson

Hi Thara and Vladimir,

On Wed, 20 Oct 2021 at 19:37, Thara Gopinath <thara.gopinath@linaro.org> wrote:
>
>
>
> On 10/13/21 6:55 AM, Bhupesh Sharma wrote:
> > Since we decided to use soc specific compatibles for describing
> > the qce crypto IP nodes in the device-trees, adapt the driver
> > now to handle the same.
> >
> > Cc: Thara Gopinath <thara.gopinath@linaro.org>
> > Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> > Cc: Rob Herring <robh+dt@kernel.org>
> > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
> > ---
> >   drivers/crypto/qce/core.c | 4 ++--
> >   1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c
> > index 033c7278aa5d..2ab0b97d718c 100644
> > --- a/drivers/crypto/qce/core.c
> > +++ b/drivers/crypto/qce/core.c
> > @@ -298,8 +298,8 @@ static int qce_crypto_remove(struct platform_device *pdev)
> >   }
> >
> >   static const struct of_device_id qce_crypto_of_match[] = {
> > -     { .compatible = "qcom,crypto-v5.1", },
> Hi Bhupesh,
>
> I think we should keep the qcom,crypto-v5.1 here for backward
> compatibility. Since v5.4 was added only recently it might be okay to
> remove it.

Thanks, I will fix this in the v5.

Regards,
Bhupesh

> > -     { .compatible = "qcom,crypto-v5.4", },
> > +     { .compatible = "qcom,ipq6018-qce", },
> > +     { .compatible = "qcom,sdm845-qce", },
> >       {}
> >   };
> >   MODULE_DEVICE_TABLE(of, qce_crypto_of_match);
> >
>
>

^ permalink raw reply	[flat|nested] 52+ messages in thread

* Re: [PATCH v4 14/20] crypto: qce: core: Add support to initialize interconnect path
  2021-10-13 19:19   ` Vladimir Zapolskiy
@ 2021-10-24 13:53     ` Bhupesh Sharma
  0 siblings, 0 replies; 52+ messages in thread
From: Bhupesh Sharma @ 2021-10-24 13:53 UTC (permalink / raw)
  To: Vladimir Zapolskiy
  Cc: MSM, linux-crypto, bhupesh.linux, Linux Kernel Mailing List,
	devicetree, Rob Herring, Andy Gross, Herbert Xu,
	David S . Miller, Thara Gopinath, Bjorn Andersson

Hi Vladimir,

On Thu, 14 Oct 2021 at 00:49, Vladimir Zapolskiy
<vladimir.zapolskiy@linaro.org> wrote:
>
> Hi Bhupesh,
>
> On 10/13/21 1:55 PM, Bhupesh Sharma wrote:
> > From: Thara Gopinath <thara.gopinath@linaro.org>
> >
> > Crypto engine on certain Snapdragon processors like sm8150, sm8250, sm8350
> > etc. requires interconnect path between the engine and memory to be
> > explicitly enabled and bandwidth set prior to any operations. Add support
> > in the qce core to enable the interconnect path appropriately.
> >
> > Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> > Cc: Rob Herring <robh+dt@kernel.org>
> > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
> > [Make header file inclusion alphabetical]
> > Signed-off-by: Thara Gopinath <thara.gopinath@linaro.org>
> > ---
> >   drivers/crypto/qce/core.c | 35 ++++++++++++++++++++++++++++-------
> >   drivers/crypto/qce/core.h |  1 +
> >   2 files changed, 29 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c
> > index d3780be44a76..033c7278aa5d 100644
> > --- a/drivers/crypto/qce/core.c
> > +++ b/drivers/crypto/qce/core.c
> > @@ -5,6 +5,7 @@
> >
> >   #include <linux/clk.h>
> >   #include <linux/dma-mapping.h>
> > +#include <linux/interconnect.h>
> >   #include <linux/interrupt.h>
> >   #include <linux/module.h>
> >   #include <linux/mod_devicetable.h>
> > @@ -22,6 +23,8 @@
> >   #define QCE_MAJOR_VERSION5  0x05
> >   #define QCE_QUEUE_LENGTH    1
> >
> > +#define QCE_DEFAULT_MEM_BANDWIDTH    393600
> > +
> >   static const struct qce_algo_ops *qce_ops[] = {
> >   #ifdef CONFIG_CRYPTO_DEV_QCE_SKCIPHER
> >       &skcipher_ops,
> > @@ -206,21 +209,35 @@ static int qce_crypto_probe(struct platform_device *pdev)
> >       if (ret < 0)
> >               return ret;
> >
> > +     qce->mem_path = of_icc_get(qce->dev, "memory");
>
> Please consider to use devm_of_icc_get() here also.

Thanks, I will fix this in the v5.

Regards,
Bhupesh

> > +     if (IS_ERR(qce->mem_path))
> > +             return PTR_ERR(qce->mem_path);
> > +
> >       qce->core = devm_clk_get(qce->dev, "core");
> > -     if (IS_ERR(qce->core))
> > -             return PTR_ERR(qce->core);
> > +     if (IS_ERR(qce->core)) {
> > +             ret = PTR_ERR(qce->core);
> > +             goto err_mem_path_put;
> > +     }
> >
> >       qce->iface = devm_clk_get(qce->dev, "iface");
> > -     if (IS_ERR(qce->iface))
> > -             return PTR_ERR(qce->iface);
> > +     if (IS_ERR(qce->iface)) {
> > +             ret = PTR_ERR(qce->iface);
> > +             goto err_mem_path_put;
> > +     }
> >
> >       qce->bus = devm_clk_get(qce->dev, "bus");
> > -     if (IS_ERR(qce->bus))
> > -             return PTR_ERR(qce->bus);
> > +     if (IS_ERR(qce->bus)) {
> > +             ret = PTR_ERR(qce->bus);
> > +             goto err_mem_path_put;
> > +     }
> > +
> > +     ret = icc_set_bw(qce->mem_path, QCE_DEFAULT_MEM_BANDWIDTH, QCE_DEFAULT_MEM_BANDWIDTH);
> > +     if (ret)
> > +             goto err_mem_path_put;
> >
> >       ret = clk_prepare_enable(qce->core);
> >       if (ret)
> > -             return ret;
> > +             goto err_mem_path_disable;
> >
> >       ret = clk_prepare_enable(qce->iface);
> >       if (ret)
> > @@ -260,6 +277,10 @@ static int qce_crypto_probe(struct platform_device *pdev)
> >       clk_disable_unprepare(qce->iface);
> >   err_clks_core:
> >       clk_disable_unprepare(qce->core);
> > +err_mem_path_disable:
> > +     icc_set_bw(qce->mem_path, 0, 0);
> > +err_mem_path_put:
> > +     icc_put(qce->mem_path);
> >       return ret;
> >   }
> >
> > diff --git a/drivers/crypto/qce/core.h b/drivers/crypto/qce/core.h
> > index 085774cdf641..228fcd69ec51 100644
> > --- a/drivers/crypto/qce/core.h
> > +++ b/drivers/crypto/qce/core.h
> > @@ -35,6 +35,7 @@ struct qce_device {
> >       void __iomem *base;
> >       struct device *dev;
> >       struct clk *core, *iface, *bus;
> > +     struct icc_path *mem_path;
> >       struct qce_dma_data dma;
> >       int burst_size;
> >       unsigned int pipe_pair_id;
> >
>
> --
> Best wishes,
> Vladimir

^ permalink raw reply	[flat|nested] 52+ messages in thread

* Re: [PATCH v4 13/20] dma: qcom: bam_dma: Add support to initialize interconnect path
  2021-10-13 19:15   ` Vladimir Zapolskiy
@ 2021-10-24 13:53     ` Bhupesh Sharma
  0 siblings, 0 replies; 52+ messages in thread
From: Bhupesh Sharma @ 2021-10-24 13:53 UTC (permalink / raw)
  To: Vladimir Zapolskiy
  Cc: MSM, linux-crypto, bhupesh.linux, Linux Kernel Mailing List,
	devicetree, Rob Herring, Andy Gross, Herbert Xu,
	David S . Miller, Thara Gopinath, Bjorn Andersson

Hi Vladimir,

On Thu, 14 Oct 2021 at 00:46, Vladimir Zapolskiy
<vladimir.zapolskiy@linaro.org> wrote:
>
> Hi Bhupesh, Thara,
>
> On 10/13/21 1:55 PM, Bhupesh Sharma wrote:
> > From: Thara Gopinath <thara.gopinath@linaro.org>
> >
> > BAM dma engine associated with certain hardware blocks could require
> > relevant interconnect pieces be initialized prior to the dma engine
> > initialization. For e.g. crypto bam dma engine on sm8250. Such requirement
> > is passed on to the bam dma driver from dt via the "interconnects"
> > property.  Add support in bam_dma driver to check whether the interconnect
> > path is accessible/enabled prior to attempting driver intializations.
> >
> > Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> > Cc: Rob Herring <robh+dt@kernel.org>
> > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
> > [Make header file inclusion alphabetical]
> > Signed-off-by: Thara Gopinath <thara.gopinath@linaro.org>
> > ---
> >   drivers/dma/qcom/bam_dma.c | 16 +++++++++++++++-
> >   1 file changed, 15 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/dma/qcom/bam_dma.c b/drivers/dma/qcom/bam_dma.c
> > index c8a77b428b52..fc84ef42507d 100644
> > --- a/drivers/dma/qcom/bam_dma.c
> > +++ b/drivers/dma/qcom/bam_dma.c
> > @@ -26,6 +26,7 @@
> >   #include <linux/kernel.h>
> >   #include <linux/io.h>
> >   #include <linux/init.h>
> > +#include <linux/interconnect.h>
> >   #include <linux/slab.h>
> >   #include <linux/module.h>
> >   #include <linux/interrupt.h>
> > @@ -392,6 +393,7 @@ struct bam_device {
> >       const struct reg_offset_data *layout;
> >
> >       struct clk *bamclk;
> > +     struct icc_path *mem_path;
> >       int irq;
> >
> >       /* dma start transaction tasklet */
> > @@ -1284,9 +1286,18 @@ static int bam_dma_probe(struct platform_device *pdev)
> >               return ret;
> >       }
> >
> > +     /* Ensure that interconnects are initialized */
> > +     bdev->mem_path = of_icc_get(bdev->dev, "memory");
>
> I suppose devm_of_icc_get() usage could leave the error path and
> bam_dma_remove() intact.

Thanks, I will fix this in the v5.

Regards,
Bhupesh

> > +
> > +     if (IS_ERR(bdev->mem_path)) {
> > +             ret = PTR_ERR(bdev->mem_path);
> > +             dev_err(bdev->dev, "failed to acquire icc path %d\n", ret);
> > +             goto err_disable_clk;
> > +     }
> > +
> >       ret = bam_init(bdev);
> >       if (ret)
> > -             goto err_disable_clk;
> > +             goto err_icc_path_put;
> >
> >       tasklet_setup(&bdev->task, dma_tasklet);
> >
> > @@ -1371,6 +1382,8 @@ static int bam_dma_probe(struct platform_device *pdev)
> >               tasklet_kill(&bdev->channels[i].vc.task);
> >   err_tasklet_kill:
> >       tasklet_kill(&bdev->task);
> > +err_icc_path_put:
> > +     icc_put(bdev->mem_path);
> >   err_disable_clk:
> >       clk_disable_unprepare(bdev->bamclk);
> >
> > @@ -1406,6 +1419,7 @@ static int bam_dma_remove(struct platform_device *pdev)
> >
> >       tasklet_kill(&bdev->task);
> >
> > +     icc_put(bdev->mem_path);
> >       clk_disable_unprepare(bdev->bamclk);
> >
> >       return 0;
> >
>
> --
> Best wishes,
> Vladimir

^ permalink raw reply	[flat|nested] 52+ messages in thread

* Re: [PATCH v4 05/20] dt-bindings: qcom-bam: Add 'interconnects' & 'interconnect-names' to optional properties
  2021-10-14  7:03     ` Bhupesh Sharma
@ 2021-10-24 13:55       ` Bhupesh Sharma
  0 siblings, 0 replies; 52+ messages in thread
From: Bhupesh Sharma @ 2021-10-24 13:55 UTC (permalink / raw)
  To: Rob Herring
  Cc: Herbert Xu, devicetree, Rob Herring, Thara Gopinath,
	bhupesh.linux, Andy Gross, MSM, linux-crypto, David S . Miller,
	Bjorn Andersson, Linux Kernel Mailing List

Hi Rob,

On Thu, 14 Oct 2021 at 12:33, Bhupesh Sharma <bhupesh.sharma@linaro.org> wrote:
>
> Hello Rob,
>
> Thanks for your review.
> These issues are already fixed via patches within this series itself
> (as some dts also need correction to pass the 'make dtbs_check'
> check). I am not sure, but it seems the check was run without applying
> other patches from this series.
>
> See details below:
>
> On Thu, 14 Oct 2021 at 00:09, Rob Herring <robh@kernel.org> wrote:
> >
> > On Wed, 13 Oct 2021 16:25:26 +0530, Bhupesh Sharma wrote:
> > > Add new optional properties - 'interconnects' and
> > > 'interconnect-names' to the device-tree binding documentation for
> > > qcom-bam DMA IP.
> > >
> > > These properties describe the interconnect path between bam and main
> > > memory and the interconnect type respectively.
> > >
> > > Cc: Thara Gopinath <thara.gopinath@linaro.org>
> > > Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> > > Cc: Rob Herring <robh+dt@kernel.org>
> > > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
> > > ---
> > >  Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml | 8 ++++++++
> > >  1 file changed, 8 insertions(+)
> > >
> >
> > Running 'make dtbs_check' with the schema in this patch gives the
> > following warnings. Consider if they are expected or the schema is
> > incorrect. These may not be new warnings.
> >
> > Note that it is not yet a requirement to have 0 warnings for dtbs_check.
> > This will change in the future.
> >
> > Full log is available here: https://patchwork.ozlabs.org/patch/1540390
> >
> >
> > dma@12142000: $nodename:0: 'dma@12142000' does not match '^dma-controller(@.*)?$'
> >         arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dt.yaml
> >
> > dma@12182000: $nodename:0: 'dma@12182000' does not match '^dma-controller(@.*)?$'
> >         arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dt.yaml
> >         arch/arm/boot/dts/qcom-apq8064-cm-qs600.dt.yaml
> >         arch/arm/boot/dts/qcom-apq8064-ifc6410.dt.yaml
> >         arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dt.yaml
> >         arch/arm/boot/dts/qcom-ipq8064-ap148.dt.yaml
> >         arch/arm/boot/dts/qcom-ipq8064-rb3011.dt.yaml
> >         arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dt.yaml
> >
> > dma@121c2000: $nodename:0: 'dma@121c2000' does not match '^dma-controller(@.*)?$'
> >         arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dt.yaml
> >         arch/arm/boot/dts/qcom-apq8064-cm-qs600.dt.yaml
> >         arch/arm/boot/dts/qcom-apq8064-ifc6410.dt.yaml
> >         arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dt.yaml
> >
> > dma@12402000: $nodename:0: 'dma@12402000' does not match '^dma-controller(@.*)?$'
> >         arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dt.yaml
> >         arch/arm/boot/dts/qcom-apq8064-cm-qs600.dt.yaml
> >         arch/arm/boot/dts/qcom-apq8064-ifc6410.dt.yaml
> >         arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dt.yaml
> >         arch/arm/boot/dts/qcom-ipq8064-ap148.dt.yaml
> >         arch/arm/boot/dts/qcom-ipq8064-rb3011.dt.yaml
> >
> > dma@1dc4000: $nodename:0: 'dma@1dc4000' does not match '^dma-controller(@.*)?$'
> >         arch/arm64/boot/dts/qcom/sdm845-cheza-r1.dt.yaml
> >         arch/arm64/boot/dts/qcom/sdm845-cheza-r2.dt.yaml
> >         arch/arm64/boot/dts/qcom/sdm845-cheza-r3.dt.yaml
> >         arch/arm64/boot/dts/qcom/sdm845-db845c.dt.yaml
> >         arch/arm64/boot/dts/qcom/sdm845-mtp.dt.yaml
> >         arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dt.yaml
> >         arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dt.yaml
> >         arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dt.yaml
> >         arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dt.yaml
>
> All the above will be fixed by '[PATCH 01/20] arm64/dts: qcom: Fix 'dma' &
>  'qcom,controlled-remotely' nodes in dts' in this series. See the git
> log of the this patch for details:
>
> 'A few qcom device-tree files define dma-controller nodes
> with non-standard 'node names' and also set
> the bool property 'qcom,controlled-remotely' incorrectly, which
> leads to following errors with 'make dtbs_check':
>
>  $ arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dt.yaml:
>      dma@1dc4000: $nodename:0: 'dma@1dc4000' does not match
>      '^dma-controller(@.*)?$'
>
>  $ arch/arm64/boot/dts/qcom/sm8250-mtp.dt.yaml:
>      dma@1dc4000: qcom,controlled-remotely: 'oneOf' conditional
>      failed, one must be fixed:
>     [[1]] is not of type 'boolean'
>     True was expected
>     [[1]] is not of type 'null'
>
> Fix the same.
> '
>
> > dma@1dc4000: 'iommus' does not match any of the regexes: 'pinctrl-[0-9]+'
> >         arch/arm64/boot/dts/qcom/sdm845-cheza-r1.dt.yaml
> >         arch/arm64/boot/dts/qcom/sdm845-cheza-r2.dt.yaml
> >         arch/arm64/boot/dts/qcom/sdm845-cheza-r3.dt.yaml
> >         arch/arm64/boot/dts/qcom/sdm845-db845c.dt.yaml
> >         arch/arm64/boot/dts/qcom/sdm845-mtp.dt.yaml
> >         arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dt.yaml
> >         arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dt.yaml
> >         arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dt.yaml
> >         arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dt.yaml
>
> Fixed by ' [PATCH 06/20] dt-bindings: qcom-bam: Add 'iommus' to optional
>  properties ' in this series.
>
> > dma@1dc4000: qcom,controlled-remotely: 'oneOf' conditional failed, one must be fixed:
> >         arch/arm64/boot/dts/qcom/sdm845-cheza-r1.dt.yaml
> >         arch/arm64/boot/dts/qcom/sdm845-cheza-r2.dt.yaml
> >         arch/arm64/boot/dts/qcom/sdm845-cheza-r3.dt.yaml
> >         arch/arm64/boot/dts/qcom/sdm845-db845c.dt.yaml
> >         arch/arm64/boot/dts/qcom/sdm845-mtp.dt.yaml
> >         arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dt.yaml
> >         arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dt.yaml
> >         arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dt.yaml
> >         arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dt.yaml
>
> Again this would be fixed by '[PATCH 01/20] arm64/dts: qcom: Fix 'dma' &
>  'qcom,controlled-remotely' nodes in dts' in this series.
>
> > dma@704000: $nodename:0: 'dma@704000' does not match '^dma-controller(@.*)?$'
> >         arch/arm64/boot/dts/qcom/ipq8074-hk01.dt.yaml
> >         arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dt.yaml
> >         arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dt.yaml
>
> Fixed by '[PATCH 01/20] arm64/dts: qcom: Fix 'dma' &
> 'qcom,controlled-remotely' nodes in dts' in this series
>
> > dma@704000: qcom,controlled-remotely: 'oneOf' conditional failed, one must be fixed:
> >         arch/arm64/boot/dts/qcom/ipq8074-hk01.dt.yaml
> >         arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dt.yaml
> >         arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dt.yaml
>
> Fixed by '[PATCH 01/20] arm64/dts: qcom: Fix 'dma' &
> 'qcom,controlled-remotely' nodes in dts' in this series
>
> > dma@7544000: $nodename:0: 'dma@7544000' does not match '^dma-controller(@.*)?$'
> >         arch/arm64/boot/dts/qcom/apq8096-db820c.dt.yaml
> >         arch/arm64/boot/dts/qcom/apq8096-ifc6640.dt.yaml
> >         arch/arm64/boot/dts/qcom/msm8996-mtp.dt.yaml
> >         arch/arm64/boot/dts/qcom/msm8996-pmi8996-sony-xperia-tone-dora.dt.yaml
> >         arch/arm64/boot/dts/qcom/msm8996-pmi8996-sony-xperia-tone-kagura.dt.yaml
> >         arch/arm64/boot/dts/qcom/msm8996-pmi8996-sony-xperia-tone-keyaki.dt.yaml
> >         arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone-dora.dt.yaml
> >         arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone-kagura.dt.yaml
> >         arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone-keyaki.dt.yaml
> >
> > dma@7584000: $nodename:0: 'dma@7584000' does not match '^dma-controller(@.*)?$'
> >         arch/arm64/boot/dts/qcom/apq8096-db820c.dt.yaml
> >         arch/arm64/boot/dts/qcom/apq8096-ifc6640.dt.yaml
> >         arch/arm64/boot/dts/qcom/msm8996-mtp.dt.yaml
> >         arch/arm64/boot/dts/qcom/msm8996-pmi8996-sony-xperia-tone-dora.dt.yaml
> >         arch/arm64/boot/dts/qcom/msm8996-pmi8996-sony-xperia-tone-kagura.dt.yaml
> >         arch/arm64/boot/dts/qcom/msm8996-pmi8996-sony-xperia-tone-keyaki.dt.yaml
> >         arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone-dora.dt.yaml
> >         arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone-kagura.dt.yaml
> >         arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone-keyaki.dt.yaml
> >
> > dma@7884000: $nodename:0: 'dma@7884000' does not match '^dma-controller(@.*)?$'
> >         arch/arm/boot/dts/qcom-ipq4018-ap120c-ac-bit.dt.yaml
> >         arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dt.yaml
> >         arch/arm/boot/dts/qcom-ipq4018-jalapeno.dt.yaml
> >         arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dt.yaml
> >         arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dt.yaml
> >         arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dt.yaml
> >         arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dt.yaml
> >         arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dt.yaml
> >
> > dma@7984000: $nodename:0: 'dma@7984000' does not match '^dma-controller(@.*)?$'
> >         arch/arm/boot/dts/qcom-ipq4018-ap120c-ac-bit.dt.yaml
> >         arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dt.yaml
> >         arch/arm/boot/dts/qcom-ipq4018-jalapeno.dt.yaml
> >         arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dt.yaml
> >         arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dt.yaml
> >         arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dt.yaml
> >         arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dt.yaml
> >         arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dt.yaml
> >
> > dma@8e04000: $nodename:0: 'dma@8e04000' does not match '^dma-controller(@.*)?$'
> >         arch/arm/boot/dts/qcom-ipq4018-ap120c-ac-bit.dt.yaml
> >         arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dt.yaml
> >         arch/arm/boot/dts/qcom-ipq4018-jalapeno.dt.yaml
> >         arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dt.yaml
> >         arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dt.yaml
> >         arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dt.yaml
> >         arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dt.yaml
> >         arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dt.yaml
> >
> > dma@c184000: $nodename:0: 'dma@c184000' does not match '^dma-controller(@.*)?$'
> >         arch/arm64/boot/dts/qcom/msm8998-asus-novago-tp370ql.dt.yaml
> >         arch/arm64/boot/dts/qcom/msm8998-hp-envy-x2.dt.yaml
> >         arch/arm64/boot/dts/qcom/msm8998-lenovo-miix-630.dt.yaml
> >         arch/arm64/boot/dts/qcom/msm8998-mtp.dt.yaml
> >         arch/arm64/boot/dts/qcom/msm8998-oneplus-cheeseburger.dt.yaml
> >         arch/arm64/boot/dts/qcom/msm8998-oneplus-dumpling.dt.yaml
>
> All the above 6 issues are fixed by '[PATCH 01/20] arm64/dts: qcom: Fix 'dma' &
>  'qcom,controlled-remotely' nodes in dts' in this series.
>
> > dma-controller@17184000: 'iommus' does not match any of the regexes: 'pinctrl-[0-9]+'
> >         arch/arm64/boot/dts/qcom/sdm845-cheza-r1.dt.yaml
> >         arch/arm64/boot/dts/qcom/sdm845-cheza-r2.dt.yaml
> >         arch/arm64/boot/dts/qcom/sdm845-cheza-r3.dt.yaml
> >         arch/arm64/boot/dts/qcom/sdm845-db845c.dt.yaml
> >         arch/arm64/boot/dts/qcom/sdm845-mtp.dt.yaml
> >         arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dt.yaml
> >         arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dt.yaml
> >         arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dt.yaml
> >         arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dt.yaml
>
> Fixed by ' [PATCH 06/20] dt-bindings: qcom-bam: Add 'iommus' to optional
>  properties ' in this series.
>
> > dma-controller@704000: 'qcom,config-pipe-trust-reg' does not match any of the regexes: 'pinctrl-[0-9]+'
> >         arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dt.yaml
>
> Fixed by '[PATCH 02/20] arm64/dts: qcom: ipq6018: Remove unused
>  'qcom,config-pipe-trust-reg' property' in this series.
>
> > dma-controller@704000: qcom,controlled-remotely: 'oneOf' conditional failed, one must be fixed:
> >         arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dt.yaml
>
> Fixed by '[PATCH 01/20] arm64/dts: qcom: Fix 'dma' &
> ''qcom,controlled-remotely' nodes in dts' in this series.
>
> > dma-controller@7984000: clock-names:0: 'bam_clk' was expected
> >         arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dt.yaml
> >
> > dma-controller@7984000: clock-names: Additional items are not allowed ('bam_clk' was unexpected)
> >         arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dt.yaml
> >
> > dma-controller@7984000: clock-names: ['iface_clk', 'bam_clk'] is too long
> >         arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dt.yaml
> >
> > dma-controller@7984000: clocks: [[9, 138], [9, 137]] is too long
> >         arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dt.yaml
>
> Fixed by '[PATCH 03/20] arm64/dts: qcom: ipq6018: Remove unused 'iface_clk'
> property from dma-controller node' in this series.
>
> In summary, I ran 'make dtbs_check' after applying this series on
> linus's tip and linux-next's tip as well and saw no errors being
> reported for 'Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml'.

Ping. Do I need to fix anything in v5 or are the fixes regarding the
YAML documentation fine? I am about to send the v5.

Regards,
Bhupesh

^ permalink raw reply	[flat|nested] 52+ messages in thread

* Re: [PATCH v4 00/20] Enable Qualcomm Crypto Engine on sm8250
  2021-10-20 14:03 ` [PATCH v4 00/20] Enable Qualcomm Crypto Engine on sm8250 Thara Gopinath
@ 2021-10-24 13:58   ` Bhupesh Sharma
  0 siblings, 0 replies; 52+ messages in thread
From: Bhupesh Sharma @ 2021-10-24 13:58 UTC (permalink / raw)
  To: Thara Gopinath
  Cc: MSM, linux-crypto, bhupesh.linux, Linux Kernel Mailing List,
	devicetree, Rob Herring, Andy Gross, Herbert Xu,
	David S . Miller, Bjorn Andersson

Hi Thara,

On Wed, 20 Oct 2021 at 19:33, Thara Gopinath <thara.gopinath@linaro.org> wrote:
>
> On 10/13/21 6:55 AM, Bhupesh Sharma wrote:
> > Sorry for a delayed v4, but I have been caught up with some other
> > patches.
>
> Hi Bhupesh,
>
> If possible, please consider splitting this series into 2. One with
> changes required to support crypto driver on
> sm8250 and other with the generic fixes / fixing the dt-bindings et all.
> It would be easier to review as well

That's a good suggestion, but I would suggest keeping the series as
one for now (as we are already approaching v5 and most of the review
comments are taken care of in v5).

Regards,
Bhupesh

> > Changes since v3:
> > =================
> > - v3 can be seen here: https://lore.kernel.org/linux-arm-msm/20210519143700.27392-1-bhupesh.sharma@linaro.org/
> > - Dropped a couple of patches from v3, on basis of the review comments:
> >     ~ [PATCH 13/17] crypto: qce: core: Make clocks optional
> >     ~ [PATCH 15/17] crypto: qce: Convert the device found dev_dbg() to dev_info()
> > - Addressed review comments from Thara, Rob and Stephan Gerhold.
> > - Collect Reviewed-by from Rob and Thara on some of the patches from the
> >    v3 patchset.
> >
> > Changes since v2:
> > =================
> > - v2 can be seen here: https://lore.kernel.org/dmaengine/20210505213731.538612-1-bhupesh.sharma@linaro.org/
> > - Drop a couple of patches from v1, which tried to address the defered
> >    probing of qce driver in case bam dma driver is not yet probed.
> >    Replace it instead with a single (simpler) patch [PATCH 16/17].
> > - Convert bam dma and qce crypto dt-bindings to YAML.
> > - Addressed review comments from Thara, Bjorn, Vinod and Rob.
> >
> > Changes since v1:
> > =================
> > - v1 can be seen here: https://lore.kernel.org/linux-arm-msm/20210310052503.3618486-1-bhupesh.sharma@linaro.org/
> > - v1 did not work well as reported earlier by Dmitry, so v2 contains the following
> >    changes/fixes:
> >    ~ Enable the interconnect path b/w BAM DMA and main memory first
> >      before trying to access the BAM DMA registers.
> >    ~ Enable the interconnect path b/w qce crytpo and main memory first
> >      before trying to access the qce crypto registers.
> >    ~ Make sure to document the required and optional properties for both
> >      BAM DMA and qce crypto drivers.
> >    ~ Add a few debug related print messages in case the qce crypto driver
> >      passes or fails to probe.
> >    ~ Convert the qce crypto driver probe to a defered one in case the BAM DMA
> >      or the interconnect driver(s) (needed on specific Qualcomm parts) are not
> >      yet probed.
> >
> > Qualcomm crypto engine is also available on sm8250 SoC.
> > It supports hardware accelerated algorithms for encryption
> > and authentication. It also provides support for aes, des, 3des
> > encryption algorithms and sha1, sha256, hmac(sha1), hmac(sha256)
> > authentication algorithms.
> >
> > Tested the enabled crypto algorithms with cryptsetup test utilities
> > on sm8250-mtp and RB5 board (see [1]) and also with crypto self-tests,
> > including the fuzz tests (CONFIG_CRYPTO_MANAGER_EXTRA_TESTS=y).
> >
> > Note that this series is rebased on a SMMU related fix from Arnd applied
> > on either linus's tip of linux-next's tip (see [2]), without which
> > the sm8250 based boards fail to boot with the latest tip.
> >
> > [1]. https://linux.die.net/man/8/cryptsetup
> > [2]. https://lore.kernel.org/linux-arm-kernel/CAA8EJpoD4Th1tdwYQLnZur2oA0xX0LojSrNFLyJqdi6+rnB3YQ@mail.gmail.com/T/
> >
> > Cc: Thara Gopinath <thara.gopinath@linaro.org>
> > Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> > Cc: Rob Herring <robh+dt@kernel.org>
> >
> > Bhupesh Sharma (17):
> >    arm64/dts: qcom: Fix 'dma' & 'qcom,controlled-remotely' nodes in dts
> >    arm64/dts: qcom: ipq6018: Remove unused 'qcom,config-pipe-trust-reg'
> >      property
> >    arm64/dts: qcom: ipq6018: Remove unused 'iface_clk' property from
> >      dma-controller node
> >    dt-bindings: qcom-bam: Convert binding to YAML
> >    dt-bindings: qcom-bam: Add 'interconnects' & 'interconnect-names' to
> >      optional properties
> >    dt-bindings: qcom-bam: Add 'iommus' to optional properties
> >    dt-bindings: qcom-qce: Convert bindings to yaml
> >    dt-bindings: qcom-qce: Add 'interconnects' and move 'clocks' to
> >      optional properties
> >    dt-bindings: qcom-qce: Add 'iommus' to optional properties
> >    arm64/dts: qcom: sdm845: Use RPMH_CE_CLK macro directly
> >    dt-bindings: crypto : Add new compatible strings for qcom-qce
> >    arm64/dts: qcom: Use new compatibles for crypto nodes
> >    crypto: qce: Add new compatibles for qce crypto driver
> >    crypto: qce: Print a failure msg in case probe() fails
> >    crypto: qce: Defer probing if BAM dma channel is not yet initialized
> >    crypto: qce: Add 'sm8250-qce' compatible string check
> >    arm64/dts: qcom: sm8250: Add dt entries to support crypto engine.
> >
> > Thara Gopinath (3):
> >    dma: qcom: bam_dma: Add support to initialize interconnect path
> >    crypto: qce: core: Add support to initialize interconnect path
> >    crypto: qce: core: Make clocks optional
> >
> >   .../devicetree/bindings/crypto/qcom-qce.yaml  |  90 +++++++++++++++
> >   .../devicetree/bindings/dma/qcom_bam_dma.txt  |  50 --------
> >   .../devicetree/bindings/dma/qcom_bam_dma.yaml | 107 ++++++++++++++++++
> >   arch/arm64/boot/dts/qcom/ipq6018.dtsi         |  10 +-
> >   arch/arm64/boot/dts/qcom/ipq8074.dtsi         |   4 +-
> >   arch/arm64/boot/dts/qcom/msm8996.dtsi         |   4 +-
> >   arch/arm64/boot/dts/qcom/msm8998.dtsi         |   2 +-
> >   arch/arm64/boot/dts/qcom/sdm845.dtsi          |  10 +-
> >   arch/arm64/boot/dts/qcom/sm8250.dtsi          |  28 +++++
> >   drivers/crypto/qce/core.c                     |  66 +++++++----
> >   drivers/crypto/qce/core.h                     |   1 +
> >   drivers/dma/qcom/bam_dma.c                    |  16 ++-
> >   12 files changed, 302 insertions(+), 86 deletions(-)
> >   create mode 100644 Documentation/devicetree/bindings/crypto/qcom-qce.yaml
> >   delete mode 100644 Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
> >   create mode 100644 Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml
> >
>
>

^ permalink raw reply	[flat|nested] 52+ messages in thread

* Re: [PATCH v4 18/20] crypto: qce: Defer probing if BAM dma channel is not yet initialized
  2021-10-20 14:10   ` Thara Gopinath
@ 2021-10-24 14:05     ` Bhupesh Sharma
  0 siblings, 0 replies; 52+ messages in thread
From: Bhupesh Sharma @ 2021-10-24 14:05 UTC (permalink / raw)
  To: Thara Gopinath
  Cc: MSM, linux-crypto, bhupesh.linux, Linux Kernel Mailing List,
	devicetree, Rob Herring, Andy Gross, Herbert Xu,
	David S . Miller, Bjorn Andersson

Hi Thara,

On Wed, 20 Oct 2021 at 19:40, Thara Gopinath <thara.gopinath@linaro.org> wrote:
>
> On 10/13/21 6:55 AM, Bhupesh Sharma wrote:
> > Since the Qualcomm qce crypto driver needs the BAM dma driver to be
> > setup first (to allow crypto operations), it makes sense to defer
> > the qce crypto driver probing in case the BAM dma driver is not yet
> > probed.
> >
> > Move the code leg requesting dma channels earlier in the
> > probe() flow. This fixes the qce probe failure issues when both qce
> > and BMA dma are compiled as static part of the kernel.
>
> Hi Bhupesh,
>
> I am quite curious to know the nature of probe failure you are seeing
> with the current sequence.  I am not against changing the sequence but
> for me when a driver is enabled, it is clocks first, interconnect next
> and then dma. Also I have tested the current sequence on sm8150 with
> both the modules built in as static and I have not seen the failure.

Sure. The problem I faced was the following. Let's consider the
scenario where while the qce crypto driver and the interconnect are
compiled as static parts of the kernel, the bam DMA driver is compiled
as a module, then the -EPROBE_DEFER return leg from the qce crypto
driver is very late in the probe() flow, as we first turn on the
clocks and then the interconnect.

Now the suggested linux deferred probe implementation is to return as
early from the caling driver in case the called driver (subdev) is not
yet ready. SInce the qce crypto driver requires the bam DMA to be set
up first, it makes sense to move 'qce_dma_request' early in the boot
flow. If it's not yet probed(), it probably doesn't make sense to set
up the clks and interconnects yet in the qce driver. We can do it
later when the bam DMA is setup.

I have tested the following combinations with the change I made in
this patchset:

1. qce - static, bam - module, interconnect - module ->
qce_dma_request returned -EPROBE_DEFER
2. qce - static, bam - module, interconnect - static ->
qce_dma_request returned -EPROBE_DEFER
3. qce - static, bam - static, interconnect - module ->
qce_dma_request returned -EPROBE_DEFER
4. qce - static, bam - static, interconnect - static -> no -EPROBE_DEFER

Thanks,
Bhupesh

> > Cc: Thara Gopinath <thara.gopinath@linaro.org>
> > Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
> > ---
> >   drivers/crypto/qce/core.c | 20 ++++++++++++--------
> >   1 file changed, 12 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c
> > index cb8c77709e1e..c6f686126fc9 100644
> > --- a/drivers/crypto/qce/core.c
> > +++ b/drivers/crypto/qce/core.c
> > @@ -209,9 +209,19 @@ static int qce_crypto_probe(struct platform_device *pdev)
> >       if (ret < 0)
> >               return ret;
> >
> > +     /* qce driver requires BAM dma driver to be setup first.
> > +      * In case the dma channel are not set yet, this check
> > +      * helps use to return -EPROBE_DEFER earlier.
> > +      */
> > +     ret = qce_dma_request(qce->dev, &qce->dma);
> > +     if (ret)
> > +             return ret;
> > +
> >       qce->mem_path = of_icc_get(qce->dev, "memory");
> > -     if (IS_ERR(qce->mem_path))
> > +     if (IS_ERR(qce->mem_path)) {
> > +             qce_dma_release(&qce->dma);
> >               return PTR_ERR(qce->mem_path);
> > +     }
> >
> >       qce->core = devm_clk_get_optional(qce->dev, "core");
> >       if (IS_ERR(qce->core)) {
> > @@ -247,10 +257,6 @@ static int qce_crypto_probe(struct platform_device *pdev)
> >       if (ret)
> >               goto err_clks_iface;
> >
> > -     ret = qce_dma_request(qce->dev, &qce->dma);
> > -     if (ret)
> > -             goto err_clks;
> > -
> >       ret = qce_check_version(qce);
> >       if (ret)
> >               goto err_clks;
> > @@ -265,12 +271,10 @@ static int qce_crypto_probe(struct platform_device *pdev)
> >
> >       ret = qce_register_algs(qce);
> >       if (ret)
> > -             goto err_dma;
> > +             goto err_clks;
> >
> >       return 0;
> >
> > -err_dma:
> > -     qce_dma_release(&qce->dma);
> >   err_clks:
> >       clk_disable_unprepare(qce->bus);
> >   err_clks_iface:
> >
>
>

^ permalink raw reply	[flat|nested] 52+ messages in thread

* Re: [PATCH v4 08/20] dt-bindings: qcom-qce: Add 'interconnects' and move 'clocks' to optional properties
  2021-10-13 10:55 ` [PATCH v4 08/20] dt-bindings: qcom-qce: Add 'interconnects' and move 'clocks' to optional properties Bhupesh Sharma
@ 2021-10-26 19:40   ` Rob Herring
  0 siblings, 0 replies; 52+ messages in thread
From: Rob Herring @ 2021-10-26 19:40 UTC (permalink / raw)
  To: Bhupesh Sharma
  Cc: linux-arm-msm, linux-crypto, bhupesh.linux, linux-kernel,
	devicetree, agross, herbert, davem, Thara Gopinath,
	Bjorn Andersson

On Wed, Oct 13, 2021 at 04:25:29PM +0530, Bhupesh Sharma wrote:
> Add 'interconnects' and 'interconnect-names' as optional properties
> to the device-tree binding documentation for qcom crypto IP.
> 
> These properties describe the interconnect path between crypto and main
> memory and the interconnect type respectively.

And why are 'clocks' now optional? Seems like it should be 2 patches 
given the long subject with a conjunction.

> 
> Cc: Thara Gopinath <thara.gopinath@linaro.org>
> Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
> ---
>  Documentation/devicetree/bindings/crypto/qcom-qce.yaml | 10 ++++++++--
>  1 file changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
> index b7ae873dc943..954f762090f3 100644
> --- a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
> +++ b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
> @@ -32,6 +32,14 @@ properties:
>        - const: bus
>        - const: core
>  
> +  interconnects:
> +    maxItems: 1
> +    description: |
> +      Interconnect path between qce crypto and main memory.
> +
> +  interconnect-names:
> +    const: memory
> +
>    dmas:
>      items:
>        - description: DMA specifiers for tx dma channel.
> @@ -45,8 +53,6 @@ properties:
>  required:
>    - compatible
>    - reg
> -  - clocks
> -  - clock-names
>    - dmas
>    - dma-names
>  
> -- 
> 2.31.1
> 
> 

^ permalink raw reply	[flat|nested] 52+ messages in thread

* Re: [PATCH v4 09/20] dt-bindings: qcom-qce: Add 'iommus' to optional properties
  2021-10-13 10:55 ` [PATCH v4 09/20] dt-bindings: qcom-qce: Add 'iommus' " Bhupesh Sharma
@ 2021-10-26 19:40   ` Rob Herring
  0 siblings, 0 replies; 52+ messages in thread
From: Rob Herring @ 2021-10-26 19:40 UTC (permalink / raw)
  To: Bhupesh Sharma
  Cc: herbert, robh+dt, bhupesh.linux, agross, Thara Gopinath, davem,
	devicetree, linux-kernel, linux-arm-msm, linux-crypto,
	Bjorn Andersson

On Wed, 13 Oct 2021 16:25:30 +0530, Bhupesh Sharma wrote:
> Add the missing optional property - 'iommus' to the
> device-tree binding documentation for qcom-qce crypto IP.
> 
> This property describes the phandle(s) to apps_smmu node with sid mask.
> 
> Cc: Thara Gopinath <thara.gopinath@linaro.org>
> Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
> ---
>  .../devicetree/bindings/crypto/qcom-qce.yaml          | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 52+ messages in thread

end of thread, other threads:[~2021-10-26 19:41 UTC | newest]

Thread overview: 52+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-10-13 10:55 [PATCH v4 00/20] Enable Qualcomm Crypto Engine on sm8250 Bhupesh Sharma
2021-10-13 10:55 ` [PATCH v4 01/20] arm64/dts: qcom: Fix 'dma' & 'qcom,controlled-remotely' nodes in dts Bhupesh Sharma
2021-10-13 10:55 ` [PATCH v4 02/20] arm64/dts: qcom: ipq6018: Remove unused 'qcom,config-pipe-trust-reg' property Bhupesh Sharma
2021-10-13 10:55 ` [PATCH v4 03/20] arm64/dts: qcom: ipq6018: Remove unused 'iface_clk' property from dma-controller node Bhupesh Sharma
2021-10-13 10:55 ` [PATCH v4 04/20] dt-bindings: qcom-bam: Convert binding to YAML Bhupesh Sharma
2021-10-13 12:56   ` Vladimir Zapolskiy
2021-10-13 17:13     ` Bhupesh Sharma
2021-10-13 10:55 ` [PATCH v4 05/20] dt-bindings: qcom-bam: Add 'interconnects' & 'interconnect-names' to optional properties Bhupesh Sharma
2021-10-13 13:03   ` Vladimir Zapolskiy
2021-10-13 17:14     ` Bhupesh Sharma
2021-10-13 18:39   ` Rob Herring
2021-10-14  7:03     ` Bhupesh Sharma
2021-10-24 13:55       ` Bhupesh Sharma
2021-10-13 10:55 ` [PATCH v4 06/20] dt-bindings: qcom-bam: Add 'iommus' " Bhupesh Sharma
2021-10-13 10:55 ` [PATCH v4 07/20] dt-bindings: qcom-qce: Convert bindings to yaml Bhupesh Sharma
2021-10-13 13:05   ` Vladimir Zapolskiy
2021-10-13 17:15     ` Bhupesh Sharma
2021-10-13 10:55 ` [PATCH v4 08/20] dt-bindings: qcom-qce: Add 'interconnects' and move 'clocks' to optional properties Bhupesh Sharma
2021-10-26 19:40   ` Rob Herring
2021-10-13 10:55 ` [PATCH v4 09/20] dt-bindings: qcom-qce: Add 'iommus' " Bhupesh Sharma
2021-10-26 19:40   ` Rob Herring
2021-10-13 10:55 ` [PATCH v4 10/20] arm64/dts: qcom: sdm845: Use RPMH_CE_CLK macro directly Bhupesh Sharma
2021-10-13 10:55 ` [PATCH v4 11/20] dt-bindings: crypto : Add new compatible strings for qcom-qce Bhupesh Sharma
2021-10-18 18:26   ` Rob Herring
2021-10-13 10:55 ` [PATCH v4 12/20] arm64/dts: qcom: Use new compatibles for crypto nodes Bhupesh Sharma
2021-10-13 10:55 ` [PATCH v4 13/20] dma: qcom: bam_dma: Add support to initialize interconnect path Bhupesh Sharma
2021-10-13 19:15   ` Vladimir Zapolskiy
2021-10-24 13:53     ` Bhupesh Sharma
2021-10-13 10:55 ` [PATCH v4 14/20] crypto: qce: core: " Bhupesh Sharma
2021-10-13 19:19   ` Vladimir Zapolskiy
2021-10-24 13:53     ` Bhupesh Sharma
2021-10-13 10:55 ` [PATCH v4 15/20] crypto: qce: Add new compatibles for qce crypto driver Bhupesh Sharma
2021-10-13 19:22   ` Vladimir Zapolskiy
2021-10-20 14:07   ` Thara Gopinath
2021-10-24 13:52     ` Bhupesh Sharma
2021-10-13 10:55 ` [PATCH v4 16/20] crypto: qce: core: Make clocks optional Bhupesh Sharma
2021-10-13 19:23   ` Vladimir Zapolskiy
2021-10-24 13:34     ` Bhupesh Sharma
2021-10-13 10:55 ` [PATCH v4 17/20] crypto: qce: Print a failure msg in case probe() fails Bhupesh Sharma
2021-10-13 19:26   ` Vladimir Zapolskiy
2021-10-24 13:33     ` Bhupesh Sharma
2021-10-13 10:55 ` [PATCH v4 18/20] crypto: qce: Defer probing if BAM dma channel is not yet initialized Bhupesh Sharma
2021-10-13 20:49   ` Vladimir Zapolskiy
2021-10-14  7:40     ` Bhupesh Sharma
2021-10-14  8:42       ` Vladimir Zapolskiy
2021-10-20 14:10   ` Thara Gopinath
2021-10-24 14:05     ` Bhupesh Sharma
2021-10-13 10:55 ` [PATCH v4 19/20] crypto: qce: Add 'sm8250-qce' compatible string check Bhupesh Sharma
2021-10-20 14:11   ` Thara Gopinath
2021-10-13 10:55 ` [PATCH v4 20/20] arm64/dts: qcom: sm8250: Add dt entries to support crypto engine Bhupesh Sharma
2021-10-20 14:03 ` [PATCH v4 00/20] Enable Qualcomm Crypto Engine on sm8250 Thara Gopinath
2021-10-24 13:58   ` Bhupesh Sharma

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