From: Juergen Gross <jgross@suse.com>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-kernel@vger.kernel.org, xen-devel@lists.xenproject.org,
x86@kernel.org, boris.ostrovsky@oracle.com, hpa@zytor.com,
mingo@redhat.com
Subject: Re: [PATCH 2/2] x86/pae: use 64 bit atomic xchg function in native_ptep_get_and_clear
Date: Mon, 20 Aug 2018 16:55:57 +0200 [thread overview]
Message-ID: <9286b65d-3f55-2b48-848b-b507be6883c7@suse.com> (raw)
In-Reply-To: <alpine.DEB.2.21.1808201519270.1551@nanos.tec.linutronix.de>
On 20/08/18 15:26, Thomas Gleixner wrote:
> On Mon, 20 Aug 2018, Juergen Gross wrote:
>> In case adding about 6 cycles for native_ptep_get_and_clear() is believed
>> to be too bad I can modify the patch to add a paravirt function for that
>> purpose in order to add the overhead for Xen guests only (in fact the
>> overhead for Xen guests will be less, as only one instruction writing to
>> the PTE has to be emulated by the hypervisor).
>
> I doubt that its worth the trouble of yet another paravirt thingy.
>
>> ---
>> arch/x86/include/asm/pgtable-3level.h | 14 ++++++++------
>> 1 file changed, 8 insertions(+), 6 deletions(-)
>>
>> diff --git a/arch/x86/include/asm/pgtable-3level.h b/arch/x86/include/asm/pgtable-3level.h
>> index a564084c6141..7919ae4e27d8 100644
>> --- a/arch/x86/include/asm/pgtable-3level.h
>> +++ b/arch/x86/include/asm/pgtable-3level.h
>> @@ -2,6 +2,8 @@
>> #ifndef _ASM_X86_PGTABLE_3LEVEL_H
>> #define _ASM_X86_PGTABLE_3LEVEL_H
>>
>> +#include <asm/atomic64_32.h>
>> +
>> /*
>> * Intel Physical Address Extension (PAE) Mode - three-level page
>> * tables on PPro+ CPUs.
>> @@ -148,14 +150,14 @@ static inline void pud_clear(pud_t *pudp)
>> #ifdef CONFIG_SMP
>> static inline pte_t native_ptep_get_and_clear(pte_t *ptep)
>> {
>> - pte_t res;
>> + union {
>> + pte_t pte;
>> + long long val;
>> + } res;
>>
>> - /* xchg acts as a barrier before the setting of the high bits */
>> - res.pte_low = xchg(&ptep->pte_low, 0);
>> - res.pte_high = ptep->pte_high;
>> - ptep->pte_high = 0;
>> + res.val = arch_atomic64_xchg((atomic64_t *)ptep, 0);
>
> Couldn't you just keep
>
> pte_t res;
>
> and do:
>
> res.pte = (pteval_t) arch_atomic64_xchg((atomic64_t *)ptep, 0);
>
> Hmm?
Yes, got this suggestion already by Jan. I'm waiting with V2 until
tomorrow to see whether someone has other complaints.
Juergen
prev parent reply other threads:[~2018-08-20 14:56 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-08-20 5:14 [PATCH 0/2] x86/xen: avoid 32-bit writes to PTEs in PV PAE guests Juergen Gross
2018-08-20 5:14 ` [PATCH 1/2] x86/xen: don't write ptes directly in 32-bit PV guests Juergen Gross
2018-08-20 8:38 ` [Xen-devel] " Jan Beulich
2018-08-20 5:14 ` [PATCH 2/2] x86/pae: use 64 bit atomic xchg function in native_ptep_get_and_clear Juergen Gross
2018-08-20 8:40 ` [Xen-devel] " Jan Beulich
2018-08-20 8:56 ` Juergen Gross
2018-08-20 13:26 ` Thomas Gleixner
2018-08-20 14:55 ` Juergen Gross [this message]
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