From: Leonardo Bras <leobras.c@gmail.com>
To: Alexey Kardashevskiy <aik@ozlabs.ru>,
Michael Ellerman <mpe@ellerman.id.au>,
Benjamin Herrenschmidt <benh@kernel.crashing.org>,
Paul Mackerras <paulus@samba.org>,
Christophe Leroy <christophe.leroy@c-s.fr>,
Joel Stanley <joel@jms.id.au>,
Thiago Jung Bauermann <bauerman@linux.ibm.com>,
Ram Pai <linuxram@us.ibm.com>,
Brian King <brking@linux.vnet.ibm.com>,
Murilo Fossa Vicentini <muvic@linux.ibm.com>,
David Dai <zdai@linux.vnet.ibm.com>
Cc: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v1 01/10] powerpc/pseries/iommu: Replace hard-coded page shift
Date: Fri, 28 Aug 2020 16:55:25 -0300 [thread overview]
Message-ID: <93037398c7afaabc0411890998f3f29f741c8aff.camel@gmail.com> (raw)
In-Reply-To: <1e77a3d9-dff9-f58b-45be-77be7cbea41a@ozlabs.ru>
On Fri, 2020-08-28 at 12:27 +1000, Alexey Kardashevskiy wrote:
>
> On 28/08/2020 01:32, Leonardo Bras wrote:
> > Hello Alexey, thank you for this feedback!
> >
> > On Sat, 2020-08-22 at 19:33 +1000, Alexey Kardashevskiy wrote:
> > > > +#define TCE_RPN_BITS 52 /* Bits 0-51 represent RPN on TCE */
> > >
> > > Ditch this one and use MAX_PHYSMEM_BITS instead? I am pretty sure this
> > > is the actual limit.
> >
> > I understand this MAX_PHYSMEM_BITS(51) comes from the maximum physical memory addressable in the machine. IIUC, it means we can access physical address up to (1ul << MAX_PHYSMEM_BITS).
> >
> > This 52 comes from PAPR "Table 9. TCE Definition" which defines bits
> > 0-51 as the RPN. By looking at code, I understand that it means we may input any address < (1ul << 52) to TCE.
> >
> > In practice, MAX_PHYSMEM_BITS should be enough as of today, because I suppose we can't ever pass a physical page address over
> > (1ul << 51), and TCE accepts up to (1ul << 52).
> > But if we ever increase MAX_PHYSMEM_BITS, it doesn't necessarily means that TCE_RPN_BITS will also be increased, so I think they are independent values.
> >
> > Does it make sense? Please let me know if I am missing something.
>
> The underlying hardware is PHB3/4 about which the IODA2 Version 2.4
> 6Apr2012.pdf spec says:
>
> "The number of most significant RPN bits implemented in the TCE is
> dependent on the max size of System Memory to be supported by the platform".
>
> IODA3 is the same on this matter.
>
> This is MAX_PHYSMEM_BITS and PHB itself does not have any other limits
> on top of that. So the only real limit comes from MAX_PHYSMEM_BITS and
> where TCE_RPN_BITS comes from exactly - I have no idea.
Well, I created this TCE_RPN_BITS = 52 because the previous mask was a
hardcoded 40-bit mask (0xfffffffffful), for hard-coded 12-bit (4k)
pagesize, and on PAPR+/LoPAR also defines TCE as having bits 0-51
described as RPN, as described before.
IODA3 Revision 3.0_prd1 (OpenPowerFoundation), Figure 3.4 and 3.5.
shows system memory mapping into a TCE, and the TCE also has bits 0-51
for the RPN (52 bits). "Table 3.6. TCE Definition" also shows it.
In fact, by the looks of those figures, the RPN_MASK should always be a
52-bit mask, and RPN = (page >> tceshift) & RPN_MASK.
Maybe that's it?
>
>
> > >
> > > > +#define TCE_RPN_MASK(ps) ((1ul << (TCE_RPN_BITS - (ps))) - 1)
> > > > #define TCE_VALID 0x800 /* TCE valid */
> > > > #define TCE_ALLIO 0x400 /* TCE valid for all lpars */
> > > > #define TCE_PCI_WRITE 0x2 /* write from PCI allowed */
> > > > diff --git a/arch/powerpc/platforms/pseries/iommu.c b/arch/powerpc/platforms/pseries/iommu.c
> > > > index e4198700ed1a..8fe23b7dff3a 100644
> > > > --- a/arch/powerpc/platforms/pseries/iommu.c
> > > > +++ b/arch/powerpc/platforms/pseries/iommu.c
> > > > @@ -107,6 +107,9 @@ static int tce_build_pSeries(struct iommu_table *tbl, long index,
> > > > u64 proto_tce;
> > > > __be64 *tcep;
> > > > u64 rpn;
> > > > + const unsigned long tceshift = tbl->it_page_shift;
> > > > + const unsigned long pagesize = IOMMU_PAGE_SIZE(tbl);
> > > > + const u64 rpn_mask = TCE_RPN_MASK(tceshift);
> > >
> > > Using IOMMU_PAGE_SIZE macro for the page size and not using
> > > IOMMU_PAGE_MASK for the mask - this incosistency makes my small brain
> > > explode :) I understand the history but maaaaan... Oh well, ok.
> > >
> >
> > Yeah, it feels kind of weird after two IOMMU related consts. :)
> > But sure IOMMU_PAGE_MASK() would not be useful here :)
> >
> > And this kind of let me thinking:
> > > > + rpn = __pa(uaddr) >> tceshift;
> > > > + *tcep = cpu_to_be64(proto_tce | (rpn & rpn_mask) << tceshift);
> > Why not:
> > rpn_mask = TCE_RPN_MASK(tceshift) << tceshift;
>
> A mask for a page number (but not the address!) hurts my brain, masks
> are good against addresses but numbers should already have all bits
> adjusted imho, may be it is just me :-/
>
>
> >
> > rpn = __pa(uaddr) & rpn_mask;
> > *tcep = cpu_to_be64(proto_tce | rpn)
> >
> > I am usually afraid of changing stuff like this, but I think it's safe.
> >
> > > Good, otherwise. Thanks,
> >
> > Thank you for reviewing!
> >
> >
> >
next prev parent reply other threads:[~2020-08-28 19:55 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-17 23:40 [PATCH v1 00/10] DDW indirect mapping Leonardo Bras
2020-08-17 23:40 ` [PATCH v1 01/10] powerpc/pseries/iommu: Replace hard-coded page shift Leonardo Bras
2020-08-22 9:33 ` Alexey Kardashevskiy
2020-08-27 15:32 ` Leonardo Bras
2020-08-28 2:27 ` Alexey Kardashevskiy
2020-08-28 19:55 ` Leonardo Bras [this message]
2020-08-31 0:06 ` Alexey Kardashevskiy
2020-08-31 1:41 ` Oliver O'Halloran
2020-08-31 3:48 ` Alexey Kardashevskiy
2020-09-01 21:38 ` Leonardo Bras
2020-09-03 4:26 ` Alexey Kardashevskiy
2020-08-17 23:40 ` [PATCH v1 02/10] powerpc/kernel/iommu: Align size for IOMMU_PAGE_SIZE on iommu_*_coherent() Leonardo Bras
2020-08-22 10:07 ` Alexey Kardashevskiy
2020-08-27 16:51 ` Leonardo Bras
2020-08-28 1:40 ` Alexey Kardashevskiy
2020-08-28 20:41 ` Leonardo Bras
2020-08-31 0:47 ` Alexey Kardashevskiy
2020-09-01 22:34 ` Leonardo Bras
2020-09-03 4:41 ` Alexey Kardashevskiy
2020-09-04 6:04 ` Leonardo Bras
2020-09-08 3:18 ` Alexey Kardashevskiy
2020-08-17 23:40 ` [PATCH v1 03/10] powerpc/kernel/iommu: Use largepool as a last resort when !largealloc Leonardo Bras
2020-08-22 10:09 ` Alexey Kardashevskiy
2020-08-27 16:58 ` Leonardo Bras
2020-08-17 23:40 ` [PATCH v1 04/10] powerpc/kernel/iommu: Add new iommu_table_in_use() helper Leonardo Bras
2020-08-22 10:34 ` Alexey Kardashevskiy
2020-08-27 18:34 ` Leonardo Bras
2020-08-28 1:51 ` Alexey Kardashevskiy
2020-08-17 23:40 ` [PATCH v1 05/10] powerpc/pseries/iommu: Add iommu_pseries_alloc_table() helper Leonardo Bras
2020-08-24 0:38 ` Alexey Kardashevskiy
2020-08-27 21:23 ` Leonardo Bras
2020-08-17 23:40 ` [PATCH v1 06/10] powerpc/pseries/iommu: Add ddw_list_add() helper Leonardo Bras
2020-08-24 3:46 ` Alexey Kardashevskiy
2020-08-27 22:11 ` Leonardo Bras
2020-08-28 1:58 ` Alexey Kardashevskiy
2020-08-28 21:28 ` Leonardo Bras
2020-08-17 23:40 ` [PATCH v1 07/10] powerpc/pseries/iommu: Allow DDW windows starting at 0x00 Leonardo Bras
2020-08-24 3:44 ` Alexey Kardashevskiy
2020-08-28 14:04 ` Leonardo Bras
2020-08-31 0:50 ` Alexey Kardashevskiy
2020-08-17 23:40 ` [PATCH v1 08/10] powerpc/pseries/iommu: Add ddw_property_create() and refactor enable_ddw() Leonardo Bras
2020-08-24 5:07 ` Alexey Kardashevskiy
2020-08-28 15:25 ` Leonardo Bras
2020-08-31 4:34 ` Alexey Kardashevskiy
2020-09-02 5:27 ` Leonardo Bras
2020-08-17 23:40 ` [PATCH v1 09/10] powerpc/pseries/iommu: Make use of DDW even if it does not map the partition Leonardo Bras
2020-08-24 5:17 ` Alexey Kardashevskiy
2020-08-28 18:36 ` Leonardo Bras
2020-08-31 4:35 ` Alexey Kardashevskiy
2020-09-02 6:11 ` Leonardo Bras
2020-09-04 1:00 ` Alexey Kardashevskiy
2020-08-17 23:40 ` [PATCH v1 10/10] powerpc/pseries/iommu: Rename "direct window" to "dma window" Leonardo Bras
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