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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id o126-v6sm4758515wmo.3.2018.11.23.06.39.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Nov 2018 06:39:23 -0800 (PST) Subject: Re: [PATCH RFC 1/8] drm/bridge: dw-hdmi: Add SCDC and TMDS Scrambling support To: Laurent Pinchart Cc: architt@codeaurora.org, a.hajda@samsung.com, dri-devel@lists.freedesktop.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, Nickey Yang , Huicong Xu References: <20181123140221.15700-1-narmstrong@baylibre.com> <1880382.AeP59NOuia@avalon> <18593437.RcPPLLf6y1@avalon> From: Neil Armstrong Openpgp: preference=signencrypt Autocrypt: addr=narmstrong@baylibre.com; prefer-encrypt=mutual; keydata= xsBNBE1ZBs8BCAD78xVLsXPwV/2qQx2FaO/7mhWL0Qodw8UcQJnkrWmgTFRobtTWxuRx8WWP GTjuhvbleoQ5Cxjr+v+1ARGCH46MxFP5DwauzPekwJUD5QKZlaw/bURTLmS2id5wWi3lqVH4 BVF2WzvGyyeV1o4RTCYDnZ9VLLylJ9bneEaIs/7cjCEbipGGFlfIML3sfqnIvMAxIMZrvcl9 qPV2k+KQ7q+aXavU5W+yLNn7QtXUB530Zlk/d2ETgzQ5FLYYnUDAaRl+8JUTjc0CNOTpCeik 80TZcE6f8M76Xa6yU8VcNko94Ck7iB4vj70q76P/J7kt98hklrr85/3NU3oti3nrIHmHABEB AAHNKE5laWwgQXJtc3Ryb25nIDxuYXJtc3Ryb25nQGJheWxpYnJlLmNvbT7CwHsEEwEKACUC GyMGCwkIBwMCBhUIAgkKCwQWAgMBAh4BAheABQJXDO2CAhkBAAoJEBaat7Gkz/iubGIH/iyk RqvgB62oKOFlgOTYCMkYpm2aAOZZLf6VKHKc7DoVwuUkjHfIRXdslbrxi4pk5VKU6ZP9AKsN NtMZntB8WrBTtkAZfZbTF7850uwd3eU5cN/7N1Q6g0JQihE7w4GlIkEpQ8vwSg5W7hkx3yQ6 2YzrUZh/b7QThXbNZ7xOeSEms014QXazx8+txR7jrGF3dYxBsCkotO/8DNtZ1R+aUvRfpKg5 ZgABTC0LmAQnuUUf2PHcKFAHZo5KrdO+tyfL+LgTUXIXkK+tenkLsAJ0cagz1EZ5gntuheLD YJuzS4zN+1Asmb9kVKxhjSQOcIh6g2tw7vaYJgL/OzJtZi6JlIXOwE0ETVkGzwEIALyKDN/O GURaHBVzwjgYq+ZtifvekdrSNl8TIDH8g1xicBYpQTbPn6bbSZbdvfeQPNCcD4/EhXZuhQXM coJsQQQnO4vwVULmPGgtGf8PVc7dxKOeta+qUh6+SRh3vIcAUFHDT3f/Zdspz+e2E0hPV2hi SvICLk11qO6cyJE13zeNFoeY3ggrKY+IzbFomIZY4yG6xI99NIPEVE9lNBXBKIlewIyVlkOa YvJWSV+p5gdJXOvScNN1epm5YHmf9aE2ZjnqZGoMMtsyw18YoX9BqMFInxqYQQ3j/HpVgTSv mo5ea5qQDDUaCsaTf8UeDcwYOtgI8iL4oHcsGtUXoUk33HEAEQEAAcLAXwQYAQIACQUCTVkG zwIbDAAKCRAWmrexpM/4rrXiB/sGbkQ6itMrAIfnM7IbRuiSZS1unlySUVYu3SD6YBYnNi3G 5EpbwfBNuT3H8//rVvtOFK4OD8cRYkxXRQmTvqa33eDIHu/zr1HMKErm+2SD6PO9umRef8V8 2o2oaCLvf4WeIssFjwB0b6a12opuRP7yo3E3gTCSKmbUuLv1CtxKQF+fUV1cVaTPMyT25Od+ RC1K+iOR0F54oUJvJeq7fUzbn/KdlhA8XPGzwGRy4zcsPWvwnXgfe5tk680fEKZVwOZKIEuJ C3v+/yZpQzDvGYJvbyix0lHnrCzq43WefRHI5XTTQbM0WUIBIcGmq38+OgUsMYu4NzLu7uZF Acmp6h8g Organization: Baylibre Message-ID: <931fd1f8-3c13-2d46-68ab-d375bffc2e53@baylibre.com> Date: Fri, 23 Nov 2018 15:39:22 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.2.1 MIME-Version: 1.0 In-Reply-To: <18593437.RcPPLLf6y1@avalon> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 23/11/2018 15:33, Laurent Pinchart wrote: > Hi Neil, > > On Friday, 23 November 2018 16:29:15 EET Neil Armstrong wrote: >> On 23/11/2018 15:25, Laurent Pinchart wrote: >>> On Friday, 23 November 2018 16:02:14 EET Neil Armstrong wrote: >>>> Add support for SCDC Setup for TMDS Clock > 3.4GHz and enable TMDS >>>> Scrambling when supported or mandatory. >>>> >>>> This patch also adds an helper to setup the control bit to support >>>> the hight TMDS Bit Period/TMDS Clock-Period Ratio as required with >>> >>> s/hight/high/ ? >> >> Thanks for catching ! >> >>>> TMDS Clock > 3.4GHz for HDMI2.0 3840x2160@60/50 modes. >>> >>> Why do you need a helper for this, is there no way it could be handled >>> internally ? >> >> I could, but all the platforms would also do it internally... seems better >> to have common helper, no ? And it will be usable by the PHY models handler >> in the dw-hdmi driver aswell. > > I meant internally in the dw-hdmi driver, not in the glue layer. No since the spec says you must setup div40 support in the SCDC right before enabling the TMDS stream and wait 100ms minimum, it would eventually work from the dw-hdmi driver, but we cannot presume how the platforms PHYs are setup. > >>>> These changes were based on work done by Huicong Xu >>>> and Nickey Yang to support HDMI2.0 modes >>>> on the Rockchip 4.4 BSP kernel at [1] >>>> >>>> [1] https://github.com/rockchip-linux/kernel/tree/release-4.4 >>>> >>>> Cc: Nickey Yang >>>> Cc: Huicong Xu >>>> Signed-off-by: Neil Armstrong >>>> --- >>>> >>>> drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 45 +++++++++++++++++++++-- >>>> drivers/gpu/drm/bridge/synopsys/dw-hdmi.h | 1 + >>>> include/drm/bridge/dw_hdmi.h | 1 + >>>> 3 files changed, 44 insertions(+), 3 deletions(-) >>>> >>>> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c >>>> b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c index >>>> 5971976284bf..523508af70b0 100644 >>>> --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c >>>> +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c > > [snip] > >>>> @@ -1562,6 +1581,26 @@ static void hdmi_av_composer(struct dw_hdmi *hdmi, >>>> vsync_len /= 2; >>>> } >>>> >>>> + /* Scrambling Control */ >>>> + if (hdmi_info->scdc.supported) { >>>> + if (vmode->mpixelclock > 340000000 || >>>> + hdmi_info->scdc.scrambling.low_rates) { >>>> + drm_scdc_readb(&hdmi->i2c->adap, SCDC_SINK_VERSION, >>>> + &bytes); >>>> + drm_scdc_writeb(&hdmi->i2c->adap, SCDC_SOURCE_VERSION, >>>> + bytes); >>> >>> Shouldn't the source version be min(sink version, highest supported source >>> version) ? >> >> How should the "highest supported source version" be defined ? > > That's the highest version supported by the DW HDMI TX controller, and is an > intrinsic property of the IP core. With the above code, a sink newer than the > DW HDMI TX will incorrectly be told that the source supports the same version > as the sink. You are right, we could be ourselves on the already-know dw-hdmi IP version we know to determine a currently known max version for the current platforms using dw-hdmi. > >>>> + drm_scdc_set_scrambling(&hdmi->i2c->adap, 1); >>>> + hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, >>>> + HDMI_MC_SWRSTZ); >>>> + hdmi_writeb(hdmi, 1, HDMI_FC_SCRAMBLER_CTRL); >>>> + } else { >>>> + hdmi_writeb(hdmi, 0, HDMI_FC_SCRAMBLER_CTRL); >>>> + hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, >>>> + HDMI_MC_SWRSTZ); >>>> + drm_scdc_set_scrambling(&hdmi->i2c->adap, 0); >>>> + } >>>> + } >>>> + >>>> /* Set up horizontal active pixel width */ >>>> hdmi_writeb(hdmi, mode->hdisplay >> 8, HDMI_FC_INHACTV1); >>>> hdmi_writeb(hdmi, mode->hdisplay, HDMI_FC_INHACTV0); > > [snip] >