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[188.155.176.92]) by smtp.gmail.com with ESMTPSA id u17-20020a170906781100b006f3ef214dacsm6228554ejm.18.2022.05.10.05.54.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 10 May 2022 05:54:06 -0700 (PDT) Message-ID: <9365247a-8aa0-bad5-c619-9d5a984b17de@linaro.org> Date: Tue, 10 May 2022 14:54:05 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.8.1 Subject: Re: [PATCH v5 1/2] arm64: dts: marvell: Add Armada 98DX2530 SoC and RD-AC5X board Content-Language: en-US To: Andrew Lunn Cc: Chris Packham , "catalin.marinas@arm.com" , "will@kernel.org" , "robh+dt@kernel.org" , "krzysztof.kozlowski+dt@linaro.org" , "gregory.clement@bootlin.com" , "sebastian.hesselbarth@gmail.com" , "kostap@marvell.com" , "robert.marko@sartura.hr" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" References: <20220504044624.951841-1-chris.packham@alliedtelesis.co.nz> <20220504044624.951841-2-chris.packham@alliedtelesis.co.nz> <6770d320-b998-0c9d-3824-0d429834b289@alliedtelesis.co.nz> <3498643b-cb2e-5685-65e0-7efe1113783f@linaro.org> From: Krzysztof Kozlowski In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 10/05/2022 14:37, Andrew Lunn wrote: > On Tue, May 10, 2022 at 09:08:08AM +0200, Krzysztof Kozlowski wrote: >> On 10/05/2022 06:14, Chris Packham wrote: >>> >>> Based on the information I have (which isn't much) there is a ref_clk >>> input that is connected to a 25MHz oscillator and then I'm assuming >>> these are all generated from that with various dividers. 25MHz is the >>> only documented option. >>> >>> There doesn't appear to be any documented register where I can read out >>> the divider ratios. It might be nice I could have the fixed osc node and >>> have these 3 clocks derived with fixed divisors but I don't see any what >>> of achieving that. >> >> >> OK, but where are the dividers? The ref_clk is outside of SoC, so should >> be defined in board DTS (at least its rate). If the rest is in the SoC, >> they are usually part of clock controller, because usually they belong >> to some power domain or have some clock gating. > > 25MHz is a 'magic value' in Ethernet, nearly everything is based > around it. And remember this SoC is basically an Ethernet switch with > a small CPU glued on one side. If you gated clocks derived from the > 25MHz reference clock, probably part of your Ethernet switch stops > working, which is the whole point of this SoC. So i doubt there are > gates on the derived clocks. If there is any gating and power domains, > it is generally at a different level. You can power down individual > ports of the Ethernet switch. But generally, there is one bit in a > register somewhere to do that, and you don't have direct control over > clocks and regulators etc. The 25 MHz input clock I understand, it was about other clocks, like spi, axi and core. These clearly look like part of SoC, so defining them with a "stubs" (uncontrollable fixed-clock) is not the best way of modelling an SoC. Although maybe this SoC does not have a proper clock controller and even SPI and AXI clocks are always on? Best regards, Krzysztof