From: Andrew Lunn <andrew@lunn.ch>
To: "Alexis Lothoré" <alexis.lothore@bootlin.com>
Cc: "Florian Fainelli" <f.fainelli@gmail.com>,
"Vladimir Oltean" <olteanv@gmail.com>,
"David S. Miller" <davem@davemloft.net>,
"Eric Dumazet" <edumazet@google.com>,
"Jakub Kicinski" <kuba@kernel.org>,
"Paolo Abeni" <pabeni@redhat.com>,
"Richard Cochran" <richardcochran@gmail.com>,
"Rob Herring" <robh+dt@kernel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Russell King" <linux@armlinux.org.uk>,
linux-kernel@vger.kernel.org, netdev@vger.kernel.org,
devicetree@vger.kernel.org,
"Thomas Petazzoni" <thomas.petazzoni@bootlin.com>,
paul.arola@telus.com, scott.roberts@telus.com,
"Marek Behún" <kabel@kernel.org>
Subject: Re: [PATCH net-next v3 4/7] net: dsa: mv88e6xxx: add field to specify internal phys layout
Date: Wed, 24 May 2023 19:10:05 +0200 [thread overview]
Message-ID: <93e2804a-0da2-48a7-942b-5231772459b9@lunn.ch> (raw)
In-Reply-To: <20230524130127.268201-5-alexis.lothore@bootlin.com>
On Wed, May 24, 2023 at 03:01:24PM +0200, Alexis Lothoré wrote:
> mv88e6xxx currently assumes that switch equipped with internal phys have
> those phys mapped contiguously starting from port 0 (see
> mv88e6xxx_phy_is_internal). However, some switches have internal PHYs but
> NOT starting from port 0. For example 88e6393X, 88E6193X and 88E6191X have
> integrated PHYs available on ports 1 to 8
> To properly support this offset, add a new field to allow specifying an
> internal PHYs layout. If field is not set, default layout is assumed (start
> at port 0)
>
> ---
> Changes since v2:
> - move start/end computation out of for loop
> - remove whitespace
>
> Signed-off-by: Alexis Lothoré <alexis.lothore@bootlin.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Andrew
next prev parent reply other threads:[~2023-05-24 17:10 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-24 13:01 [PATCH net-next v3 0/7] net: dsa: mv88e6xxx: add 88E6361 support Alexis Lothoré
2023-05-24 13:01 ` [PATCH net-next v3 1/7] dt-bindings: net: dsa: marvell: add MV88E6361 switch to compatibility list Alexis Lothoré
2023-05-24 13:01 ` [PATCH net-next v3 2/7] net: dsa: mv88e6xxx: pass directly chip structure to mv88e6xxx_phy_is_internal Alexis Lothoré
2023-05-24 13:18 ` Russell King (Oracle)
2023-05-24 14:46 ` Alexis Lothoré
2023-05-24 17:08 ` Andrew Lunn
2023-05-25 9:08 ` Alexis Lothoré
2023-05-24 13:01 ` [PATCH net-next v3 3/7] net: dsa: mv88e6xxx: use mv88e6xxx_phy_is_internal in mv88e6xxx_port_ppu_updates Alexis Lothoré
2023-05-24 13:01 ` [PATCH net-next v3 4/7] net: dsa: mv88e6xxx: add field to specify internal phys layout Alexis Lothoré
2023-05-24 17:10 ` Andrew Lunn [this message]
2023-05-24 13:01 ` [PATCH net-next v3 5/7] net: dsa: mv88e6xxx: fix 88E6393X family " Alexis Lothoré
2023-05-24 13:01 ` [PATCH net-next v3 6/7] net: dsa: mv88e6xxx: pass mv88e6xxx_chip structure to port_max_speed_mode Alexis Lothoré
2023-05-24 13:01 ` [PATCH net-next v3 7/7] net: dsa: mv88e6xxx: enable support for 88E6361 switch Alexis Lothoré
2023-05-24 13:36 ` Russell King (Oracle)
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