From: Atish Patra <atish.patra@wdc.com>
To: Rob Herring <robh+dt@kernel.org>
Cc: "linux-riscv@lists.infradead.org"
<linux-riscv@lists.infradead.org>,
Palmer Dabbelt <palmer@sifive.com>,
Anup Patel <anup@brainfault.org>,
Christoph Hellwig <hch@infradead.org>,
Damien Le Moal <Damien.LeMoal@wdc.com>,
Thomas Gleixner <tglx@linutronix.de>,
Mark Rutland <mark.rutland@arm.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"alankao@andestech.com" <alankao@andestech.com>,
Zong Li <zong@andestech.com>
Subject: Re: [RFC 1/2] dt-bindings: topology: Add RISC-V cpu topology.
Date: Fri, 2 Nov 2018 13:34:06 -0700 [thread overview]
Message-ID: <954ec7be-f7ba-4e00-70fe-130cb4b84e61@wdc.com> (raw)
In-Reply-To: <CAL_Jsq+wProNynprMjQnrz1jmbZT9TmmA-_=vPUxCEED_8xONg@mail.gmail.com>
On 11/2/18 6:09 AM, Rob Herring wrote:
> On Thu, Nov 1, 2018 at 6:04 PM Atish Patra <atish.patra@wdc.com> wrote:
>>
>> Define a RISC-V cpu topology. This is based on cpu-map in ARM world.
>> But it doesn't need a separate thread node for defining SMT systems.
>> Multiple cpu phandle properties can be parsed to identify the sibling
>> hardware threads. Moreover, we do not have cluster concept in RISC-V.
>> So package is a better word choice than cluster for RISC-V.
>
> There was a proposal to add package info for ARM recently. Not sure
> what happened to that, but we don't need 2 different ways.
>
> There's never going to be clusters for RISC-V? What prevents that?
> Seems shortsighted to me.
>
Agreed. My intention was to keep it simple at first go.
If package node is added, that would work for us as well.
>>
>> Signed-off-by: Atish Patra <atish.patra@wdc.com>
>> ---
>> .../devicetree/bindings/riscv/topology.txt | 154 +++++++++++++++++++++
>> 1 file changed, 154 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/riscv/topology.txt
>>
>> diff --git a/Documentation/devicetree/bindings/riscv/topology.txt b/Documentation/devicetree/bindings/riscv/topology.txt
>> new file mode 100644
>> index 00000000..96039ed3
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/riscv/topology.txt
>> @@ -0,0 +1,154 @@
>> +===========================================
>> +RISC-V cpu topology binding description
>> +===========================================
>> +
>> +===========================================
>> +1 - Introduction
>> +===========================================
>> +
>> +In a RISC-V system, the hierarchy of CPUs can be defined through following nodes that
>> +are used to describe the layout of physical CPUs in the system:
>> +
>> +- packages
>> +- core
>> +
>> +The cpu nodes (bindings defined in [1]) represent the devices that
>> +correspond to physical CPUs and are to be mapped to the hierarchy levels.
>> +Simultaneous multi-threading (SMT) systems can also represent their topology
>> +by defining multiple cpu phandles inside core node. The details are explained
>> +in paragraph 3.
>
> I don't see a reason to do this differently than ARM. That said, I
> don't think the thread part is in use on ARM, so it could possibly be
> changed.
>
>> +
>> +The remainder of this document provides the topology bindings for ARM, based
>
> for ARM?
>
Sorry for the typo.
>> +on the Devicetree Specification, available from:
>> +
>> +https://www.devicetree.org/specifications/
>> +
>> +If not stated otherwise, whenever a reference to a cpu node phandle is made its
>> +value must point to a cpu node compliant with the cpu node bindings as
>> +documented in [1].
>> +A topology description containing phandles to cpu nodes that are not compliant
>> +with bindings standardized in [1] is therefore considered invalid.
>> +
>> +This cpu topology binding description is mostly based on the topology defined
>> +in ARM [2].
>> +===========================================
>> +2 - cpu-topology node
>
> cpu-map. Why change this?
>
To my ears, it felt a better name. But I don't mind dropping it in favor
of cpu-map if we are going to standardize cpu-map for both ARM & RISC-V.
> What I would like to see is the ARM topology binding reworked to be
> common or some good reasons why it doesn't work for RISC-V as-is.
>
IMHO, ARM topology can be reworked and put it in a common place so that
RISC-V can leverage that.
My intention for this RFC patch was to start the ball rolling on cpu
topology in RISC-V and see if DT approach is fine with everybody. I
would be happy to see ARM code to move it to a common code base where
RISC-V can reuse it.
Regards,
Atish
> Rob
>
next prev parent reply other threads:[~2018-11-02 20:34 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-01 23:04 [RFC 0/2] Add RISC-V cpu topology Atish Patra
2018-11-01 23:04 ` [RFC 1/2] dt-bindings: topology: " Atish Patra
2018-11-02 13:09 ` Rob Herring
2018-11-02 13:31 ` Sudeep Holla
2018-11-02 15:11 ` Rob Herring
2018-11-02 15:50 ` Sudeep Holla
2018-11-02 20:53 ` Atish Patra
2018-11-02 21:08 ` Rob Herring
2018-11-02 20:34 ` Atish Patra [this message]
2018-11-05 19:38 ` Palmer Dabbelt
2018-11-05 20:10 ` Rob Herring
2018-11-06 0:12 ` Atish Patra
2018-11-06 10:03 ` Nick Kossifidis
2018-11-06 11:37 ` Mark Rutland
2018-11-01 23:04 ` [RFC 2/2] RISC-V: Introduce " Atish Patra
2018-11-02 18:58 ` [RFC 0/2] Add RISC-V " Nick Kossifidis
2018-11-02 21:14 ` Atish Patra
2018-11-02 22:18 ` Nick Kossifidis
2018-11-06 14:13 ` Sudeep Holla
2018-11-06 15:26 ` Nick Kossifidis
2018-11-06 15:50 ` Sudeep Holla
2018-11-06 16:20 ` Mark Rutland
2018-11-07 2:31 ` Nick Kossifidis
2018-11-07 12:06 ` Mark Rutland
2018-11-08 13:45 ` Nick Kossifidis
2018-11-08 15:54 ` Mark Rutland
2018-11-09 3:55 ` Nick Kossifidis
2018-11-07 12:28 ` Sudeep Holla
2018-11-08 14:52 ` Nick Kossifidis
2018-11-08 16:48 ` Sudeep Holla
2018-11-09 2:36 ` Nick Kossifidis
2018-11-09 12:33 ` Sudeep Holla
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=954ec7be-f7ba-4e00-70fe-130cb4b84e61@wdc.com \
--to=atish.patra@wdc.com \
--cc=Damien.LeMoal@wdc.com \
--cc=alankao@andestech.com \
--cc=anup@brainfault.org \
--cc=devicetree@vger.kernel.org \
--cc=hch@infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=mark.rutland@arm.com \
--cc=palmer@sifive.com \
--cc=robh+dt@kernel.org \
--cc=tglx@linutronix.de \
--cc=zong@andestech.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).