From: Terry Bowman <Terry.Bowman@amd.com>
To: Dan Williams <dan.j.williams@intel.com>,
alison.schofield@intel.com, vishal.l.verma@intel.com,
ira.weiny@intel.com, bwidawsk@kernel.org, dave.jiang@intel.com,
Jonathan.Cameron@huawei.com, linux-cxl@vger.kernel.org
Cc: rrichter@amd.com, linux-kernel@vger.kernel.org, bhelgaas@google.com
Subject: Re: [PATCH v5 22/26] cxl/pci: Map RCH downstream AER registers for logging protocol errors
Date: Mon, 12 Jun 2023 13:19:47 -0500 [thread overview]
Message-ID: <95639b45-1166-de98-5fdf-5f8eeab2d123@amd.com> (raw)
In-Reply-To: <6483ecb5a4526_e067a29490@dwillia2-xfh.jf.intel.com.notmuch>
Hi Dan,
I'll make the updates you recommended below.
Regards,
Terry
On 6/9/23 22:23, Dan Williams wrote:
> Terry Bowman wrote:
>> The restricted CXL host (RCH) error handler will log protocol errors
>> using AER and RAS status registers. The AER and RAS registers need
>> to be virtually memory mapped before enabling interrupts. Update
>> __devm_cxl_add_dport() to include RCH RAS and AER mapping.
>>
>> Add 'struct cxl_regs' to 'struct cxl_dport' for saving a unique copy of
>> the RCH downstream port's mapped registers.
>>
>> Co-developed-by: Robert Richter <rrichter@amd.com>
>> Signed-off-by: Robert Richter <rrichter@amd.com>
>> Signed-off-by: Terry Bowman <terry.bowman@amd.com>
>> ---
>> drivers/cxl/core/port.c | 38 ++++++++++++++++++++++++++++++++++++++
>> drivers/cxl/core/regs.c | 1 +
>> drivers/cxl/cxl.h | 11 +++++++++++
>> 3 files changed, 50 insertions(+)
>>
>> diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
>> index 3111f754c740..bc5d0ee9da54 100644
>> --- a/drivers/cxl/core/port.c
>> +++ b/drivers/cxl/core/port.c
>> @@ -8,6 +8,7 @@
>> #include <linux/pci.h>
>> #include <linux/slab.h>
>> #include <linux/idr.h>
>> +#include <linux/aer.h>
>> #include <cxlmem.h>
>> #include <cxlpci.h>
>> #include <cxl.h>
>> @@ -947,6 +948,39 @@ static void cxl_dport_unlink(void *data)
>> sysfs_remove_link(&port->dev.kobj, link_name);
>> }
>>
>> +static int cxl_dport_map_rch_aer(struct cxl_dport *dport)
>> +{
>> + struct cxl_rcrb_info *ri = &dport->rcrb;
>> + resource_size_t aer_phys;
>> + void __iomem *dport_aer;
>> +
>> + if (!dport->rch || !ri->aer_cap)
>> + return -ENODEV;
>> +
>> + aer_phys = ri->aer_cap + ri->base;
>> + dport_aer = devm_cxl_iomap_block(dport->dev, aer_phys,
>> + sizeof(struct aer_capability_regs));
>
> @dport->dev is not suitable to be the @host argument to
> devm_cxl_iomap_block(). It needs to match the lifetime of the @dport
> allocation which means @host needs to be set to @port->dev.
>
>
>> + if (!dport_aer)
>> + return -ENOMEM;
>> +
>> + dport->regs.dport_aer = dport_aer;
>> +
>> + return 0;
>> +}
>> +
>> +static int cxl_dport_map_regs(struct cxl_dport *dport)
>> +{
>> + struct cxl_register_map *map = &dport->comp_map;
>> +
>> + if (!map->component_map.ras.valid)
>> + dev_dbg(map->dev, "RAS registers not found\n");
>> + else if (cxl_map_component_regs(map, &dport->regs.component,
>> + BIT(CXL_CM_CAP_CAP_ID_RAS)))
>> + dev_dbg(dport->dev, "Failed to map RAS capability.\n");
>> +
>> + return cxl_dport_map_rch_aer(dport);
>> +}
>> +
>> static struct cxl_dport *
>> __devm_cxl_add_dport(struct cxl_port *port, struct device *dport_dev,
>> int port_id, resource_size_t component_reg_phys,
>> @@ -1000,6 +1034,10 @@ __devm_cxl_add_dport(struct cxl_port *port, struct device *dport_dev,
>> if (rc && rc != -ENODEV)
>> return ERR_PTR(rc);
>>
>> + rc = cxl_dport_map_regs(dport);
>> + if (rc && rc != -ENODEV)
>> + return ERR_PTR(rc);
>
> I'll repeat the previous comment about replacing:
>
> if (rc && rc != -ENODEV)
>
> ...with an optional initialization at alloc time.
>
>> +
>> cond_cxl_root_lock(port);
>> rc = add_dport(port, dport);
>> cond_cxl_root_unlock(port);
>> diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c
>> index dd6c3c898cff..26fb4f395365 100644
>> --- a/drivers/cxl/core/regs.c
>> +++ b/drivers/cxl/core/regs.c
>> @@ -198,6 +198,7 @@ void __iomem *devm_cxl_iomap_block(struct device *dev, resource_size_t addr,
>>
>> return ret_val;
>> }
>> +EXPORT_SYMBOL_NS_GPL(devm_cxl_iomap_block, CXL);
>>
>> int cxl_map_component_regs(struct cxl_register_map *map,
>> struct cxl_component_regs *regs,
>> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
>> index 6134644b51f8..0e0bcbefefaf 100644
>> --- a/drivers/cxl/cxl.h
>> +++ b/drivers/cxl/cxl.h
>> @@ -209,6 +209,13 @@ struct cxl_regs {
>> struct_group_tagged(cxl_device_regs, device_regs,
>> void __iomem *status, *mbox, *memdev;
>> );
>> + /*
>> + * RCH downstream port specific RAS register
>> + * @aer: CXL 3.0 8.2.1.1 RCH Downstream Port RCRB
>> + */
>> + struct_group_tagged(cxl_rch_regs, rch_regs,
>> + void __iomem *dport_aer;
>> + );
>> };
>>
>> struct cxl_reg_map {
>> @@ -255,6 +262,8 @@ void cxl_probe_component_regs(struct device *dev, void __iomem *base,
>> struct cxl_component_reg_map *map);
>> void cxl_probe_device_regs(struct device *dev, void __iomem *base,
>> struct cxl_device_reg_map *map);
>> +void __iomem *devm_cxl_iomap_block(struct device *dev, resource_size_t addr,
>> + resource_size_t length);
>> int cxl_map_component_regs(struct cxl_register_map *map,
>> struct cxl_component_regs *regs,
>> unsigned long map_mask);
>> @@ -603,6 +612,7 @@ struct cxl_rcrb_info {
>> * @port_id: unique hardware identifier for dport in decoder target list
>> * @rch: Indicate whether this dport was enumerated in RCH or VH mode
>> * @rcrb: Data about the Root Complex Register Block layout
>> + * @regs: Dport parsed register blocks
>> */
>> struct cxl_dport {
>> struct device *dev;
>> @@ -611,6 +621,7 @@ struct cxl_dport {
>> int port_id;
>> bool rch;
>> struct cxl_rcrb_info rcrb;
>> + struct cxl_regs regs;
>> };
>>
>> /**
>> --
>> 2.34.1
>>
>
>
next prev parent reply other threads:[~2023-06-12 18:20 UTC|newest]
Thread overview: 69+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-07 22:16 [PATCH v5 00/26] cxl/pci: Add support for RCH RAS error handling Terry Bowman
2023-06-07 22:16 ` [PATCH v5 01/26] cxl/acpi: Probe RCRB later during RCH downstream port creation Terry Bowman
2023-06-08 1:03 ` Dan Williams
2023-06-08 1:11 ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 02/26] cxl/rch: Prepare for caching the MMIO mapped PCIe AER capability Terry Bowman
2023-06-08 4:53 ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 03/26] cxl: Rename member @dport of struct cxl_dport to @dev Terry Bowman
2023-06-08 6:42 ` Dan Williams
2023-06-08 14:36 ` Terry Bowman
2023-06-08 19:08 ` Dan Williams
2023-06-08 19:22 ` Terry Bowman
2023-06-07 22:16 ` [PATCH v5 04/26] cxl/core/regs: Rename phys_addr in cxl_map_component_regs() Terry Bowman
2023-06-08 6:47 ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 05/26] cxl/core/regs: Add @dev to cxl_register_map Terry Bowman
2023-06-08 19:29 ` Dan Williams
2023-06-08 21:50 ` Terry Bowman
2023-06-07 22:16 ` [PATCH v5 06/26] cxl/pci: Refactor component register discovery for reuse Terry Bowman
2023-06-08 19:57 ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 07/26] cxl/acpi: Moving add_host_bridge_uport() around Terry Bowman
2023-06-08 20:02 ` Dan Williams
2023-06-08 21:50 ` Terry Bowman
2023-06-07 22:16 ` [PATCH v5 08/26] cxl/acpi: Directly bind the CEDT detected CHBCR to the Host Bridge's port Terry Bowman
2023-06-09 4:24 ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 09/26] cxl/regs: Remove early capability checks in Component Register setup Terry Bowman
2023-06-10 0:18 ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 10/26] cxl/mem: Prepare for early RCH dport component register setup Terry Bowman
2023-06-10 0:26 ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 11/26] cxl/pci: Early setup RCH dport component registers from RCRB Terry Bowman
2023-06-10 1:36 ` Dan Williams
2023-06-10 1:44 ` Dan Williams
2023-06-12 20:39 ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 12/26] cxl/port: Store the port's Component Register mappings in struct cxl_port Terry Bowman
2023-06-10 2:18 ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 13/26] cxl/port: Store the downstream port's Component Register mappings in struct cxl_dport Terry Bowman
2023-06-10 2:23 ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 14/26] cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state Terry Bowman
2023-06-10 2:29 ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 15/26] cxl/hdm: Use stored Component Register mappings to map HDM decoder capability Terry Bowman
2023-06-10 2:34 ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 16/26] cxl/port: Remove Component Register base address from struct cxl_port Terry Bowman
2023-06-10 2:36 ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 17/26] cxl/port: Remove Component Register base address from struct cxl_dport Terry Bowman
2023-06-10 2:37 ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 18/26] cxl/pci: Remove Component Register base address from struct cxl_dev_state Terry Bowman
2023-06-10 2:38 ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 19/26] cxl/pci: Add RCH downstream port AER register discovery Terry Bowman
2023-06-10 3:09 ` Dan Williams
2023-06-12 14:41 ` Terry Bowman
2023-06-07 22:16 ` [PATCH v5 20/26] PCI/AER: Refactor cper_print_aer() for use by CXL driver module Terry Bowman
2023-06-10 3:11 ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 21/26] cxl/pci: Update CXL error logging to use RAS register address Terry Bowman
2023-06-10 3:12 ` Dan Williams
2023-06-12 21:12 ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 22/26] cxl/pci: Map RCH downstream AER registers for logging protocol errors Terry Bowman
2023-06-10 3:23 ` Dan Williams
2023-06-12 18:19 ` Terry Bowman [this message]
2023-06-07 22:16 ` [PATCH v5 23/26] cxl/pci: Disable root port interrupts in RCH mode Terry Bowman
2023-06-12 20:29 ` Dan Williams
2023-06-13 15:28 ` Terry Bowman
2023-06-07 22:16 ` [PATCH v5 24/26] cxl/pci: Add RCH downstream port error logging Terry Bowman
2023-06-12 21:38 ` Dan Williams
2023-06-16 16:17 ` Terry Bowman
2023-06-16 16:28 ` Terry Bowman
2023-06-07 22:16 ` [PATCH v5 25/26] PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem dev handler Terry Bowman
2023-06-08 22:54 ` kernel test robot
2023-06-12 22:49 ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 26/26] PCI/AER: Unmask RCEC internal errors to enable RCH downstream port error handling Terry Bowman
2023-06-08 19:21 ` Bjorn Helgaas
2023-06-12 22:57 ` Dan Williams
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