From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933142AbcJQIHc (ORCPT ); Mon, 17 Oct 2016 04:07:32 -0400 Received: from szxga02-in.huawei.com ([119.145.14.65]:28036 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932594AbcJQIGk (ORCPT ); Mon, 17 Oct 2016 04:06:40 -0400 Subject: Re: [PATCH] mfd: Add HiSilicon Flash Memory Controller(FMC) driver To: Rob Herring , , References: <1473130643-12310-1-git-send-email-linshunquan1@hisilicon.com> <20160913145607.GA11998@rob-hp-laptop> <6b522be0-dcec-a84b-f161-69b8805bef62@hisilicon.com> <6108fbb9-e82b-f56e-cf41-18d8859fbdfd@hisilicon.com> CC: Lee Jones , , , "howell.yang@hisilicon.com" , Jiancheng Xue , "jalen.hsu@hisilicon.com" , lvkuanliang 00222834 , "suwenping@hisilicon.com" , "raojun@hisilicon.com" , "kevin.lixu@hisilicon.com" , From: "linshunquan (A)" Message-ID: <95d79627-11a2-3236-3cff-7c294772cc51@hisilicon.com> Date: Mon, 17 Oct 2016 16:03:17 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 MIME-Version: 1.0 In-Reply-To: <6108fbb9-e82b-f56e-cf41-18d8859fbdfd@hisilicon.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-Originating-IP: [10.67.211.114] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2016/10/10 11:19, linshunquan (A) wrote: > > > On 2016/9/15 5:56, Rob Herring wrote: >> On Wed, Sep 14, 2016 at 4:12 AM, linshunquan (A) >> wrote: >>> >>> >>> On 2016/9/13 22:56, Rob Herring wrote: >>>> On Tue, Sep 06, 2016 at 10:57:22AM +0800, linshunquan 00354166 wrote: >>>>> From: Shunquan Lin >>>>> >>>>> This patch adds driver support for HiSilicon Flash Memory >>>>> Controller(FMC). HiSilicon FMC is a multi-functions device which >>>>> supports SPI Nor flash controller, SPI nand Flash controller and >>>>> parallel nand flash controller. >>>>> >>>>> Signed-off-by: Shunquan Lin >>>>> + - spi-nor: >>>>> + Required properties: >>>>> + - compatible : "hisilicon,fmc-spi-nor" >>>>> + see "Documentation/devicetree/bindings/mtd/hisilicon,fmc-spi-nor.txt >>>>> + >>>>> + - spi-nand: >>>>> + Required properties: >>>>> + - compatible : "hisilicon,fmc-spi-nand" >>>>> + - reg : The chipselect for spi-nand devices >>>>> + - address-cells : Should be 1. >>>>> + - size-cells : Should be 0. >>>>> + >>>>> + - nand: >>>>> + Required properties: >>>>> + - compatible : "hisilicon,fmc-nand" >>>>> + - reg : The chipselect for nand devices >>>>> + - address-cells : Should be 1. >>>>> + - size-cells : Should be 0. >>>>> + >>>>> +Example: >>>>> +fmc: spi-nor-controller@10000000 { >>>>> + compatible = "hisilicon,hisi-fmc"; >>>>> + reg = <0x10000000 0x1000>, <0x14000000 0x1000000>; >>>>> + reg-names = "control", "memory"; >>>>> + clocks = <&crg FMC_CLK>; >>>>> + #address-cells = <1>; >>>>> + #size-cells = <0>; >>>>> + >>>>> + hisfc:spi-nor@0 { >>>>> + compatible = "hisilicon,fmc-spi-nor"; >>>> >>>> Is this an actual h/w sub-block? If not remove this node and make the >>>> spi-nor the immediate child. >>>> >>> >>> Hi Herring, >>> Thanks for your reply. Firstly I must correct a mistake here: >>> fmc: spi-nor-controller@10000000 { >>> compatible = "hisilicon,hisi-fmc"; >>> ... >>> correct to: >>> fmc: flash-memory-controller@10000000 { >>> compatible = "hisilicon,hisi-fmc"; >>> ... >>> >>> Spi-nor is a sub block of HiSilicon Flash Memory Controller(FMC), HiSilicon FMC >>> is a multi-functions device, besides it also supports SPI Nand and Parallel Nand. >> >> I understand that, but then were are the registers for the sub-blocks? >> If there is only a single set of chipselects for all devices (i.e. 0 >> to N) and no separate register blocks for the sub-blocks, then you >> don't need this intermediate node. >> > > Hi Rob， > I'm sorry it's taken me so long to get back to you. > > To the HiSilicon FMC, different devices have different chipselect, and you are right, > the register blocks are no separate, but spi nor, spi nand and nand may require > different initial configuration of default sublock clocks and clock frequencies, so > I think this node is necessary. > > Here is a sample about the soc Hi3519: > > in arch/arm/boot/dts/hi3519.dtsi defined: > > fmc: flash-memory-controller@10000000 { > compatible = "hisilicon,hisi-fmc"; > reg = <0x10000000 0x1000>, <0x14000000 0x1000000>; > reg-names = "control", "memory"; > clocks = <&crg HI3519_FMC_CLK>; > #address-cells = <1>; > #size-cells = <0>; > > hisfc:spi-nor { > compatible = "hisilicon,hisi-sfc"; > assigned-clocks = <&crg HI3519_FMC_CLK>; > assigned-clock-rates = <24000000>; > #address-cells = <1>; > #size-cells = <0>; > }; > > hisnfc:spi-nand { > compatible = "hisilicon,fmc-spi-nand"; > assigned-clocks = <&crg HI3519_FMC_CLK>; > assigned-clock-rates = <3000000>; > #address-cells = <1>; > #size-cells = <0>; > }; > }; > > in arch/arm/boot/dts/hi3519-demb.dts, which include hi3519.disi, defined: > > &hisfc { > hi_sfc@0 { > compatible = "jedec,spi-nor"; > reg = <0>; > spi-max-frequency = <160000000>; > m25p,fast-read; > }; > }; > > &hisnfc { > hinand@0 { > compatible = "jedec,spi-nand"; > reg = <0>; > spi-max-frequency = <200000000>; > }; > }; > > Maybe I have not well understood on DTS, I hope I can get some suggestions from Rob. > > Best regards > /Shunquan Lin > Hi Rob, I think seriously about your question again. It is really not necessary to set so many nodes, I have a new solution as blew: fmc: flash-memory-controller@10000000 { compatible = "hisilicon,hisi-fmc"; reg = <0x10000000 0x1000>, <0x14000000 0x1000000>; reg-names = "control", "memory"; clocks = <&crg FMC_CLK>; #address-cells = <1>; #size-cells = <0>; spi-nor@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <160000000>; }; Perhaps, if there are some sub-block to add, we can define: spi-nor@1{ compatible = "jedec,spi-nor"; reg = <1>; spi-max-frequency = <160000000>; } spi-nand@0{ compatible = "jedec,spi-nand"; reg = <2>; spi-max-frequency = <200000000>; } ... } It is so nice to get any reply and suggestion from you. Best regards /Shunquan Lin