From: Ming Qian <ming.qian@nxp.com>
To: mchehab@kernel.org, shawnguo@kernel.org, robh+dt@kernel.org,
s.hauer@pengutronix.de
Cc: hverkuil-cisco@xs4all.nl, kernel@pengutronix.de,
festevam@gmail.com, linux-imx@nxp.com, aisheng.dong@nxp.com,
linux-media@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 11/13] ARM64: dts: freescale: imx8q: add imx vpu codec entries
Date: Mon, 7 Jun 2021 16:42:58 +0800 [thread overview]
Message-ID: <9695e8d0adee42f3bc6449e32cdb974cdd10757b.1623054584.git.ming.qian@nxp.com> (raw)
In-Reply-To: <cover.1623054584.git.ming.qian@nxp.com>
Add the Video Processing Unit node for IMX8Q SoC.
Signed-off-by: Ming Qian <ming.qian@nxp.com>
Signed-off-by: Shijie Qin <shijie.qin@nxp.com>
Signed-off-by: Zhou Peng <eagle.zhou@nxp.com>
---
.../arm64/boot/dts/freescale/imx8-ss-vpu.dtsi | 76 +++++++++++++++++++
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 22 ++++++
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 27 +++++++
3 files changed, 125 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi
new file mode 100644
index 000000000000..6e9437f11817
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+vpu: vpu-bus@2c000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x2c000000 0x0 0x2c000000 0x2000000>;
+ reg = <0 0x2c000000 0 0x1000000>;
+ power-domains = <&pd IMX_SC_R_VPU>;
+ status = "disabled";
+
+ mu_m0: mailbox@2d000000 {
+ compatible = "fsl,imx6sx-mu";
+ reg = <0x2d000000 0x20000>;
+ interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ power-domains = <&pd IMX_SC_R_VPU_MU_0>;
+ status = "okay";
+ };
+
+ mu1_m0: mailbox@2d020000 {
+ compatible = "fsl,imx6sx-mu";
+ reg = <0x2d020000 0x20000>;
+ interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ power-domains = <&pd IMX_SC_R_VPU_MU_1>;
+ status = "okay";
+ };
+
+ mu2_m0: mailbox@2d040000 {
+ compatible = "fsl,imx6sx-mu";
+ reg = <0x2d040000 0x20000>;
+ interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ power-domains = <&pd IMX_SC_R_VPU_MU_2>;
+ status = "disabled";
+ };
+
+ vpu_core0: vpu_decoder@2d080000 {
+ reg = <0x2d080000 0x10000>;
+ compatible = "nxp,imx8q-vpu-decoder";
+ power-domains = <&pd IMX_SC_R_VPU_DEC_0>;
+ mbox-names = "tx0", "tx1", "rx";
+ mboxes = <&mu_m0 0 0
+ &mu_m0 0 1
+ &mu_m0 1 0>;
+ id = <0>;
+ status = "disabled";
+ };
+ vpu_core1: vpu_encoder@2d090000 {
+ reg = <0x2d090000 0x10000>;
+ compatible = "nxp,imx8q-vpu-encoder";
+ power-domains = <&pd IMX_SC_R_VPU_ENC_0>;
+ mbox-names = "tx0", "tx1", "rx";
+ mboxes = <&mu1_m0 0 0
+ &mu1_m0 0 1
+ &mu1_m0 1 0>;
+ id = <1>;
+ status = "disabled";
+ };
+ vpu_core2: vpu_encoder@2d0a0000 {
+ reg = <0x2d0a0000 0x10000>;
+ compatible = "nxp,imx8q-vpu-encoder";
+ power-domains = <&pd IMX_SC_R_VPU_ENC_1>;
+ mbox-names = "tx0", "tx1", "rx";
+ mboxes = <&mu2_m0 0 0
+ &mu2_m0 0 1
+ &mu2_m0 1 0>;
+ id = <2>;
+ status = "disabled";
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
index 46437d3c7a04..d79eaa0a28ac 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
@@ -196,6 +196,28 @@ &usdhc2 {
status = "okay";
};
+&vpu {
+ compatible = "nxp,imx8qxp-vpu", "simple-bus";
+ memory-region = <&vpu_reserved>;
+ status = "okay";
+};
+
+&vpu_core0 {
+ reg = <0x2d040000 0x10000>;
+ boot-region = <&decoder_boot>;
+ rpc-region = <&decoder_rpc>;
+ print-offset = <0x180000>;
+ status = "okay";
+};
+
+&vpu_core1 {
+ reg = <0x2d050000 0x10000>;
+ boot-region = <&encoder_boot>;
+ rpc-region = <&encoder_rpc>;
+ print-offset = <0x80000>;
+ status = "okay";
+};
+
&iomuxc {
pinctrl_fec1: fec1grp {
fsl,pins = <
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index e46faac1fe71..74900686ec37 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -133,10 +133,34 @@ reserved-memory {
#size-cells = <2>;
ranges;
+ decoder_boot: decoder-boot@84000000 {
+ reg = <0 0x84000000 0 0x2000000>;
+ no-map;
+ };
+
+ encoder_boot: encoder-boot@86000000 {
+ reg = <0 0x86000000 0 0x200000>;
+ no-map;
+ };
+
+ decoder_rpc: decoder-rpc@0x92000000 {
+ reg = <0 0x92000000 0 0x200000>;
+ no-map;
+ };
+
+ encoder_rpc: encoder-rpc@0x92200000 {
+ reg = <0 0x92200000 0 0x100000>;
+ no-map;
+ };
dsp_reserved: dsp@92400000 {
reg = <0 0x92400000 0 0x2000000>;
no-map;
};
+ vpu_reserved: vpu_reserved@94400000 {
+ compatible = "shared-dma-pool";
+ no-map;
+ reg = <0 0x94400000 0 0x800000>;
+ };
};
pmu {
@@ -629,4 +653,7 @@ map0 {
};
};
};
+
+ /* sorted in register address */
+ #include "imx8-ss-vpu.dtsi"
};
--
2.31.1
next prev parent reply other threads:[~2021-06-07 8:44 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-07 8:42 [PATCH v2 00/13] imx8q video decoder/encoder driver Ming Qian
2021-06-07 8:42 ` [PATCH v2 01/13] dt-bindings: media: imx8q: add imx video codec bindings Ming Qian
2021-06-17 0:00 ` Rob Herring
2021-06-17 2:20 ` [EXT] " Ming Qian
2021-06-07 8:42 ` [PATCH v2 02/13] media: v4l: add some definition of v4l2 colorspace/xfer_func/ycbcr_encoding Ming Qian
2021-06-07 8:42 ` [PATCH v2 03/13] media: imx: imx8q: add imx8q vpu device driver Ming Qian
2021-06-07 8:42 ` [PATCH v2 04/13] media: imx: imx8q: add vpu core driver Ming Qian
2021-06-07 8:42 ` [PATCH v2 05/13] media: imx: imx8q: implement vpu core communication based on mailbox Ming Qian
2021-06-07 8:42 ` [PATCH v2 06/13] media: imx: imx8q: add vpu v4l2 m2m support Ming Qian
2021-06-07 8:42 ` [PATCH v2 07/13] media: imx: imx8q: add v4l2 m2m vpu encoder stateful driver Ming Qian
2021-06-07 8:42 ` [PATCH v2 08/13] media: imx: imx8q: add v4l2 m2m vpu decoder " Ming Qian
2021-06-07 8:42 ` [PATCH v2 09/13] media: imx: imx8q: implement windsor encoder rpc interface Ming Qian
2021-06-07 8:42 ` [PATCH v2 10/13] media: imx: imx8q: implement malone decoder " Ming Qian
2021-06-07 8:42 ` Ming Qian [this message]
2021-06-07 8:42 ` [PATCH v2 12/13] firmware: imx: scu-pd: imx8q: add vpu mu resources Ming Qian
2021-06-07 8:43 ` [PATCH v2 13/13] MAINTAINERS: add NXP IMX8Q VPU CODEC V4L2 driver entry Ming Qian
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