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[88.152.144.157]) by smtp.gmail.com with ESMTPSA id m17sm12760100wrz.22.2021.11.29.00.54.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 29 Nov 2021 00:54:41 -0800 (PST) Message-ID: <97431cab-d67d-4bc7-e181-d64534791f03@canonical.com> Date: Mon, 29 Nov 2021 09:54:39 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.3.2 Subject: Re: [PATCH V4 1/2] dt-bindings: riscv: add MMU Standard Extensions support for Svpbmt Content-Language: en-US To: wefu@redhat.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, taiten.peng@canonical.com, aniket.ponkshe@canonical.com, gordan.markus@canonical.com, guoren@linux.alibaba.com, arnd@arndb.de, wens@csie.org, maxime@cerno.tech, dlustig@nvidia.com, gfavor@ventanamicro.com, andrea.mondelli@huawei.com, behrensj@mit.edu, xinhaoqu@huawei.com, huffman@cadence.com, mick@ics.forth.gr, allen.baum@esperantotech.com, jscheid@ventanamicro.com, rtrauben@gmail.com, Anup Patel , Rob Herring , anup.patel@wdc.com, atishp04@gmail.com, palmer@dabbelt.com, guoren@kernel.org, christoph.muellner@vrull.eu, philipp.tomsich@vrull.eu, hch@lst.de, liush@allwinnertech.com, lazyparser@gmail.com, drew@beagleboard.org References: <20211129014007.286478-1-wefu@redhat.com> <20211129014007.286478-2-wefu@redhat.com> From: Heinrich Schuchardt In-Reply-To: <20211129014007.286478-2-wefu@redhat.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 11/29/21 02:40, wefu@redhat.com wrote: > From: Wei Fu > > Previous patch has added svpbmt in arch/riscv and add "riscv,svpmbt" > in the DT mmu node. Update dt-bindings related property here. > > Signed-off-by: Wei Fu > Co-developed-by: Guo Ren > Signed-off-by: Guo Ren > Cc: Anup Patel > Cc: Palmer Dabbelt > Cc: Rob Herring > --- > Documentation/devicetree/bindings/riscv/cpus.yaml | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > index aa5fb64d57eb..9ff9cbdd8a85 100644 > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > @@ -63,6 +63,16 @@ properties: > - riscv,sv48 > - riscv,none > > + mmu: Shouldn't we keep the items be in alphabetic order, i.e. mmu before mmu-type? > + description: > + Describes the CPU's MMU Standard Extensions support. > + These values originate from the RISC-V Privileged > + Specification document, available from > + https://riscv.org/specifications/ > + $ref: '/schemas/types.yaml#/definitions/string' > + enum: > + - riscv,svpmbt The privileged specification has multiple MMU related extensions: Svnapot, Svpbmt, Svinval. Shall they all be modeled in this enum? Best regards Heinrich > + > riscv,isa: > description: > Identifies the specific RISC-V instruction set architecture >