From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9D1ECC43381 for ; Fri, 8 Mar 2019 11:45:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7A03820851 for ; Fri, 8 Mar 2019 11:45:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726418AbfCHLpo (ORCPT ); Fri, 8 Mar 2019 06:45:44 -0500 Received: from mga11.intel.com ([192.55.52.93]:19628 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725789AbfCHLpo (ORCPT ); Fri, 8 Mar 2019 06:45:44 -0500 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 08 Mar 2019 03:45:43 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.58,455,1544515200"; d="scan'208";a="129912677" Received: from ahunter-desktop.fi.intel.com (HELO [10.237.72.56]) ([10.237.72.56]) by fmsmga008.fm.intel.com with ESMTP; 08 Mar 2019 03:45:39 -0800 Subject: Re: [PATCH V1 01/11] mmc: tegra: fix ddr signaling for non-ddr modes To: Sowjanya Komatineni , ulf.hansson@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, riteshh@codeaurora.org Cc: thierry.reding@gmail.com, jonathanh@nvidia.com, anrao@nvidia.com, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org References: <1551504025-3541-1-git-send-email-skomatineni@nvidia.com> From: Adrian Hunter Organization: Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Message-ID: <9787b070-e5e6-3f80-e0f9-1133529be174@intel.com> Date: Fri, 8 Mar 2019 13:44:07 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.5.0 MIME-Version: 1.0 In-Reply-To: <1551504025-3541-1-git-send-email-skomatineni@nvidia.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2/03/19 7:20 AM, Sowjanya Komatineni wrote: > ddr_signaling is set to true for DDR50 and DDR52 modes but is > not set back to false for other modes. This programs incorrect > host clock when mode change happens from DDR52/DDR50 to other > SDR or HS modes like incase of mmc_retune where it switches > from HS400 to HS DDR and then from HS DDR to HS mode and then > to HS200. > > This patch fixes the ddr_signaling to set properly for non DDR > modes. > > Signed-off-by: Sowjanya Komatineni Acked-by: Adrian Hunter > --- > drivers/mmc/host/sdhci-tegra.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c > index 32e62904c0d3..46086dd43bfb 100644 > --- a/drivers/mmc/host/sdhci-tegra.c > +++ b/drivers/mmc/host/sdhci-tegra.c > @@ -779,6 +779,7 @@ static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host, > bool set_dqs_trim = false; > bool do_hs400_dll_cal = false; > > + tegra_host->ddr_signaling = false; > switch (timing) { > case MMC_TIMING_UHS_SDR50: > case MMC_TIMING_UHS_SDR104: >