From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3578EC54FD0 for ; Fri, 24 Apr 2020 15:39:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0D3ED2084D for ; Fri, 24 Apr 2020 15:39:01 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=cerno.tech header.i=@cerno.tech header.b="CvTlpgdn"; dkim=pass (2048-bit key) header.d=messagingengine.com header.i=@messagingengine.com header.b="fmrKc0jh" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728643AbgDXPgo (ORCPT ); Fri, 24 Apr 2020 11:36:44 -0400 Received: from wnew2-smtp.messagingengine.com ([64.147.123.27]:60131 "EHLO wnew2-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728607AbgDXPgi (ORCPT ); Fri, 24 Apr 2020 11:36:38 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailnew.west.internal (Postfix) with ESMTP id DD3F7334; Fri, 24 Apr 2020 11:36:36 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute4.internal (MEProxy); Fri, 24 Apr 2020 11:36:37 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cerno.tech; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=fm2; bh=XgpR8YJnNmnYq WrxoxGzp5tJxm5kpe8QM86vr3IeBP4=; b=CvTlpgdnk+I6xeAkpc11HZ8an/noN v9bYUzMyT33rG+5aX4zp6+L6WSeLiljqVk8C7Z9tOBT30YRNWn1ubiIrSr3PdtpR 5xvJJz51P5HBMKwfXkxx5SzmLwwEeEl8s2QvLOICuc6X1MmAlnxPRaxldqkMz/m0 o1nufB8ZJT5qbu8G32AGWfk9Rjrk5vakoEeNWZJzCZZWqJG+IVSKtMInXV6ntC3O 14Bf8xnr3tCtwXNOolln4IiHdq/1KslFpPAr5yjBQveaVlHi5Lqg6mv9cmqkt7Wx hu81risDkHsn1UfIVbsRclDgBkHacnaY6zAFePG5yjbtyaZ6Y/Z10raCw== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm2; bh=XgpR8YJnNmnYqWrxoxGzp5tJxm5kpe8QM86vr3IeBP4=; b=fmrKc0jh xFyxYi/ovynC1lBCtJgTS7SQ6jcPrt7+lz2uuopqzo9gMXv6Pcck5BHcnpu4aEIs WsSLYS+ZlXtWy07NXmBX1Gqc5gt8XKuBFygv+BCYLrD8XdKXl3+oBJl4L1G+BRC1 ZKq59jVsWOObQAAIjHdyZ/EnHCO73tQ4h8uZ+Naa0dTWJ97VmOwqdAGdcvryAOpY p5xCWLiEtBrCyWnpX9M61KfmzNEj5GIw+djQ54FJeXRPB8eYSOEFdGt/2/UCUyGX JBcNlNlVQu7q96bUkuWXL0UgpTyzcAw3KuDLVnPWcnat5dhKbB+mY++Qf66gZgfH 76vVHqNQmCZq6A== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgeduhedrhedugdekiecutefuodetggdotefrodftvf curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu uegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenuc fjughrpefhvffufffkofgjfhgggfestdekredtredttdenucfhrhhomhepofgrgihimhgv ucftihhprghrugcuoehmrgigihhmvgestggvrhhnohdrthgvtghhqeenucfkphepledtrd ekledrieekrdejieenucevlhhushhtvghrufhiiigvpeegjeenucfrrghrrghmpehmrghi lhhfrhhomhepmhgrgihimhgvsegtvghrnhhordhtvggthh X-ME-Proxy: Received: from localhost (lfbn-tou-1-1502-76.w90-89.abo.wanadoo.fr [90.89.68.76]) by mail.messagingengine.com (Postfix) with ESMTPA id 2534B3065D87; Fri, 24 Apr 2020 11:36:36 -0400 (EDT) From: Maxime Ripard To: Nicolas Saenz Julienne , Eric Anholt Cc: dri-devel@lists.freedesktop.org, linux-rpi-kernel@lists.infradead.org, bcm-kernel-feedback-list@broadcom.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Dave Stevenson , Tim Gover , Phil Elwell , Maxime Ripard Subject: [PATCH v2 53/91] drm/vc4: crtc: Add FIFO depth to vc4_crtc_data Date: Fri, 24 Apr 2020 17:34:34 +0200 Message-Id: <97f6f0dfa74264edf5bcb9c12b5424f5b8739021.1587742492.git-series.maxime@cerno.tech> X-Mailer: git-send-email 2.26.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Not all pixelvalve FIFOs in vc5 have the same depth, so we need to add that to our vc4_crtc_data structure to be able to compute the fill level properly later on. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/vc4/vc4_crtc.c | 19 ++++++++++++++++--- drivers/gpu/drm/vc4/vc4_drv.h | 3 +++ 2 files changed, 19 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c index ea55d4ca2766..e9d71153c6c6 100644 --- a/drivers/gpu/drm/vc4/vc4_crtc.c +++ b/drivers/gpu/drm/vc4/vc4_crtc.c @@ -251,10 +251,20 @@ vc4_crtc_update_gamma_lut(struct drm_crtc *crtc) vc4_crtc_lut_load(crtc); } -static u32 vc4_get_fifo_full_level(u32 format) +static u32 vc4_get_fifo_full_level(struct vc4_crtc *vc4_crtc, u32 format) { - static const u32 fifo_len_bytes = 64; + u32 fifo_len_bytes = vc4_crtc->data->fifo_depth; + /* + * Pixels are pulled from the HVS if the number of bytes is + * lower than the FIFO full level. + * + * The latency of the pixel fetch mechanism is 6 pixels, so we + * need to convert those 6 pixels in bytes, depending on the + * format, and then subtract that from the length of the FIFO + * to make sure we never end up in a situation where the FIFO + * is full. + */ switch (format) { case PV_CONTROL_FORMAT_DSIV_16: case PV_CONTROL_FORMAT_DSIC_16: @@ -369,7 +379,7 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc) CRTC_WRITE(PV_CONTROL, VC4_SET_FIELD(format, PV_CONTROL_FORMAT) | - VC4_SET_FIELD(vc4_get_fifo_full_level(format), + VC4_SET_FIELD(vc4_get_fifo_full_level(vc4_crtc, format), PV_CONTROL_FIFO_LEVEL) | VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) | PV_CONTROL_CLR_AT_START | @@ -1068,6 +1078,7 @@ static const struct vc4_crtc_data bcm2835_pv0_data = { .hvs_available_channels = BIT(0), .hvs_output = 0, .debugfs_name = "crtc0_regs", + .fifo_depth = 64, .pixels_per_clock = 1, .encoder_types = { [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0, @@ -1079,6 +1090,7 @@ static const struct vc4_crtc_data bcm2835_pv1_data = { .hvs_available_channels = BIT(2), .hvs_output = 2, .debugfs_name = "crtc1_regs", + .fifo_depth = 64, .pixels_per_clock = 1, .encoder_types = { [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1, @@ -1090,6 +1102,7 @@ static const struct vc4_crtc_data bcm2835_pv2_data = { .hvs_available_channels = BIT(1), .hvs_output = 1, .debugfs_name = "crtc2_regs", + .fifo_depth = 64, .pixels_per_clock = 1, .encoder_types = { [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI, diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h index 6468c6df20b6..1ac27f8ec725 100644 --- a/drivers/gpu/drm/vc4/vc4_drv.h +++ b/drivers/gpu/drm/vc4/vc4_drv.h @@ -450,6 +450,9 @@ to_vc4_encoder(struct drm_encoder *encoder) } struct vc4_crtc_data { + /* Depth of the PixelValve FIFO in bytes */ + unsigned int fifo_depth; + /* Which channels of the HVS can the output source from */ unsigned int hvs_available_channels; -- git-series 0.9.1