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From: Sowjanya Komatineni <skomatineni@nvidia.com>
To: Dmitry Osipenko <digetx@gmail.com>, <thierry.reding@gmail.com>,
	<jonathanh@nvidia.com>, <frankc@nvidia.com>, <hverkuil@xs4all.nl>,
	<sakari.ailus@iki.fi>, <helen.koike@collabora.com>
Cc: <sboyd@kernel.org>, <linux-media@vger.kernel.org>,
	<devicetree@vger.kernel.org>, <linux-clk@vger.kernel.org>,
	<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [RFC PATCH v6 6/9] media: tegra: Add Tegra210 Video input driver
Date: Mon, 6 Apr 2020 08:35:43 -0700	[thread overview]
Message-ID: <9b8cf37b-d2ad-9df2-aad8-216c2c954e69@nvidia.com> (raw)
In-Reply-To: <38d921a7-5cdf-8d0a-2772-4399dd1a96a0@gmail.com>


On 4/5/20 1:35 PM, Dmitry Osipenko wrote:
> External email: Use caution opening links or attachments
>
>
> 04.04.2020 04:25, Sowjanya Komatineni пишет:
> ...
>> +static int tegra_channel_capture_frame(struct tegra_vi_channel *chan,
>> +                                    struct tegra_channel_buffer *buf)
>> +{
>> +     int err = 0;
>> +     u32 thresh, value, frame_start, mw_ack_done;
>> +     int bytes_per_line = chan->format.bytesperline;
>> +
>> +     /* program buffer address by using surface 0 */
>> +     vi_csi_write(chan, TEGRA_VI_CSI_SURFACE0_OFFSET_MSB,
>> +                  (u64)buf->addr >> 32);
>> +     vi_csi_write(chan, TEGRA_VI_CSI_SURFACE0_OFFSET_LSB, buf->addr);
>> +     vi_csi_write(chan, TEGRA_VI_CSI_SURFACE0_STRIDE, bytes_per_line);
>> +
>> +     /*
>> +      * Tegra VI block interacts with host1x syncpt for synchronizing
>> +      * programmed condition of capture state and hardware operation.
>> +      * Frame start and Memory write acknowledge syncpts has their own
>> +      * FIFO of depth 2.
>> +      *
>> +      * Syncpoint trigger conditions set through VI_INCR_SYNCPT register
>> +      * are added to HW syncpt FIFO and when the HW triggers, syncpt
>> +      * condition is removed from the FIFO and counter at syncpoint index
>> +      * will be incremented by the hardware and software can wait for
>> +      * counter to reach threshold to synchronize capturing frame with the
>> +      * hardware capture events.
>> +      */
>> +
>> +     /* increase channel syncpoint threshold for FRAME_START */
>> +     thresh = host1x_syncpt_incr_max(chan->frame_start_sp, 1);
>> +
>> +     /* Program FRAME_START trigger condition syncpt request */
>> +     frame_start = VI_CSI_PP_FRAME_START(chan->portno);
>> +     value = VI_CFG_VI_INCR_SYNCPT_COND(frame_start) |
>> +             host1x_syncpt_id(chan->frame_start_sp);
>> +     tegra_vi_write(chan, TEGRA_VI_CFG_VI_INCR_SYNCPT, value);
>> +
>> +     /* increase channel syncpoint threshold for MW_ACK_DONE */
>> +     buf->mw_ack_sp_thresh = host1x_syncpt_incr_max(chan->mw_ack_sp, 1);
>> +
>> +     /* Program MW_ACK_DONE trigger condition syncpt request */
>> +     mw_ack_done = VI_CSI_MW_ACK_DONE(chan->portno);
>> +     value = VI_CFG_VI_INCR_SYNCPT_COND(mw_ack_done) |
>> +             host1x_syncpt_id(chan->mw_ack_sp);
>> +     tegra_vi_write(chan, TEGRA_VI_CFG_VI_INCR_SYNCPT, value);
>> +
>> +     /* enable single shot capture */
>> +     vi_csi_write(chan, TEGRA_VI_CSI_SINGLE_SHOT, SINGLE_SHOT_CAPTURE);
>> +     chan->capture_reqs++;
>> +
>> +     /* wait for syncpt counter to reach frame start event threshold */
>> +     err = host1x_syncpt_wait(chan->frame_start_sp, thresh,
>> +                              TEGRA_VI_SYNCPT_WAIT_TIMEOUT, &value);
>> +     if (err) {
>> +             dev_err(&chan->video.dev,
>> +                     "frame start syncpt timeout: %d\n", err);
>> +             /* increment syncpoint counter for timedout events */
>> +             host1x_syncpt_incr(chan->frame_start_sp);
> Why incrementing is done while hardware is still active?
>
> The sync point's state needs to be completely reset after resetting
> hardware. But I don't think that the current upstream host1x driver
> supports doing that, it's one of the known-long-standing problems of the
> host1x driver.
>
> At least the sp->max_val incrementing should be done based on the actual
> syncpoint value and this should be done after resetting hardware.

upstream host1x driver don't have API to reset or to equalize max value 
with min/load value.

So to synchronize missed event, incrementing HW syncpt counter.

This should not impact as we increment this in case of missed events only.

>> +             spin_lock(&chan->sp_incr_lock);
>> +             host1x_syncpt_incr(chan->mw_ack_sp);
>> +             spin_unlock(&chan->sp_incr_lock);
>> +             /* clear errors and recover */
>> +             tegra_channel_capture_error_recover(chan);
>> +             release_buffer(chan, buf, VB2_BUF_STATE_ERROR);
>> +             return err;
>> +     }

  reply	other threads:[~2020-04-06 15:35 UTC|newest]

Thread overview: 80+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-04-04  1:24 [RFC PATCH v6 0/9] Add Tegra driver for video capture Sowjanya Komatineni
2020-04-04  1:24 ` [RFC PATCH v6 1/9] arm64: tegra: Fix sor powergate clocks and reset Sowjanya Komatineni
2020-04-04  1:25 ` [RFC PATCH v6 2/9] arm64: tegra: Add reset-cells to mc Sowjanya Komatineni
2020-04-04  1:25 ` [RFC PATCH v6 3/9] dt-bindings: clock: tegra: Add clk id for CSI TPG clock Sowjanya Komatineni
2020-04-14 18:12   ` Rob Herring
2020-04-04  1:25 ` [RFC PATCH v6 4/9] clk: tegra: Add Tegra210 CSI TPG clock gate Sowjanya Komatineni
2020-04-04  1:25 ` [RFC PATCH v6 5/9] dt-binding: tegra: Add VI and CSI bindings Sowjanya Komatineni
2020-04-14 18:14   ` Rob Herring
2020-04-04  1:25 ` [RFC PATCH v6 6/9] media: tegra: Add Tegra210 Video input driver Sowjanya Komatineni
2020-04-05 19:37   ` Dmitry Osipenko
2020-04-06 18:58     ` Sowjanya Komatineni
2020-04-05 19:45   ` Dmitry Osipenko
2020-04-05 19:57     ` Dmitry Osipenko
2020-04-05 19:51   ` Dmitry Osipenko
2020-04-05 20:35   ` Dmitry Osipenko
2020-04-06 15:35     ` Sowjanya Komatineni [this message]
2020-04-06 16:05       ` Dmitry Osipenko
2020-04-06 16:12         ` Sowjanya Komatineni
2020-04-06 16:29           ` Dmitry Osipenko
2020-04-06 16:37             ` Sowjanya Komatineni
2020-04-06 17:02               ` Sowjanya Komatineni
2020-04-06 19:53                 ` Dmitry Osipenko
2020-04-06 20:05                   ` Sowjanya Komatineni
2020-04-06 20:28                     ` Dmitry Osipenko
2020-04-06 20:30                       ` Sowjanya Komatineni
2020-04-05 20:54   ` Dmitry Osipenko
2020-04-05 21:11   ` Dmitry Osipenko
2020-04-06 15:41     ` Sowjanya Komatineni
2020-04-06 16:11       ` Dmitry Osipenko
2020-04-07 19:05         ` Sowjanya Komatineni
2020-04-06 19:48   ` Dmitry Osipenko
2020-04-06 20:00     ` Sowjanya Komatineni
2020-04-06 20:02   ` Dmitry Osipenko
2020-04-06 20:20     ` Sowjanya Komatineni
2020-04-06 20:37       ` Dmitry Osipenko
2020-04-06 20:38         ` Sowjanya Komatineni
2020-04-06 20:43           ` Sowjanya Komatineni
2020-04-06 20:54           ` Dmitry Osipenko
2020-04-06 21:18             ` Sowjanya Komatineni
2020-04-06 20:45   ` Dmitry Osipenko
2020-04-06 20:50     ` Sowjanya Komatineni
2020-04-06 20:53       ` Dmitry Osipenko
2020-04-06 20:55         ` Sowjanya Komatineni
2020-04-06 20:56           ` Dmitry Osipenko
2020-04-06 21:02             ` Sowjanya Komatineni
2020-04-06 21:11               ` Dmitry Osipenko
2020-04-06 21:15                 ` Sowjanya Komatineni
2020-04-06 21:39                   ` Sowjanya Komatineni
2020-04-06 22:00                     ` Sowjanya Komatineni
2020-04-06 22:07                       ` Sowjanya Komatineni
2020-04-06 23:18                         ` Dmitry Osipenko
2020-04-06 23:48                           ` Sowjanya Komatineni
2020-04-06 23:50                             ` Sowjanya Komatineni
2020-04-07 21:08                             ` Sowjanya Komatineni
2020-04-07 22:08                               ` Dmitry Osipenko
2020-04-07 22:14                                 ` Dmitry Osipenko
2020-04-07 22:22                                 ` Sowjanya Komatineni
2020-04-07 23:12                                   ` Dmitry Osipenko
     [not found]                                     ` <1a31cd60-739f-0660-1c45-31487d2f2128@nvidia.com>
2020-04-07 23:38                                       ` Sowjanya Komatineni
2020-04-07 23:56                                         ` Sowjanya Komatineni
2020-04-07 23:57                                         ` Sowjanya Komatineni
2020-04-07 23:59                                         ` Sowjanya Komatineni
2020-04-08  0:00                                           ` Sowjanya Komatineni
2020-04-08 14:21                                             ` Dmitry Osipenko
2020-04-08 17:45                                               ` Sowjanya Komatineni
2020-04-08 18:58                                                 ` Sowjanya Komatineni
2020-04-08 19:38                                                   ` Sowjanya Komatineni
2020-04-09  3:38                                                     ` Sowjanya Komatineni
2020-04-09 14:50                                                       ` Dmitry Osipenko
2020-04-09 18:28                                                         ` Sowjanya Komatineni
2020-04-10 18:47                                                           ` Dmitry Osipenko
2020-04-10 18:59                                                             ` Sowjanya Komatineni
2020-04-10 19:45                                                               ` Dmitry Osipenko
2020-04-07 19:39   ` Dmitry Osipenko
2020-04-07 19:42     ` Sowjanya Komatineni
2020-04-10 19:47   ` Dmitry Osipenko
2020-04-04  1:25 ` [RFC PATCH v6 7/9] MAINTAINERS: Add Tegra Video driver section Sowjanya Komatineni
2020-04-04  1:25 ` [RFC PATCH v6 8/9] dt-bindings: reset: Add ID for Tegra210 VI reset Sowjanya Komatineni
2020-04-14 18:14   ` Rob Herring
2020-04-04  1:25 ` [RFC PATCH v6 9/9] arm64: tegra: Add Tegra VI CSI support in device tree Sowjanya Komatineni

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