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[46.138.48.94]) by smtp.googlemail.com with ESMTPSA id w26sm1021100ljh.18.2021.10.16.08.36.36 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 16 Oct 2021 08:36:37 -0700 (PDT) Subject: Re: [PATCH v13 11/35] drm/tegra: dc: Support OPP and SoC core voltage scaling To: Ulf Hansson , Viresh Kumar Cc: Thierry Reding , Jonathan Hunter , Stephen Boyd , Peter De Schrijver , Mikko Perttunen , Peter Chen , Lee Jones , =?UTF-8?Q?Uwe_Kleine-K=c3=b6nig?= , Nishanth Menon , Adrian Hunter , Michael Turquette , Linux Kernel Mailing List , linux-tegra , Linux PM , Linux USB List , linux-staging@lists.linux.dev, linux-pwm@vger.kernel.org, linux-mmc , dri-devel , DTML , linux-clk , Mark Brown , Vignesh Raghavendra , Richard Weinberger , Miquel Raynal , Lucas Stach , Stefan Agner , Mauro Carvalho Chehab , David Heidelberg References: <20210926224058.1252-1-digetx@gmail.com> <20210926224058.1252-12-digetx@gmail.com> From: Dmitry Osipenko Message-ID: <9bb95684-de30-697a-139c-1e3e54dade2a@gmail.com> Date: Sat, 16 Oct 2021 18:36:35 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 01.10.2021 16:27, Ulf Hansson пишет: > On Mon, 27 Sept 2021 at 00:42, Dmitry Osipenko wrote: >> >> Add OPP and SoC core voltage scaling support to the display controller >> driver. This is required for enabling system-wide DVFS on pre-Tegra186 >> SoCs. >> >> Tested-by: Peter Geis # Ouya T30 >> Tested-by: Paul Fertser # PAZ00 T20 >> Tested-by: Nicolas Chauvet # PAZ00 T20 and TK1 T124 >> Tested-by: Matt Merhar # Ouya T30 >> Signed-off-by: Dmitry Osipenko >> --- >> drivers/gpu/drm/tegra/dc.c | 74 ++++++++++++++++++++++++++++++++++++++ >> drivers/gpu/drm/tegra/dc.h | 2 ++ >> 2 files changed, 76 insertions(+) >> >> diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c >> index a29d64f87563..d4047a14e2b6 100644 >> --- a/drivers/gpu/drm/tegra/dc.c >> +++ b/drivers/gpu/drm/tegra/dc.c >> @@ -11,9 +11,12 @@ >> #include >> #include >> #include >> +#include >> +#include >> #include >> #include >> >> +#include >> #include >> >> #include >> @@ -1762,6 +1765,47 @@ int tegra_dc_state_setup_clock(struct tegra_dc *dc, >> return 0; >> } >> >> +static void tegra_dc_update_voltage_state(struct tegra_dc *dc, >> + struct tegra_dc_state *state) >> +{ >> + unsigned long rate, pstate; >> + struct dev_pm_opp *opp; >> + int err; >> + >> + if (!dc->has_opp_table) >> + return; >> + >> + /* calculate actual pixel clock rate which depends on internal divider */ >> + rate = DIV_ROUND_UP(clk_get_rate(dc->clk) * 2, state->div + 2); >> + >> + /* find suitable OPP for the rate */ >> + opp = dev_pm_opp_find_freq_ceil(dc->dev, &rate); >> + >> + if (opp == ERR_PTR(-ERANGE)) >> + opp = dev_pm_opp_find_freq_floor(dc->dev, &rate); >> + >> + if (IS_ERR(opp)) { >> + dev_err(dc->dev, "failed to find OPP for %luHz: %pe\n", >> + rate, opp); >> + return; >> + } >> + >> + pstate = dev_pm_opp_get_required_pstate(opp, 0); >> + dev_pm_opp_put(opp); >> + >> + /* >> + * The minimum core voltage depends on the pixel clock rate (which >> + * depends on internal clock divider of the CRTC) and not on the >> + * rate of the display controller clock. This is why we're not using >> + * dev_pm_opp_set_rate() API and instead controlling the power domain >> + * directly. >> + */ >> + err = dev_pm_genpd_set_performance_state(dc->dev, pstate); >> + if (err) >> + dev_err(dc->dev, "failed to set power domain state to %lu: %d\n", >> + pstate, err); > > Yeah, the above code looks very similar to the code I pointed to in > patch6. Perhaps we need to discuss with Viresh, whether it makes sense > to fold in a patch adding an opp helper function after all, to avoid > the open coding. > > Viresh? I'll keep it open-coded for now. This code is specific to Tegra because normally ceil error shouldn't fall back to the floor, but for Tegra it's expected to happen and it's a normal condition.