From: Alexey Budankov <alexey.budankov@linux.intel.com>
To: Peter Zijlstra <peterz@infradead.org>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>,
Ingo Molnar <mingo@redhat.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Jiri Olsa <jolsa@redhat.com>, Namhyung Kim <namhyung@kernel.org>,
Andi Kleen <ak@linux.intel.com>,
Kan Liang <kan.liang@linux.intel.com>,
Stephane Eranian <eranian@google.com>,
Ian Rogers <irogers@google.com>, Song Liu <songliubraving@fb.com>,
linux-kernel <linux-kernel@vger.kernel.org>
Subject: [PATCH v5 4/4] perf/core,x86: synchronize PMU task contexts on optimized context switches
Date: Wed, 23 Oct 2019 10:13:56 +0300 [thread overview]
Message-ID: <9c6445a9-bdba-ef03-3859-f1f91198f27a@linux.intel.com> (raw)
In-Reply-To: <f8d5a880-38e5-29f4-9e6a-848f70a67988@linux.intel.com>
Install Intel specific PMU task context synchronization adapter and
extend optimized context switch path with PMU specific task context
synchronization to fix LBR callstack virtualization on context switches.
Signed-off-by: Alexey Budankov <alexey.budankov@linux.intel.com>
---
arch/x86/events/intel/core.c | 7 +++++++
kernel/events/core.c | 13 ++++++++++++-
2 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index bbf6588d47ee..dc64b16e6b71 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -3820,6 +3820,12 @@ static void intel_pmu_sched_task(struct perf_event_context *ctx,
intel_pmu_lbr_sched_task(ctx, sched_in);
}
+static void intel_pmu_swap_task_ctx(struct perf_event_context *prev,
+ struct perf_event_context *next)
+{
+ intel_pmu_lbr_swap_task_ctx(prev, next);
+}
+
static int intel_pmu_check_period(struct perf_event *event, u64 value)
{
return intel_pmu_has_bts_period(event, value) ? -EINVAL : 0;
@@ -3955,6 +3961,7 @@ static __initconst const struct x86_pmu intel_pmu = {
.guest_get_msrs = intel_guest_get_msrs,
.sched_task = intel_pmu_sched_task,
+ .swap_task_ctx = intel_pmu_swap_task_ctx,
.check_period = intel_pmu_check_period,
diff --git a/kernel/events/core.c b/kernel/events/core.c
index f9a5d4356562..ed31aa849161 100644
--- a/kernel/events/core.c
+++ b/kernel/events/core.c
@@ -3204,10 +3204,21 @@ static void perf_event_context_sched_out(struct task_struct *task, int ctxn,
raw_spin_lock(&ctx->lock);
raw_spin_lock_nested(&next_ctx->lock, SINGLE_DEPTH_NESTING);
if (context_equiv(ctx, next_ctx)) {
+ struct pmu *pmu = ctx->pmu;
+
WRITE_ONCE(ctx->task, next);
WRITE_ONCE(next_ctx->task, task);
- swap(ctx->task_ctx_data, next_ctx->task_ctx_data);
+ /*
+ * PMU specific parts of task perf context can require
+ * additional synchronization. As an example of such
+ * synchronization see implementation details of Intel
+ * LBR call stack data profiling;
+ */
+ if (pmu->swap_task_ctx)
+ pmu->swap_task_ctx(ctx, next_ctx);
+ else
+ swap(ctx->task_ctx_data, next_ctx->task_ctx_data);
/*
* RCU_INIT_POINTER here is safe because we've not
--
2.20.1
next prev parent reply other threads:[~2019-10-23 7:14 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-23 7:05 [PATCH v5 0/4] perf/core: fix restoring of Intel LBR call stack on a context switch Alexey Budankov
2019-10-23 7:11 ` [PATCH v5 1/4] perf/core,x86: introduce swap_task_ctx() method at struct pmu Alexey Budankov
2019-10-28 12:43 ` [tip: perf/core] perf/core, perf/x86: Introduce swap_task_ctx() method at 'struct pmu' tip-bot2 for Alexey Budankov
2019-10-23 7:11 ` [PATCH v5 2/4] perf/x86: install platform specific swap_task_ctx adapter Alexey Budankov
2019-10-28 12:43 ` [tip: perf/core] perf/x86: Install platform specific ->swap_task_ctx() adapter tip-bot2 for Alexey Budankov
2019-10-23 7:12 ` [PATCH v5 3/4] perf/x86/intel: implement LBR callstacks context synchronization Alexey Budankov
2019-10-28 12:43 ` [tip: perf/core] perf/x86/intel: Implement LBR callstack " tip-bot2 for Alexey Budankov
2019-10-23 7:13 ` Alexey Budankov [this message]
2019-10-28 12:43 ` [tip: perf/core] perf/x86: Synchronize PMU task contexts on optimized context switches tip-bot2 for Alexey Budankov
2019-10-25 8:35 [PATCH v5 0/4] perf/core: fix restoring of Intel LBR call stack on a context switch Alexey Budankov
2019-10-25 9:00 ` [PATCH v5 4/4] perf/core,x86: synchronize PMU task contexts on optimized context switches Alexey Budankov
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