* [PATCH v11 00/10] Mediatek MT8183 scpsys support
@ 2019-12-20 3:45 Weiyi Lu
2019-12-20 3:45 ` [PATCH v11 01/10] dt-bindings: mediatek: Add property to mt8183 smi-common Weiyi Lu
` (10 more replies)
0 siblings, 11 replies; 33+ messages in thread
From: Weiyi Lu @ 2019-12-20 3:45 UTC (permalink / raw)
To: Nicolas Boichat, Matthias Brugger, Rob Herring, Sascha Hauer
Cc: James Liao, Fan Chen, linux-arm-kernel, linux-kernel,
linux-mediatek, srv_heupstream, Weiyi Lu
This series is based on v5.5-rc1
changes since v10:
- squash PATCH 04 and PATCH 06 in v9 into its previous patch
- add "ignore_clr_ack" for multiple step bus protection control to have a clean definition of power domain data
- keep the mask register bit definitions and do the same for MT8183
changes since v9:
- add new PATCH 04 and PATCH 06 to replace by new method for all compatibles
- add new PATCH 07 to remove infracfg misc driver
- minor coding sytle fix
changes since v7:
- reword in binding document [PATCH 02/14]
- fix error return checking bug in subsys clock control [PATCH 10/14]
- add power domains properity to mfgcfg patch [PATCH 14/14] from
https://patchwork.kernel.org/patch/11126199/
changes since v6:
- remove the patch of SPDX license identifier because it's already fixed
changes since v5:
- fix documentation in [PATCH 04/14]
- remove useless variable checking and reuse API of clock control in [PATCH 06/14]
- coding style fix of bus protection control in [PATCH 08/14]
- fix naming of new added data in [PATCH 09/14]
- small refactor of multiple step bus protection control in [PATCH 10/14]
changes since v4:
- add property to mt8183 smi-common
- seperate refactor patches and new add function
- add power controller device node
Weiyi Lu (10):
dt-bindings: mediatek: Add property to mt8183 smi-common
dt-bindings: soc: Add MT8183 power dt-bindings
soc: mediatek: Add basic_clk_name to scp_power_data
soc: mediatek: Add multiple step bus protection control
soc: mediatek: Remove infracfg misc driver support
soc: mediatek: Add subsys clock control for bus protection
soc: mediatek: Add extra sram control
soc: mediatek: Add MT8183 scpsys support
arm64: dts: Add power controller device node of MT8183
arm64: dts: Add power-domains properity to mfgcfg
.../memory-controllers/mediatek,smi-common.txt | 2 +-
.../devicetree/bindings/soc/mediatek/scpsys.txt | 20 +-
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 63 +++
drivers/soc/mediatek/Kconfig | 10 -
drivers/soc/mediatek/Makefile | 3 +-
drivers/soc/mediatek/mtk-infracfg.c | 79 ---
drivers/soc/mediatek/mtk-scpsys-ext.c | 101 ++++
drivers/soc/mediatek/mtk-scpsys.c | 578 +++++++++++++++------
drivers/soc/mediatek/scpsys-ext.h | 95 ++++
include/dt-bindings/power/mt8183-power.h | 26 +
include/linux/soc/mediatek/infracfg.h | 39 --
11 files changed, 736 insertions(+), 280 deletions(-)
delete mode 100644 drivers/soc/mediatek/mtk-infracfg.c
create mode 100644 drivers/soc/mediatek/mtk-scpsys-ext.c
create mode 100644 drivers/soc/mediatek/scpsys-ext.h
create mode 100644 include/dt-bindings/power/mt8183-power.h
delete mode 100644 include/linux/soc/mediatek/infracfg.h
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH v11 01/10] dt-bindings: mediatek: Add property to mt8183 smi-common
2019-12-20 3:45 [PATCH v11 00/10] Mediatek MT8183 scpsys support Weiyi Lu
@ 2019-12-20 3:45 ` Weiyi Lu
2020-01-15 5:45 ` Weiyi Lu
2019-12-20 3:45 ` [PATCH v11 02/10] dt-bindings: soc: Add MT8183 power dt-bindings Weiyi Lu
` (9 subsequent siblings)
10 siblings, 1 reply; 33+ messages in thread
From: Weiyi Lu @ 2019-12-20 3:45 UTC (permalink / raw)
To: Nicolas Boichat, Matthias Brugger, Rob Herring, Sascha Hauer
Cc: James Liao, Fan Chen, linux-arm-kernel, linux-kernel,
linux-mediatek, srv_heupstream, Weiyi Lu
For scpsys driver using regmap based syscon driver API.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
.../devicetree/bindings/memory-controllers/mediatek,smi-common.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
index b478ade..01744ec 100644
--- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
+++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
@@ -20,7 +20,7 @@ Required properties:
"mediatek,mt2712-smi-common"
"mediatek,mt7623-smi-common", "mediatek,mt2701-smi-common"
"mediatek,mt8173-smi-common"
- "mediatek,mt8183-smi-common"
+ "mediatek,mt8183-smi-common", "syscon"
- reg : the register and size of the SMI block.
- power-domains : a phandle to the power domain of this local arbiter.
- clocks : Must contain an entry for each entry in clock-names.
--
1.8.1.1.dirty
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH v11 02/10] dt-bindings: soc: Add MT8183 power dt-bindings
2019-12-20 3:45 [PATCH v11 00/10] Mediatek MT8183 scpsys support Weiyi Lu
2019-12-20 3:45 ` [PATCH v11 01/10] dt-bindings: mediatek: Add property to mt8183 smi-common Weiyi Lu
@ 2019-12-20 3:45 ` Weiyi Lu
2019-12-20 3:45 ` [PATCH v11 03/10] soc: mediatek: Add basic_clk_name to scp_power_data Weiyi Lu
` (8 subsequent siblings)
10 siblings, 0 replies; 33+ messages in thread
From: Weiyi Lu @ 2019-12-20 3:45 UTC (permalink / raw)
To: Nicolas Boichat, Matthias Brugger, Rob Herring, Sascha Hauer
Cc: James Liao, Fan Chen, linux-arm-kernel, linux-kernel,
linux-mediatek, srv_heupstream, Weiyi Lu
Add power dt-bindings of MT8183 and introduces "BASIC" and
"SUBSYS" clock types in binding document.
The "BASIC" type is compatible to the original power control with
clock name [a-z]+[0-9]*, e.g. mm, vpu1.
The "SUBSYS" type is used for bus protection control with clock
name [a-z]+-[0-9]+, e.g. isp-0, cam-1.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
.../devicetree/bindings/soc/mediatek/scpsys.txt | 20 ++++++++++++++---
include/dt-bindings/power/mt8183-power.h | 26 ++++++++++++++++++++++
2 files changed, 43 insertions(+), 3 deletions(-)
create mode 100644 include/dt-bindings/power/mt8183-power.h
diff --git a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
index 8f469d8..8e0e1ed 100644
--- a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
+++ b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
@@ -14,6 +14,7 @@ power/power-domain.yaml. It provides the power domains defined in
- include/dt-bindings/power/mt2701-power.h
- include/dt-bindings/power/mt2712-power.h
- include/dt-bindings/power/mt7622-power.h
+- include/dt-bindings/power/mt8183-power.h
Required properties:
- compatible: Should be one of:
@@ -25,18 +26,31 @@ Required properties:
- "mediatek,mt7623a-scpsys": For MT7623A SoC
- "mediatek,mt7629-scpsys", "mediatek,mt7622-scpsys": For MT7629 SoC
- "mediatek,mt8173-scpsys"
+ - "mediatek,mt8183-scpsys"
- #power-domain-cells: Must be 1
- reg: Address range of the SCPSYS unit
- infracfg: must contain a phandle to the infracfg controller
-- clock, clock-names: clocks according to the common clock binding.
- These are clocks which hardware needs to be
- enabled before enabling certain power domains.
+- clock, clock-names: Clocks according to the common clock binding.
+ Some SoCs have to groups of clocks.
+ BASIC clocks need to be enabled before enabling the
+ corresponding power domain.
+ SUBSYS clocks need to be enabled before releasing the
+ bus protection.
Required clocks for MT2701 or MT7623: "mm", "mfg", "ethif"
Required clocks for MT2712: "mm", "mfg", "venc", "jpgdec", "audio", "vdec"
Required clocks for MT6797: "mm", "mfg", "vdec"
Required clocks for MT7622 or MT7629: "hif_sel"
Required clocks for MT7623A: "ethif"
Required clocks for MT8173: "mm", "mfg", "venc", "venc_lt"
+ Required clocks for MT8183: BASIC: "audio", "mfg", "mm", "cam", "isp",
+ "vpu", "vpu1", "vpu2", "vpu3"
+ SUBSYS: "mm-0", "mm-1", "mm-2", "mm-3",
+ "mm-4", "mm-5", "mm-6", "mm-7",
+ "mm-8", "mm-9", "isp-0", "isp-1",
+ "cam-0", "cam-1", "cam-2", "cam-3",
+ "cam-4", "cam-5", "cam-6", "vpu-0",
+ "vpu-1", "vpu-2", "vpu-3", "vpu-4",
+ "vpu-5"
Optional properties:
- vdec-supply: Power supply for the vdec power domain
diff --git a/include/dt-bindings/power/mt8183-power.h b/include/dt-bindings/power/mt8183-power.h
new file mode 100644
index 0000000..5c0c8c7
--- /dev/null
+++ b/include/dt-bindings/power/mt8183-power.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Weiyi Lu <weiyi.lu@mediatek.com>
+ */
+
+#ifndef _DT_BINDINGS_POWER_MT8183_POWER_H
+#define _DT_BINDINGS_POWER_MT8183_POWER_H
+
+#define MT8183_POWER_DOMAIN_AUDIO 0
+#define MT8183_POWER_DOMAIN_CONN 1
+#define MT8183_POWER_DOMAIN_MFG_ASYNC 2
+#define MT8183_POWER_DOMAIN_MFG 3
+#define MT8183_POWER_DOMAIN_MFG_CORE0 4
+#define MT8183_POWER_DOMAIN_MFG_CORE1 5
+#define MT8183_POWER_DOMAIN_MFG_2D 6
+#define MT8183_POWER_DOMAIN_DISP 7
+#define MT8183_POWER_DOMAIN_CAM 8
+#define MT8183_POWER_DOMAIN_ISP 9
+#define MT8183_POWER_DOMAIN_VDEC 10
+#define MT8183_POWER_DOMAIN_VENC 11
+#define MT8183_POWER_DOMAIN_VPU_TOP 12
+#define MT8183_POWER_DOMAIN_VPU_CORE0 13
+#define MT8183_POWER_DOMAIN_VPU_CORE1 14
+
+#endif /* _DT_BINDINGS_POWER_MT8183_POWER_H */
--
1.8.1.1.dirty
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH v11 03/10] soc: mediatek: Add basic_clk_name to scp_power_data
2019-12-20 3:45 [PATCH v11 00/10] Mediatek MT8183 scpsys support Weiyi Lu
2019-12-20 3:45 ` [PATCH v11 01/10] dt-bindings: mediatek: Add property to mt8183 smi-common Weiyi Lu
2019-12-20 3:45 ` [PATCH v11 02/10] dt-bindings: soc: Add MT8183 power dt-bindings Weiyi Lu
@ 2019-12-20 3:45 ` Weiyi Lu
2019-12-20 4:05 ` Nicolas Boichat
2019-12-20 3:45 ` [PATCH v11 04/10] soc: mediatek: Add multiple step bus protection control Weiyi Lu
` (7 subsequent siblings)
10 siblings, 1 reply; 33+ messages in thread
From: Weiyi Lu @ 2019-12-20 3:45 UTC (permalink / raw)
To: Nicolas Boichat, Matthias Brugger, Rob Herring, Sascha Hauer
Cc: James Liao, Fan Chen, linux-arm-kernel, linux-kernel,
linux-mediatek, srv_heupstream, Weiyi Lu
Try to stop extending the clk_id or clk_names if there are
more and more new BASIC clocks. To get its own clocks by the
basic_clk_name of each power domain.
And then use basic_clk_name strings for all compatibles, instead of
mixing clk_id and clk_name.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
drivers/soc/mediatek/mtk-scpsys.c | 138 +++++++++++++-------------------------
1 file changed, 45 insertions(+), 93 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
index f669d37..db35a28 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -78,34 +78,6 @@
#define PWR_STATUS_HIF1 BIT(26) /* MT7622 */
#define PWR_STATUS_WB BIT(27) /* MT7622 */
-enum clk_id {
- CLK_NONE,
- CLK_MM,
- CLK_MFG,
- CLK_VENC,
- CLK_VENC_LT,
- CLK_ETHIF,
- CLK_VDEC,
- CLK_HIFSEL,
- CLK_JPGDEC,
- CLK_AUDIO,
- CLK_MAX,
-};
-
-static const char * const clk_names[] = {
- NULL,
- "mm",
- "mfg",
- "venc",
- "venc_lt",
- "ethif",
- "vdec",
- "hif_sel",
- "jpgdec",
- "audio",
- NULL,
-};
-
#define MAX_CLKS 3
/**
@@ -116,7 +88,7 @@ enum clk_id {
* @sram_pdn_bits: The mask for sram power control bits.
* @sram_pdn_ack_bits: The mask for sram power control acked bits.
* @bus_prot_mask: The mask for single step bus protection.
- * @clk_id: The basic clocks required by this power domain.
+ * @basic_clk_name: The basic clocks required by this power domain.
* @caps: The flag for active wake-up action.
*/
struct scp_domain_data {
@@ -126,7 +98,7 @@ struct scp_domain_data {
u32 sram_pdn_bits;
u32 sram_pdn_ack_bits;
u32 bus_prot_mask;
- enum clk_id clk_id[MAX_CLKS];
+ const char *basic_clk_name[MAX_CLKS];
u8 caps;
};
@@ -411,12 +383,23 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
return ret;
}
-static void init_clks(struct platform_device *pdev, struct clk **clk)
+static int init_basic_clks(struct platform_device *pdev, struct clk **clk,
+ const char * const *name)
{
int i;
- for (i = CLK_NONE + 1; i < CLK_MAX; i++)
- clk[i] = devm_clk_get(&pdev->dev, clk_names[i]);
+ for (i = 0; i < MAX_CLKS && name[i]; i++) {
+ clk[i] = devm_clk_get(&pdev->dev, name[i]);
+
+ if (IS_ERR(clk[i])) {
+ dev_err(&pdev->dev,
+ "get basic clk %s fail %ld\n",
+ name[i], PTR_ERR(clk[i]));
+ return PTR_ERR(clk[i]);
+ }
+ }
+
+ return 0;
}
static struct scp *init_scp(struct platform_device *pdev,
@@ -426,9 +409,8 @@ static struct scp *init_scp(struct platform_device *pdev,
{
struct genpd_onecell_data *pd_data;
struct resource *res;
- int i, j;
+ int i, ret;
struct scp *scp;
- struct clk *clk[CLK_MAX];
scp = devm_kzalloc(&pdev->dev, sizeof(*scp), GFP_KERNEL);
if (!scp)
@@ -481,8 +463,6 @@ static struct scp *init_scp(struct platform_device *pdev,
pd_data->num_domains = num;
- init_clks(pdev, clk);
-
for (i = 0; i < num; i++) {
struct scp_domain *scpd = &scp->domains[i];
struct generic_pm_domain *genpd = &scpd->genpd;
@@ -493,17 +473,9 @@ static struct scp *init_scp(struct platform_device *pdev,
scpd->data = data;
- for (j = 0; j < MAX_CLKS && data->clk_id[j]; j++) {
- struct clk *c = clk[data->clk_id[j]];
-
- if (IS_ERR(c)) {
- dev_err(&pdev->dev, "%s: clk unavailable\n",
- data->name);
- return ERR_CAST(c);
- }
-
- scpd->clk[j] = c;
- }
+ ret = init_basic_clks(pdev, scpd->clk, data->basic_clk_name);
+ if (ret)
+ return ERR_PTR(ret);
genpd->name = data->name;
genpd->power_off = scpsys_power_off;
@@ -560,7 +532,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_CONN_PWR_CON,
.bus_prot_mask = MT2701_TOP_AXI_PROT_EN_CONN_M |
MT2701_TOP_AXI_PROT_EN_CONN_S,
- .clk_id = {CLK_NONE},
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT2701_POWER_DOMAIN_DISP] = {
@@ -568,7 +539,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.sta_mask = PWR_STATUS_DISP,
.ctl_offs = SPM_DIS_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
- .clk_id = {CLK_MM},
+ .basic_clk_name = {"mm"},
.bus_prot_mask = MT2701_TOP_AXI_PROT_EN_MM_M0,
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
@@ -578,7 +549,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_MFG_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .clk_id = {CLK_MFG},
+ .basic_clk_name = {"mfg"},
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT2701_POWER_DOMAIN_VDEC] = {
@@ -587,7 +558,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_VDE_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .clk_id = {CLK_MM},
+ .basic_clk_name = {"mm"},
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT2701_POWER_DOMAIN_ISP] = {
@@ -596,7 +567,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_ISP_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(13, 12),
- .clk_id = {CLK_MM},
+ .basic_clk_name = {"mm"},
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT2701_POWER_DOMAIN_BDP] = {
@@ -604,7 +575,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.sta_mask = PWR_STATUS_BDP,
.ctl_offs = SPM_BDP_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
- .clk_id = {CLK_NONE},
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT2701_POWER_DOMAIN_ETH] = {
@@ -613,7 +583,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_ETH_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
- .clk_id = {CLK_ETHIF},
+ .basic_clk_name = {"ethif"},
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT2701_POWER_DOMAIN_HIF] = {
@@ -622,14 +592,13 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_HIF_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
- .clk_id = {CLK_ETHIF},
+ .basic_clk_name = {"ethif"},
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT2701_POWER_DOMAIN_IFR_MSC] = {
.name = "ifr_msc",
.sta_mask = PWR_STATUS_IFR_MSC,
.ctl_offs = SPM_IFR_MSC_PWR_CON,
- .clk_id = {CLK_NONE},
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
};
@@ -644,7 +613,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_DIS_PWR_CON,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .clk_id = {CLK_MM},
+ .basic_clk_name = {"mm"},
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT2712_POWER_DOMAIN_VDEC] = {
@@ -653,7 +622,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_VDE_PWR_CON,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .clk_id = {CLK_MM, CLK_VDEC},
+ .basic_clk_name = {"mm", "vdec"},
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT2712_POWER_DOMAIN_VENC] = {
@@ -662,7 +631,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_VEN_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
- .clk_id = {CLK_MM, CLK_VENC, CLK_JPGDEC},
+ .basic_clk_name = {"mm", "venc", "jpgdec"},
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT2712_POWER_DOMAIN_ISP] = {
@@ -671,7 +640,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_ISP_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(13, 12),
- .clk_id = {CLK_MM},
+ .basic_clk_name = {"mm"},
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT2712_POWER_DOMAIN_AUDIO] = {
@@ -680,7 +649,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_AUDIO_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
- .clk_id = {CLK_AUDIO},
+ .basic_clk_name = {"audio"},
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT2712_POWER_DOMAIN_USB] = {
@@ -689,7 +658,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_USB_PWR_CON,
.sram_pdn_bits = GENMASK(10, 8),
.sram_pdn_ack_bits = GENMASK(14, 12),
- .clk_id = {CLK_NONE},
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT2712_POWER_DOMAIN_USB2] = {
@@ -698,7 +666,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_USB2_PWR_CON,
.sram_pdn_bits = GENMASK(10, 8),
.sram_pdn_ack_bits = GENMASK(14, 12),
- .clk_id = {CLK_NONE},
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT2712_POWER_DOMAIN_MFG] = {
@@ -707,7 +674,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_MFG_PWR_CON,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(16, 16),
- .clk_id = {CLK_MFG},
+ .basic_clk_name = {"mfg"},
.bus_prot_mask = BIT(14) | BIT(21) | BIT(23),
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
@@ -717,7 +684,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = 0x02c0,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(16, 16),
- .clk_id = {CLK_NONE},
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT2712_POWER_DOMAIN_MFG_SC2] = {
@@ -726,7 +692,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = 0x02c4,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(16, 16),
- .clk_id = {CLK_NONE},
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT2712_POWER_DOMAIN_MFG_SC3] = {
@@ -735,7 +700,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = 0x01f8,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(16, 16),
- .clk_id = {CLK_NONE},
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
};
@@ -760,7 +724,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = 0x300,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .clk_id = {CLK_VDEC},
+ .basic_clk_name = {"vdec"},
},
[MT6797_POWER_DOMAIN_VENC] = {
.name = "venc",
@@ -768,7 +732,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = 0x304,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
- .clk_id = {CLK_NONE},
},
[MT6797_POWER_DOMAIN_ISP] = {
.name = "isp",
@@ -776,7 +739,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = 0x308,
.sram_pdn_bits = GENMASK(9, 8),
.sram_pdn_ack_bits = GENMASK(13, 12),
- .clk_id = {CLK_NONE},
},
[MT6797_POWER_DOMAIN_MM] = {
.name = "mm",
@@ -784,7 +746,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = 0x30C,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .clk_id = {CLK_MM},
+ .basic_clk_name = {"mm"},
.bus_prot_mask = (BIT(1) | BIT(2)),
},
[MT6797_POWER_DOMAIN_AUDIO] = {
@@ -793,7 +755,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = 0x314,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
- .clk_id = {CLK_NONE},
},
[MT6797_POWER_DOMAIN_MFG_ASYNC] = {
.name = "mfg_async",
@@ -801,7 +762,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = 0x334,
.sram_pdn_bits = 0,
.sram_pdn_ack_bits = 0,
- .clk_id = {CLK_MFG},
+ .basic_clk_name = {"mfg"},
},
[MT6797_POWER_DOMAIN_MJC] = {
.name = "mjc",
@@ -809,7 +770,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = 0x310,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .clk_id = {CLK_NONE},
},
};
@@ -834,7 +794,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_ETHSYS_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
- .clk_id = {CLK_NONE},
.bus_prot_mask = MT7622_TOP_AXI_PROT_EN_ETHSYS,
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
@@ -844,7 +803,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_HIF0_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
- .clk_id = {CLK_HIFSEL},
+ .basic_clk_name = {"hif_sel"},
.bus_prot_mask = MT7622_TOP_AXI_PROT_EN_HIF0,
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
@@ -854,7 +813,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_HIF1_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
- .clk_id = {CLK_HIFSEL},
+ .basic_clk_name = {"hif_sel"},
.bus_prot_mask = MT7622_TOP_AXI_PROT_EN_HIF1,
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
@@ -864,7 +823,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_WB_PWR_CON,
.sram_pdn_bits = 0,
.sram_pdn_ack_bits = 0,
- .clk_id = {CLK_NONE},
.bus_prot_mask = MT7622_TOP_AXI_PROT_EN_WB,
.caps = MTK_SCPD_ACTIVE_WAKEUP | MTK_SCPD_FWAIT_SRAM,
},
@@ -881,7 +839,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_CONN_PWR_CON,
.bus_prot_mask = MT2701_TOP_AXI_PROT_EN_CONN_M |
MT2701_TOP_AXI_PROT_EN_CONN_S,
- .clk_id = {CLK_NONE},
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT7623A_POWER_DOMAIN_ETH] = {
@@ -890,7 +847,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_ETH_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
- .clk_id = {CLK_ETHIF},
+ .basic_clk_name = {"ethif"},
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT7623A_POWER_DOMAIN_HIF] = {
@@ -899,14 +856,13 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_HIF_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
- .clk_id = {CLK_ETHIF},
+ .basic_clk_name = {"ethif"},
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT7623A_POWER_DOMAIN_IFR_MSC] = {
.name = "ifr_msc",
.sta_mask = PWR_STATUS_IFR_MSC,
.ctl_offs = SPM_IFR_MSC_PWR_CON,
- .clk_id = {CLK_NONE},
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
};
@@ -922,7 +878,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_VDE_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .clk_id = {CLK_MM},
+ .basic_clk_name = {"mm"},
},
[MT8173_POWER_DOMAIN_VENC] = {
.name = "venc",
@@ -930,7 +886,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_VEN_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
- .clk_id = {CLK_MM, CLK_VENC},
+ .basic_clk_name = {"mm", "venc"},
},
[MT8173_POWER_DOMAIN_ISP] = {
.name = "isp",
@@ -938,7 +894,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_ISP_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(13, 12),
- .clk_id = {CLK_MM},
+ .basic_clk_name = {"mm"},
},
[MT8173_POWER_DOMAIN_MM] = {
.name = "mm",
@@ -946,7 +902,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_DIS_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .clk_id = {CLK_MM},
+ .basic_clk_name = {"mm"},
.bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 |
MT8173_TOP_AXI_PROT_EN_MM_M1,
},
@@ -956,7 +912,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_VEN2_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
- .clk_id = {CLK_MM, CLK_VENC_LT},
+ .basic_clk_name = {"mm", "venc_lt"},
},
[MT8173_POWER_DOMAIN_AUDIO] = {
.name = "audio",
@@ -964,7 +920,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_AUDIO_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
- .clk_id = {CLK_NONE},
},
[MT8173_POWER_DOMAIN_USB] = {
.name = "usb",
@@ -972,7 +927,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_USB_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
- .clk_id = {CLK_NONE},
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT8173_POWER_DOMAIN_MFG_ASYNC] = {
@@ -981,7 +935,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_MFG_ASYNC_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = 0,
- .clk_id = {CLK_MFG},
+ .basic_clk_name = {"mfg"},
},
[MT8173_POWER_DOMAIN_MFG_2D] = {
.name = "mfg_2d",
@@ -989,7 +943,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_MFG_2D_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(13, 12),
- .clk_id = {CLK_NONE},
},
[MT8173_POWER_DOMAIN_MFG] = {
.name = "mfg",
@@ -997,7 +950,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_MFG_PWR_CON,
.sram_pdn_bits = GENMASK(13, 8),
.sram_pdn_ack_bits = GENMASK(21, 16),
- .clk_id = {CLK_NONE},
.bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MFG_S |
MT8173_TOP_AXI_PROT_EN_MFG_M0 |
MT8173_TOP_AXI_PROT_EN_MFG_M1 |
--
1.8.1.1.dirty
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH v11 04/10] soc: mediatek: Add multiple step bus protection control
2019-12-20 3:45 [PATCH v11 00/10] Mediatek MT8183 scpsys support Weiyi Lu
` (2 preceding siblings ...)
2019-12-20 3:45 ` [PATCH v11 03/10] soc: mediatek: Add basic_clk_name to scp_power_data Weiyi Lu
@ 2019-12-20 3:45 ` Weiyi Lu
2019-12-20 4:09 ` Nicolas Boichat
2020-02-11 17:49 ` Matthias Brugger
2019-12-20 3:45 ` [PATCH v11 05/10] soc: mediatek: Remove infracfg misc driver support Weiyi Lu
` (6 subsequent siblings)
10 siblings, 2 replies; 33+ messages in thread
From: Weiyi Lu @ 2019-12-20 3:45 UTC (permalink / raw)
To: Nicolas Boichat, Matthias Brugger, Rob Herring, Sascha Hauer
Cc: James Liao, Fan Chen, linux-arm-kernel, linux-kernel,
linux-mediatek, srv_heupstream, Weiyi Lu
Both MT8183 & MT6765 have more control steps of bus protection
than previous project. And there add more bus protection registers
reside at infracfg & smi-common. Also add new APIs for multiple
step bus protection control with more customized arguments.
And then use bp_table for bus protection of all compatibles,
instead of mixing bus_prot_mask and bus_prot_reg_update.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
drivers/soc/mediatek/Makefile | 2 +-
drivers/soc/mediatek/mtk-scpsys-ext.c | 101 +++++++++++++++++++++++++++++
drivers/soc/mediatek/mtk-scpsys.c | 117 +++++++++++++++++++++-------------
drivers/soc/mediatek/scpsys-ext.h | 67 +++++++++++++++++++
4 files changed, 240 insertions(+), 47 deletions(-)
create mode 100644 drivers/soc/mediatek/mtk-scpsys-ext.c
create mode 100644 drivers/soc/mediatek/scpsys-ext.h
diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
index b017330..b442be9 100644
--- a/drivers/soc/mediatek/Makefile
+++ b/drivers/soc/mediatek/Makefile
@@ -1,5 +1,5 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o
-obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
+obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o mtk-scpsys-ext.o
obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
diff --git a/drivers/soc/mediatek/mtk-scpsys-ext.c b/drivers/soc/mediatek/mtk-scpsys-ext.c
new file mode 100644
index 0000000..df402ac
--- /dev/null
+++ b/drivers/soc/mediatek/mtk-scpsys-ext.c
@@ -0,0 +1,101 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Owen Chen <Owen.Chen@mediatek.com>
+ */
+#include <linux/ktime.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of_device.h>
+#include <linux/regmap.h>
+#include "scpsys-ext.h"
+
+#define MTK_POLL_DELAY_US 10
+#define MTK_POLL_TIMEOUT USEC_PER_SEC
+
+static int set_bus_protection(struct regmap *map, u32 mask,
+ u32 reg_set, u32 reg_sta, u32 reg_en)
+{
+ u32 val;
+
+ if (reg_set)
+ regmap_write(map, reg_set, mask);
+ else
+ regmap_update_bits(map, reg_en, mask, mask);
+
+ return regmap_read_poll_timeout(map, reg_sta,
+ val, (val & mask) == mask,
+ MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
+}
+
+static int clear_bus_protection(struct regmap *map, u32 mask,
+ u32 reg_clr, u32 reg_sta, u32 reg_en, bool ignore_ack)
+{
+ u32 val;
+
+ if (reg_clr)
+ regmap_write(map, reg_clr, mask);
+ else
+ regmap_update_bits(map, reg_en, mask, 0);
+
+ if (ignore_ack)
+ return 0;
+
+ return regmap_read_poll_timeout(map, reg_sta,
+ val, !(val & mask),
+ MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
+}
+
+int mtk_scpsys_ext_set_bus_protection(const struct bus_prot *bp_table,
+ struct regmap *infracfg, struct regmap *smi_common)
+{
+ int i;
+
+ for (i = 0; i < MAX_STEPS; i++) {
+ struct regmap *map = NULL;
+ int ret;
+
+ if (bp_table[i].type == INVALID_TYPE)
+ break;
+ else if (bp_table[i].type == IFR_TYPE)
+ map = infracfg;
+ else if (bp_table[i].type == SMI_TYPE)
+ map = smi_common;
+
+ ret = set_bus_protection(map,
+ bp_table[i].mask, bp_table[i].set_ofs,
+ bp_table[i].sta_ofs, bp_table[i].en_ofs);
+
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+int mtk_scpsys_ext_clear_bus_protection(const struct bus_prot *bp_table,
+ struct regmap *infracfg, struct regmap *smi_common)
+{
+ int i;
+
+ for (i = MAX_STEPS - 1; i >= 0; i--) {
+ struct regmap *map = NULL;
+ int ret;
+
+ if (bp_table[i].type == INVALID_TYPE)
+ continue;
+ else if (bp_table[i].type == IFR_TYPE)
+ map = infracfg;
+ else if (bp_table[i].type == SMI_TYPE)
+ map = smi_common;
+
+ ret = clear_bus_protection(map,
+ bp_table[i].mask, bp_table[i].clr_ofs,
+ bp_table[i].sta_ofs, bp_table[i].en_ofs,
+ bp_table[i].ignore_clr_ack);
+
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
index db35a28..763ca58 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -11,7 +11,7 @@
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
#include <linux/regulator/consumer.h>
-#include <linux/soc/mediatek/infracfg.h>
+#include "scpsys-ext.h"
#include <dt-bindings/power/mt2701-power.h>
#include <dt-bindings/power/mt2712-power.h>
@@ -87,9 +87,9 @@
* @ctl_offs: The offset for main power control register.
* @sram_pdn_bits: The mask for sram power control bits.
* @sram_pdn_ack_bits: The mask for sram power control acked bits.
- * @bus_prot_mask: The mask for single step bus protection.
* @basic_clk_name: The basic clocks required by this power domain.
* @caps: The flag for active wake-up action.
+ * @bp_table: The mask table for multiple step bus protection.
*/
struct scp_domain_data {
const char *name;
@@ -97,9 +97,9 @@ struct scp_domain_data {
int ctl_offs;
u32 sram_pdn_bits;
u32 sram_pdn_ack_bits;
- u32 bus_prot_mask;
const char *basic_clk_name[MAX_CLKS];
u8 caps;
+ struct bus_prot bp_table[MAX_STEPS];
};
struct scp;
@@ -123,8 +123,8 @@ struct scp {
struct device *dev;
void __iomem *base;
struct regmap *infracfg;
+ struct regmap *smi_common;
struct scp_ctrl_reg ctrl_reg;
- bool bus_prot_reg_update;
};
struct scp_subdomain {
@@ -138,7 +138,6 @@ struct scp_soc_data {
const struct scp_subdomain *subdomains;
int num_subdomains;
const struct scp_ctrl_reg regs;
- bool bus_prot_reg_update;
};
static int scpsys_domain_is_on(struct scp_domain *scpd)
@@ -252,24 +251,16 @@ static int scpsys_bus_protect_enable(struct scp_domain *scpd)
{
struct scp *scp = scpd->scp;
- if (!scpd->data->bus_prot_mask)
- return 0;
-
- return mtk_infracfg_set_bus_protection(scp->infracfg,
- scpd->data->bus_prot_mask,
- scp->bus_prot_reg_update);
+ return mtk_scpsys_ext_set_bus_protection(scpd->data->bp_table,
+ scp->infracfg, scp->smi_common);
}
static int scpsys_bus_protect_disable(struct scp_domain *scpd)
{
struct scp *scp = scpd->scp;
- if (!scpd->data->bus_prot_mask)
- return 0;
-
- return mtk_infracfg_clear_bus_protection(scp->infracfg,
- scpd->data->bus_prot_mask,
- scp->bus_prot_reg_update);
+ return mtk_scpsys_ext_clear_bus_protection(scpd->data->bp_table,
+ scp->infracfg, scp->smi_common);
}
static int scpsys_power_on(struct generic_pm_domain *genpd)
@@ -404,8 +395,7 @@ static int init_basic_clks(struct platform_device *pdev, struct clk **clk,
static struct scp *init_scp(struct platform_device *pdev,
const struct scp_domain_data *scp_domain_data, int num,
- const struct scp_ctrl_reg *scp_ctrl_reg,
- bool bus_prot_reg_update)
+ const struct scp_ctrl_reg *scp_ctrl_reg)
{
struct genpd_onecell_data *pd_data;
struct resource *res;
@@ -419,8 +409,6 @@ static struct scp *init_scp(struct platform_device *pdev,
scp->ctrl_reg.pwr_sta_offs = scp_ctrl_reg->pwr_sta_offs;
scp->ctrl_reg.pwr_sta2nd_offs = scp_ctrl_reg->pwr_sta2nd_offs;
- scp->bus_prot_reg_update = bus_prot_reg_update;
-
scp->dev = &pdev->dev;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -448,6 +436,17 @@ static struct scp *init_scp(struct platform_device *pdev,
return ERR_CAST(scp->infracfg);
}
+ scp->smi_common = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
+ "smi_comm");
+
+ if (scp->smi_common == ERR_PTR(-ENODEV)) {
+ scp->smi_common = NULL;
+ } else if (IS_ERR(scp->smi_common)) {
+ dev_err(&pdev->dev, "Cannot find smi_common controller: %ld\n",
+ PTR_ERR(scp->smi_common));
+ return ERR_CAST(scp->smi_common);
+ }
+
for (i = 0; i < num; i++) {
struct scp_domain *scpd = &scp->domains[i];
const struct scp_domain_data *data = &scp_domain_data[i];
@@ -530,8 +529,11 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.name = "conn",
.sta_mask = PWR_STATUS_CONN,
.ctl_offs = SPM_CONN_PWR_CON,
- .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_CONN_M |
- MT2701_TOP_AXI_PROT_EN_CONN_S,
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
+ MT2701_TOP_AXI_PROT_EN_CONN_M |
+ MT2701_TOP_AXI_PROT_EN_CONN_S),
+ },
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT2701_POWER_DOMAIN_DISP] = {
@@ -540,7 +542,10 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_DIS_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.basic_clk_name = {"mm"},
- .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_MM_M0,
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
+ MT2701_TOP_AXI_PROT_EN_MM_M0),
+ },
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT2701_POWER_DOMAIN_MFG] = {
@@ -675,7 +680,10 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(16, 16),
.basic_clk_name = {"mfg"},
- .bus_prot_mask = BIT(14) | BIT(21) | BIT(23),
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0x260, 0x264, 0x220, 0x228,
+ BIT(14) | BIT(21) | BIT(23)),
+ },
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT2712_POWER_DOMAIN_MFG_SC1] = {
@@ -747,7 +755,10 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.basic_clk_name = {"mm"},
- .bus_prot_mask = (BIT(1) | BIT(2)),
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
+ BIT(1) | BIT(2)),
+ },
},
[MT6797_POWER_DOMAIN_AUDIO] = {
.name = "audio",
@@ -794,7 +805,10 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_ETHSYS_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
- .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_ETHSYS,
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
+ MT7622_TOP_AXI_PROT_EN_ETHSYS),
+ },
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT7622_POWER_DOMAIN_HIF0] = {
@@ -804,7 +818,10 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
.basic_clk_name = {"hif_sel"},
- .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_HIF0,
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
+ MT7622_TOP_AXI_PROT_EN_HIF0),
+ },
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT7622_POWER_DOMAIN_HIF1] = {
@@ -814,7 +831,10 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
.basic_clk_name = {"hif_sel"},
- .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_HIF1,
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
+ MT7622_TOP_AXI_PROT_EN_HIF1),
+ },
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT7622_POWER_DOMAIN_WB] = {
@@ -823,7 +843,10 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_WB_PWR_CON,
.sram_pdn_bits = 0,
.sram_pdn_ack_bits = 0,
- .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_WB,
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
+ MT7622_TOP_AXI_PROT_EN_WB),
+ },
.caps = MTK_SCPD_ACTIVE_WAKEUP | MTK_SCPD_FWAIT_SRAM,
},
};
@@ -837,8 +860,11 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.name = "conn",
.sta_mask = PWR_STATUS_CONN,
.ctl_offs = SPM_CONN_PWR_CON,
- .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_CONN_M |
- MT2701_TOP_AXI_PROT_EN_CONN_S,
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
+ MT2701_TOP_AXI_PROT_EN_CONN_M |
+ MT2701_TOP_AXI_PROT_EN_CONN_S),
+ },
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT7623A_POWER_DOMAIN_ETH] = {
@@ -903,8 +929,11 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.basic_clk_name = {"mm"},
- .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 |
- MT8173_TOP_AXI_PROT_EN_MM_M1,
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
+ MT8173_TOP_AXI_PROT_EN_MM_M0 |
+ MT8173_TOP_AXI_PROT_EN_MM_M1),
+ },
},
[MT8173_POWER_DOMAIN_VENC_LT] = {
.name = "venc_lt",
@@ -950,10 +979,13 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_MFG_PWR_CON,
.sram_pdn_bits = GENMASK(13, 8),
.sram_pdn_ack_bits = GENMASK(21, 16),
- .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MFG_S |
- MT8173_TOP_AXI_PROT_EN_MFG_M0 |
- MT8173_TOP_AXI_PROT_EN_MFG_M1 |
- MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT,
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
+ MT8173_TOP_AXI_PROT_EN_MFG_S |
+ MT8173_TOP_AXI_PROT_EN_MFG_M0 |
+ MT8173_TOP_AXI_PROT_EN_MFG_M1 |
+ MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT),
+ },
},
};
@@ -969,7 +1001,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.pwr_sta_offs = SPM_PWR_STATUS,
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
},
- .bus_prot_reg_update = true,
};
static const struct scp_soc_data mt2712_data = {
@@ -981,7 +1012,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.pwr_sta_offs = SPM_PWR_STATUS,
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
},
- .bus_prot_reg_update = false,
};
static const struct scp_soc_data mt6797_data = {
@@ -993,7 +1023,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.pwr_sta_offs = SPM_PWR_STATUS_MT6797,
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND_MT6797
},
- .bus_prot_reg_update = true,
};
static const struct scp_soc_data mt7622_data = {
@@ -1003,7 +1032,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.pwr_sta_offs = SPM_PWR_STATUS,
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
},
- .bus_prot_reg_update = true,
};
static const struct scp_soc_data mt7623a_data = {
@@ -1013,7 +1041,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.pwr_sta_offs = SPM_PWR_STATUS,
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
},
- .bus_prot_reg_update = true,
};
static const struct scp_soc_data mt8173_data = {
@@ -1025,7 +1052,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.pwr_sta_offs = SPM_PWR_STATUS,
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
},
- .bus_prot_reg_update = true,
};
/*
@@ -1066,8 +1092,7 @@ static int scpsys_probe(struct platform_device *pdev)
soc = of_device_get_match_data(&pdev->dev);
- scp = init_scp(pdev, soc->domains, soc->num_domains, &soc->regs,
- soc->bus_prot_reg_update);
+ scp = init_scp(pdev, soc->domains, soc->num_domains, &soc->regs);
if (IS_ERR(scp))
return PTR_ERR(scp);
diff --git a/drivers/soc/mediatek/scpsys-ext.h b/drivers/soc/mediatek/scpsys-ext.h
new file mode 100644
index 0000000..458b2c5
--- /dev/null
+++ b/drivers/soc/mediatek/scpsys-ext.h
@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __SOC_MEDIATEK_SCPSYS_EXT_H
+#define __SOC_MEDIATEK_SCPSYS_EXT_H
+
+#define MAX_STEPS 4
+
+#define _BUS_PROT(_type, _set_ofs, _clr_ofs, \
+ _en_ofs, _sta_ofs, _mask, _ignore_clr_ack) { \
+ .type = _type, \
+ .set_ofs = _set_ofs, \
+ .clr_ofs = _clr_ofs, \
+ .en_ofs = _en_ofs, \
+ .sta_ofs = _sta_ofs, \
+ .mask = _mask, \
+ .ignore_clr_ack = _ignore_clr_ack, \
+ }
+
+#define BUS_PROT(_type, _set_ofs, _clr_ofs, \
+ _en_ofs, _sta_ofs, _mask) \
+ _BUS_PROT(_type, _set_ofs, _clr_ofs, \
+ _en_ofs, _sta_ofs, _mask, false)
+
+#define BUS_PROT_IGN(_type, _set_ofs, _clr_ofs, \
+ _en_ofs, _sta_ofs, _mask) \
+ _BUS_PROT(_type, _set_ofs, _clr_ofs, \
+ _en_ofs, _sta_ofs, _mask, true)
+
+#define MT2701_TOP_AXI_PROT_EN_MM_M0 BIT(1)
+#define MT2701_TOP_AXI_PROT_EN_CONN_M BIT(2)
+#define MT2701_TOP_AXI_PROT_EN_CONN_S BIT(8)
+
+#define MT7622_TOP_AXI_PROT_EN_ETHSYS (BIT(3) | BIT(17))
+#define MT7622_TOP_AXI_PROT_EN_HIF0 (BIT(24) | BIT(25))
+#define MT7622_TOP_AXI_PROT_EN_HIF1 (BIT(26) | BIT(27) | \
+ BIT(28))
+#define MT7622_TOP_AXI_PROT_EN_WB (BIT(2) | BIT(6) | \
+ BIT(7) | BIT(8))
+
+#define MT8173_TOP_AXI_PROT_EN_MM_M0 BIT(1)
+#define MT8173_TOP_AXI_PROT_EN_MM_M1 BIT(2)
+#define MT8173_TOP_AXI_PROT_EN_MFG_S BIT(14)
+#define MT8173_TOP_AXI_PROT_EN_MFG_M0 BIT(21)
+#define MT8173_TOP_AXI_PROT_EN_MFG_M1 BIT(22)
+#define MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT BIT(23)
+
+enum regmap_type {
+ INVALID_TYPE = 0,
+ IFR_TYPE,
+ SMI_TYPE,
+};
+
+struct bus_prot {
+ enum regmap_type type;
+ u32 set_ofs;
+ u32 clr_ofs;
+ u32 en_ofs;
+ u32 sta_ofs;
+ u32 mask;
+ bool ignore_clr_ack;
+};
+
+int mtk_scpsys_ext_set_bus_protection(const struct bus_prot *bp_table,
+ struct regmap *infracfg, struct regmap *smi_common);
+int mtk_scpsys_ext_clear_bus_protection(const struct bus_prot *bp_table,
+ struct regmap *infracfg, struct regmap *smi_common);
+
+#endif /* __SOC_MEDIATEK_SCPSYS_EXT_H */
--
1.8.1.1.dirty
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH v11 05/10] soc: mediatek: Remove infracfg misc driver support
2019-12-20 3:45 [PATCH v11 00/10] Mediatek MT8183 scpsys support Weiyi Lu
` (3 preceding siblings ...)
2019-12-20 3:45 ` [PATCH v11 04/10] soc: mediatek: Add multiple step bus protection control Weiyi Lu
@ 2019-12-20 3:45 ` Weiyi Lu
2019-12-20 4:11 ` Nicolas Boichat
2019-12-20 3:46 ` [PATCH v11 06/10] soc: mediatek: Add subsys clock control for bus protection Weiyi Lu
` (5 subsequent siblings)
10 siblings, 1 reply; 33+ messages in thread
From: Weiyi Lu @ 2019-12-20 3:45 UTC (permalink / raw)
To: Nicolas Boichat, Matthias Brugger, Rob Herring, Sascha Hauer
Cc: James Liao, Fan Chen, linux-arm-kernel, linux-kernel,
linux-mediatek, srv_heupstream, Weiyi Lu
In previous patches, we introduce scpsys-ext driver that covers
the functions which infracfg misc driver provided.
And then replace bus_prot_mask with bp_table of all compatibles.
Now, we're going to remove infracfg misc drvier which is no longer
being used.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
drivers/soc/mediatek/Kconfig | 10 -----
drivers/soc/mediatek/Makefile | 3 +-
drivers/soc/mediatek/mtk-infracfg.c | 79 -----------------------------------
include/linux/soc/mediatek/infracfg.h | 39 -----------------
4 files changed, 1 insertion(+), 130 deletions(-)
delete mode 100644 drivers/soc/mediatek/mtk-infracfg.c
delete mode 100644 include/linux/soc/mediatek/infracfg.h
diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
index 2114b56..f837b3c 100644
--- a/drivers/soc/mediatek/Kconfig
+++ b/drivers/soc/mediatek/Kconfig
@@ -10,21 +10,12 @@ config MTK_CMDQ
depends on ARCH_MEDIATEK || COMPILE_TEST
select MAILBOX
select MTK_CMDQ_MBOX
- select MTK_INFRACFG
help
Say yes here to add support for the MediaTek Command Queue (CMDQ)
driver. The CMDQ is used to help read/write registers with critical
time limitation, such as updating display configuration during the
vblank.
-config MTK_INFRACFG
- bool "MediaTek INFRACFG Support"
- select REGMAP
- help
- Say yes here to add support for the MediaTek INFRACFG controller. The
- INFRACFG controller contains various infrastructure registers not
- directly associated to any device.
-
config MTK_PMIC_WRAP
tristate "MediaTek PMIC Wrapper Support"
depends on RESET_CONTROLLER
@@ -38,7 +29,6 @@ config MTK_SCPSYS
bool "MediaTek SCPSYS Support"
default ARCH_MEDIATEK
select REGMAP
- select MTK_INFRACFG
select PM_GENERIC_DOMAINS if PM
help
Say yes here to add support for the MediaTek SCPSYS power domain
diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
index b442be9..7bf7e88 100644
--- a/drivers/soc/mediatek/Makefile
+++ b/drivers/soc/mediatek/Makefile
@@ -1,5 +1,4 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o
-obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o mtk-scpsys-ext.o
obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
-obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
+obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o mtk-scpsys-ext.o
diff --git a/drivers/soc/mediatek/mtk-infracfg.c b/drivers/soc/mediatek/mtk-infracfg.c
deleted file mode 100644
index 341c7ac..0000000
--- a/drivers/soc/mediatek/mtk-infracfg.c
+++ /dev/null
@@ -1,79 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (c) 2015 Pengutronix, Sascha Hauer <kernel@pengutronix.de>
- */
-
-#include <linux/export.h>
-#include <linux/jiffies.h>
-#include <linux/regmap.h>
-#include <linux/soc/mediatek/infracfg.h>
-#include <asm/processor.h>
-
-#define MTK_POLL_DELAY_US 10
-#define MTK_POLL_TIMEOUT (jiffies_to_usecs(HZ))
-
-#define INFRA_TOPAXI_PROTECTEN 0x0220
-#define INFRA_TOPAXI_PROTECTSTA1 0x0228
-#define INFRA_TOPAXI_PROTECTEN_SET 0x0260
-#define INFRA_TOPAXI_PROTECTEN_CLR 0x0264
-
-/**
- * mtk_infracfg_set_bus_protection - enable bus protection
- * @regmap: The infracfg regmap
- * @mask: The mask containing the protection bits to be enabled.
- * @reg_update: The boolean flag determines to set the protection bits
- * by regmap_update_bits with enable register(PROTECTEN) or
- * by regmap_write with set register(PROTECTEN_SET).
- *
- * This function enables the bus protection bits for disabled power
- * domains so that the system does not hang when some unit accesses the
- * bus while in power down.
- */
-int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask,
- bool reg_update)
-{
- u32 val;
- int ret;
-
- if (reg_update)
- regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask,
- mask);
- else
- regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_SET, mask);
-
- ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1,
- val, (val & mask) == mask,
- MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
-
- return ret;
-}
-
-/**
- * mtk_infracfg_clear_bus_protection - disable bus protection
- * @regmap: The infracfg regmap
- * @mask: The mask containing the protection bits to be disabled.
- * @reg_update: The boolean flag determines to clear the protection bits
- * by regmap_update_bits with enable register(PROTECTEN) or
- * by regmap_write with clear register(PROTECTEN_CLR).
- *
- * This function disables the bus protection bits previously enabled with
- * mtk_infracfg_set_bus_protection.
- */
-
-int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask,
- bool reg_update)
-{
- int ret;
- u32 val;
-
- if (reg_update)
- regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, 0);
- else
- regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_CLR, mask);
-
- ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1,
- val, !(val & mask),
- MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
-
- return ret;
-}
diff --git a/include/linux/soc/mediatek/infracfg.h b/include/linux/soc/mediatek/infracfg.h
deleted file mode 100644
index fd25f01..0000000
--- a/include/linux/soc/mediatek/infracfg.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __SOC_MEDIATEK_INFRACFG_H
-#define __SOC_MEDIATEK_INFRACFG_H
-
-#define MT8173_TOP_AXI_PROT_EN_MCI_M2 BIT(0)
-#define MT8173_TOP_AXI_PROT_EN_MM_M0 BIT(1)
-#define MT8173_TOP_AXI_PROT_EN_MM_M1 BIT(2)
-#define MT8173_TOP_AXI_PROT_EN_MMAPB_S BIT(6)
-#define MT8173_TOP_AXI_PROT_EN_L2C_M2 BIT(9)
-#define MT8173_TOP_AXI_PROT_EN_L2SS_SMI BIT(11)
-#define MT8173_TOP_AXI_PROT_EN_L2SS_ADD BIT(12)
-#define MT8173_TOP_AXI_PROT_EN_CCI_M2 BIT(13)
-#define MT8173_TOP_AXI_PROT_EN_MFG_S BIT(14)
-#define MT8173_TOP_AXI_PROT_EN_PERI_M0 BIT(15)
-#define MT8173_TOP_AXI_PROT_EN_PERI_M1 BIT(16)
-#define MT8173_TOP_AXI_PROT_EN_DEBUGSYS BIT(17)
-#define MT8173_TOP_AXI_PROT_EN_CQ_DMA BIT(18)
-#define MT8173_TOP_AXI_PROT_EN_GCPU BIT(19)
-#define MT8173_TOP_AXI_PROT_EN_IOMMU BIT(20)
-#define MT8173_TOP_AXI_PROT_EN_MFG_M0 BIT(21)
-#define MT8173_TOP_AXI_PROT_EN_MFG_M1 BIT(22)
-#define MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT BIT(23)
-
-#define MT2701_TOP_AXI_PROT_EN_MM_M0 BIT(1)
-#define MT2701_TOP_AXI_PROT_EN_CONN_M BIT(2)
-#define MT2701_TOP_AXI_PROT_EN_CONN_S BIT(8)
-
-#define MT7622_TOP_AXI_PROT_EN_ETHSYS (BIT(3) | BIT(17))
-#define MT7622_TOP_AXI_PROT_EN_HIF0 (BIT(24) | BIT(25))
-#define MT7622_TOP_AXI_PROT_EN_HIF1 (BIT(26) | BIT(27) | \
- BIT(28))
-#define MT7622_TOP_AXI_PROT_EN_WB (BIT(2) | BIT(6) | \
- BIT(7) | BIT(8))
-
-int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask,
- bool reg_update);
-int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask,
- bool reg_update);
-#endif /* __SOC_MEDIATEK_INFRACFG_H */
--
1.8.1.1.dirty
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH v11 06/10] soc: mediatek: Add subsys clock control for bus protection
2019-12-20 3:45 [PATCH v11 00/10] Mediatek MT8183 scpsys support Weiyi Lu
` (4 preceding siblings ...)
2019-12-20 3:45 ` [PATCH v11 05/10] soc: mediatek: Remove infracfg misc driver support Weiyi Lu
@ 2019-12-20 3:46 ` Weiyi Lu
2020-02-11 17:54 ` Matthias Brugger
2019-12-20 3:46 ` [PATCH v11 07/10] soc: mediatek: Add extra sram control Weiyi Lu
` (4 subsequent siblings)
10 siblings, 1 reply; 33+ messages in thread
From: Weiyi Lu @ 2019-12-20 3:46 UTC (permalink / raw)
To: Nicolas Boichat, Matthias Brugger, Rob Herring, Sascha Hauer
Cc: James Liao, Fan Chen, linux-arm-kernel, linux-kernel,
linux-mediatek, srv_heupstream, Weiyi Lu
Add subsys CG control flow before/after the bus protect control
due to bus protection need SMI bus relative CGs enabled to feedback
its ack.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
---
drivers/soc/mediatek/mtk-scpsys.c | 72 +++++++++++++++++++++++++++++++++++++--
1 file changed, 70 insertions(+), 2 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
index 763ca58..32be4b3 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -79,6 +79,7 @@
#define PWR_STATUS_WB BIT(27) /* MT7622 */
#define MAX_CLKS 3
+#define MAX_SUBSYS_CLKS 10
/**
* struct scp_domain_data - scp domain data for power on/off flow
@@ -88,6 +89,8 @@
* @sram_pdn_bits: The mask for sram power control bits.
* @sram_pdn_ack_bits: The mask for sram power control acked bits.
* @basic_clk_name: The basic clocks required by this power domain.
+ * @subsys_clk_prefix: The prefix name of the clocks need to be enabled
+ * before releasing bus protection.
* @caps: The flag for active wake-up action.
* @bp_table: The mask table for multiple step bus protection.
*/
@@ -98,6 +101,7 @@ struct scp_domain_data {
u32 sram_pdn_bits;
u32 sram_pdn_ack_bits;
const char *basic_clk_name[MAX_CLKS];
+ const char *subsys_clk_prefix;
u8 caps;
struct bus_prot bp_table[MAX_STEPS];
};
@@ -108,6 +112,7 @@ struct scp_domain {
struct generic_pm_domain genpd;
struct scp *scp;
struct clk *clk[MAX_CLKS];
+ struct clk *subsys_clk[MAX_SUBSYS_CLKS];
const struct scp_domain_data *data;
struct regulator *supply;
};
@@ -301,16 +306,22 @@ static int scpsys_power_on(struct generic_pm_domain *genpd)
val |= PWR_RST_B_BIT;
writel(val, ctl_addr);
- ret = scpsys_sram_enable(scpd, ctl_addr);
+ ret = scpsys_clk_enable(scpd->subsys_clk, MAX_SUBSYS_CLKS);
if (ret < 0)
goto err_pwr_ack;
+ ret = scpsys_sram_enable(scpd, ctl_addr);
+ if (ret < 0)
+ goto err_sram;
+
ret = scpsys_bus_protect_disable(scpd);
if (ret < 0)
- goto err_pwr_ack;
+ goto err_sram;
return 0;
+err_sram:
+ scpsys_clk_disable(scpd->subsys_clk, MAX_SUBSYS_CLKS);
err_pwr_ack:
scpsys_clk_disable(scpd->clk, MAX_CLKS);
err_clk:
@@ -337,6 +348,8 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
if (ret < 0)
goto out;
+ scpsys_clk_disable(scpd->subsys_clk, MAX_SUBSYS_CLKS);
+
/* subsys power off */
val = readl(ctl_addr);
val |= PWR_ISO_BIT;
@@ -374,6 +387,48 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
return ret;
}
+static int init_subsys_clks(struct platform_device *pdev,
+ const char *prefix, struct clk **clk)
+{
+ struct device_node *node = pdev->dev.of_node;
+ u32 prefix_len, sub_clk_cnt = 0;
+ struct property *prop;
+ const char *clk_name;
+
+ if (!node) {
+ dev_err(&pdev->dev, "Cannot find scpsys node: %ld\n",
+ PTR_ERR(node));
+ return PTR_ERR(node);
+ }
+
+ prefix_len = strlen(prefix);
+
+ of_property_for_each_string(node, "clock-names", prop, clk_name) {
+ if (!strncmp(clk_name, prefix, prefix_len) &&
+ (clk_name[prefix_len] == '-')) {
+ if (sub_clk_cnt >= MAX_SUBSYS_CLKS) {
+ dev_err(&pdev->dev,
+ "subsys clk out of range %d\n",
+ sub_clk_cnt);
+ return -ENOMEM;
+ }
+
+ clk[sub_clk_cnt] = devm_clk_get(&pdev->dev,
+ clk_name);
+
+ if (IS_ERR(clk[sub_clk_cnt])) {
+ dev_err(&pdev->dev,
+ "Subsys clk get fail %ld\n",
+ PTR_ERR(clk[sub_clk_cnt]));
+ return PTR_ERR(clk[sub_clk_cnt]);
+ }
+ sub_clk_cnt++;
+ }
+ }
+
+ return sub_clk_cnt;
+}
+
static int init_basic_clks(struct platform_device *pdev, struct clk **clk,
const char * const *name)
{
@@ -466,6 +521,7 @@ static struct scp *init_scp(struct platform_device *pdev,
struct scp_domain *scpd = &scp->domains[i];
struct generic_pm_domain *genpd = &scpd->genpd;
const struct scp_domain_data *data = &scp_domain_data[i];
+ int clk_cnt;
pd_data->domains[i] = genpd;
scpd->scp = scp;
@@ -476,6 +532,18 @@ static struct scp *init_scp(struct platform_device *pdev,
if (ret)
return ERR_PTR(ret);
+ if (data->subsys_clk_prefix) {
+ clk_cnt = init_subsys_clks(pdev,
+ data->subsys_clk_prefix,
+ scpd->subsys_clk);
+ if (clk_cnt < 0) {
+ dev_err(&pdev->dev,
+ "%s: subsys clk unavailable\n",
+ data->name);
+ return ERR_PTR(clk_cnt);
+ }
+ }
+
genpd->name = data->name;
genpd->power_off = scpsys_power_off;
genpd->power_on = scpsys_power_on;
--
1.8.1.1.dirty
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH v11 07/10] soc: mediatek: Add extra sram control
2019-12-20 3:45 [PATCH v11 00/10] Mediatek MT8183 scpsys support Weiyi Lu
` (5 preceding siblings ...)
2019-12-20 3:46 ` [PATCH v11 06/10] soc: mediatek: Add subsys clock control for bus protection Weiyi Lu
@ 2019-12-20 3:46 ` Weiyi Lu
2020-02-11 17:04 ` Matthias Brugger
2019-12-20 3:46 ` [PATCH v11 08/10] soc: mediatek: Add MT8183 scpsys support Weiyi Lu
` (3 subsequent siblings)
10 siblings, 1 reply; 33+ messages in thread
From: Weiyi Lu @ 2019-12-20 3:46 UTC (permalink / raw)
To: Nicolas Boichat, Matthias Brugger, Rob Herring, Sascha Hauer
Cc: James Liao, Fan Chen, linux-arm-kernel, linux-kernel,
linux-mediatek, srv_heupstream, Weiyi Lu
For some power domains like vpu_core on MT8183 whose sram need to
do clock and internal isolation while power on/off sram.
We add a flag "sram_iso_ctrl" in scp_domain_data to judge if we
need to do the extra sram isolation control or not.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
---
drivers/soc/mediatek/mtk-scpsys.c | 24 ++++++++++++++++++++++--
1 file changed, 22 insertions(+), 2 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
index 32be4b3..1972726 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -56,6 +56,8 @@
#define PWR_ON_BIT BIT(2)
#define PWR_ON_2ND_BIT BIT(3)
#define PWR_CLK_DIS_BIT BIT(4)
+#define PWR_SRAM_CLKISO_BIT BIT(5)
+#define PWR_SRAM_ISOINT_B_BIT BIT(6)
#define PWR_STATUS_CONN BIT(1)
#define PWR_STATUS_DISP BIT(3)
@@ -86,6 +88,8 @@
* @name: The domain name.
* @sta_mask: The mask for power on/off status bit.
* @ctl_offs: The offset for main power control register.
+ * @sram_iso_ctrl: The flag to judge if the power domain need to do
+ * the extra sram isolation control.
* @sram_pdn_bits: The mask for sram power control bits.
* @sram_pdn_ack_bits: The mask for sram power control acked bits.
* @basic_clk_name: The basic clocks required by this power domain.
@@ -98,6 +102,7 @@ struct scp_domain_data {
const char *name;
u32 sta_mask;
int ctl_offs;
+ bool sram_iso_ctrl;
u32 sram_pdn_bits;
u32 sram_pdn_ack_bits;
const char *basic_clk_name[MAX_CLKS];
@@ -233,6 +238,14 @@ static int scpsys_sram_enable(struct scp_domain *scpd, void __iomem *ctl_addr)
return ret;
}
+ if (scpd->data->sram_iso_ctrl) {
+ val = readl(ctl_addr) | PWR_SRAM_ISOINT_B_BIT;
+ writel(val, ctl_addr);
+ udelay(1);
+ val &= ~PWR_SRAM_CLKISO_BIT;
+ writel(val, ctl_addr);
+ }
+
return 0;
}
@@ -242,8 +255,15 @@ static int scpsys_sram_disable(struct scp_domain *scpd, void __iomem *ctl_addr)
u32 pdn_ack = scpd->data->sram_pdn_ack_bits;
int tmp;
- val = readl(ctl_addr);
- val |= scpd->data->sram_pdn_bits;
+ if (scpd->data->sram_iso_ctrl) {
+ val = readl(ctl_addr) | PWR_SRAM_CLKISO_BIT;
+ writel(val, ctl_addr);
+ val &= ~PWR_SRAM_ISOINT_B_BIT;
+ writel(val, ctl_addr);
+ udelay(1);
+ }
+
+ val = readl(ctl_addr) | scpd->data->sram_pdn_bits;
writel(val, ctl_addr);
/* Either wait until SRAM_PDN_ACK all 1 or 0 */
--
1.8.1.1.dirty
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH v11 08/10] soc: mediatek: Add MT8183 scpsys support
2019-12-20 3:45 [PATCH v11 00/10] Mediatek MT8183 scpsys support Weiyi Lu
` (6 preceding siblings ...)
2019-12-20 3:46 ` [PATCH v11 07/10] soc: mediatek: Add extra sram control Weiyi Lu
@ 2019-12-20 3:46 ` Weiyi Lu
2019-12-20 5:11 ` Nicolas Boichat
2019-12-20 3:46 ` [PATCH v11 09/10] arm64: dts: Add power controller device node of MT8183 Weiyi Lu
` (2 subsequent siblings)
10 siblings, 1 reply; 33+ messages in thread
From: Weiyi Lu @ 2019-12-20 3:46 UTC (permalink / raw)
To: Nicolas Boichat, Matthias Brugger, Rob Herring, Sascha Hauer
Cc: James Liao, Fan Chen, linux-arm-kernel, linux-kernel,
linux-mediatek, srv_heupstream, Weiyi Lu
Add scpsys driver for MT8183
And minor fix to add a comma at the end
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
---
drivers/soc/mediatek/mtk-scpsys.c | 233 +++++++++++++++++++++++++++++++++++++-
drivers/soc/mediatek/scpsys-ext.h | 28 +++++
2 files changed, 255 insertions(+), 6 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
index 1972726..b8b72fa 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -19,6 +19,7 @@
#include <dt-bindings/power/mt7622-power.h>
#include <dt-bindings/power/mt7623a-power.h>
#include <dt-bindings/power/mt8173-power.h>
+#include <dt-bindings/power/mt8183-power.h>
#define MTK_POLL_DELAY_US 10
#define MTK_POLL_TIMEOUT USEC_PER_SEC
@@ -1082,12 +1083,218 @@ static void mtk_register_power_domains(struct platform_device *pdev,
{MT8173_POWER_DOMAIN_MFG_2D, MT8173_POWER_DOMAIN_MFG},
};
+/*
+ * MT8183 power domain support
+ */
+
+static const struct scp_domain_data scp_domain_data_mt8183[] = {
+ [MT8183_POWER_DOMAIN_AUDIO] = {
+ .name = "audio",
+ .sta_mask = PWR_STATUS_AUDIO,
+ .ctl_offs = 0x0314,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ .basic_clk_name = {"audio", "audio1", "audio2"},
+ },
+ [MT8183_POWER_DOMAIN_CONN] = {
+ .name = "conn",
+ .sta_mask = PWR_STATUS_CONN,
+ .ctl_offs = 0x032c,
+ .sram_pdn_bits = 0,
+ .sram_pdn_ack_bits = 0,
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0x2a0, 0x2a4, 0, 0x228,
+ MT8183_TOP_AXI_PROT_EN_CONN),
+ },
+ },
+ [MT8183_POWER_DOMAIN_MFG_ASYNC] = {
+ .name = "mfg_async",
+ .sta_mask = PWR_STATUS_MFG_ASYNC,
+ .ctl_offs = 0x0334,
+ .sram_pdn_bits = 0,
+ .sram_pdn_ack_bits = 0,
+ .basic_clk_name = {"mfg"},
+ },
+ [MT8183_POWER_DOMAIN_MFG] = {
+ .name = "mfg",
+ .sta_mask = PWR_STATUS_MFG,
+ .ctl_offs = 0x0338,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ },
+ [MT8183_POWER_DOMAIN_MFG_CORE0] = {
+ .name = "mfg_core0",
+ .sta_mask = BIT(7),
+ .ctl_offs = 0x034c,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ },
+ [MT8183_POWER_DOMAIN_MFG_CORE1] = {
+ .name = "mfg_core1",
+ .sta_mask = BIT(20),
+ .ctl_offs = 0x0310,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ },
+ [MT8183_POWER_DOMAIN_MFG_2D] = {
+ .name = "mfg_2d",
+ .sta_mask = PWR_STATUS_MFG_2D,
+ .ctl_offs = 0x0348,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0x2a8, 0x2ac, 0, 0x258,
+ MT8183_TOP_AXI_PROT_EN_1_MFG),
+ BUS_PROT(IFR_TYPE, 0x2a0, 0x2a4, 0, 0x228,
+ MT8183_TOP_AXI_PROT_EN_MFG),
+ },
+ },
+ [MT8183_POWER_DOMAIN_DISP] = {
+ .name = "disp",
+ .sta_mask = PWR_STATUS_DISP,
+ .ctl_offs = 0x030c,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .basic_clk_name = {"mm"},
+ .subsys_clk_prefix = "mm",
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0x2a8, 0x2ac, 0, 0x258,
+ MT8183_TOP_AXI_PROT_EN_1_DISP),
+ BUS_PROT(IFR_TYPE, 0x2a0, 0x2a4, 0, 0x228,
+ MT8183_TOP_AXI_PROT_EN_DISP),
+ BUS_PROT(SMI_TYPE, 0x3c4, 0x3c8, 0, 0x3c0,
+ MT8183_SMI_COMMON_SMI_CLAMP_DISP),
+ },
+ },
+ [MT8183_POWER_DOMAIN_CAM] = {
+ .name = "cam",
+ .sta_mask = BIT(25),
+ .ctl_offs = 0x0344,
+ .sram_pdn_bits = GENMASK(9, 8),
+ .sram_pdn_ack_bits = GENMASK(13, 12),
+ .basic_clk_name = {"cam"},
+ .subsys_clk_prefix = "cam",
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0, 0x2ec,
+ MT8183_TOP_AXI_PROT_EN_MM_CAM),
+ BUS_PROT(IFR_TYPE, 0x2a0, 0x2a4, 0, 0x228,
+ MT8183_TOP_AXI_PROT_EN_CAM),
+ BUS_PROT_IGN(IFR_TYPE, 0x2d4, 0x2d8, 0, 0x2ec,
+ MT8183_TOP_AXI_PROT_EN_MM_CAM_2ND),
+ BUS_PROT(SMI_TYPE, 0x3c4, 0x3c8, 0, 0x3c0,
+ MT8183_SMI_COMMON_SMI_CLAMP_CAM),
+ },
+ },
+ [MT8183_POWER_DOMAIN_ISP] = {
+ .name = "isp",
+ .sta_mask = PWR_STATUS_ISP,
+ .ctl_offs = 0x0308,
+ .sram_pdn_bits = GENMASK(9, 8),
+ .sram_pdn_ack_bits = GENMASK(13, 12),
+ .basic_clk_name = {"isp"},
+ .subsys_clk_prefix = "isp",
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0, 0x2ec,
+ MT8183_TOP_AXI_PROT_EN_MM_ISP),
+ BUS_PROT_IGN(IFR_TYPE, 0x2d4, 0x2d8, 0, 0x2ec,
+ MT8183_TOP_AXI_PROT_EN_MM_ISP_2ND),
+ BUS_PROT(SMI_TYPE, 0x3c4, 0x3c8, 0, 0x3c0,
+ MT8183_SMI_COMMON_SMI_CLAMP_ISP),
+ },
+ },
+ [MT8183_POWER_DOMAIN_VDEC] = {
+ .name = "vdec",
+ .sta_mask = BIT(31),
+ .ctl_offs = 0x0300,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .bp_table = {
+ BUS_PROT(SMI_TYPE, 0x3c4, 0x3c8, 0, 0x3c0,
+ MT8183_SMI_COMMON_SMI_CLAMP_VDEC),
+ },
+ },
+ [MT8183_POWER_DOMAIN_VENC] = {
+ .name = "venc",
+ .sta_mask = PWR_STATUS_VENC,
+ .ctl_offs = 0x0304,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ .bp_table = {
+ BUS_PROT(SMI_TYPE, 0x3c4, 0x3c8, 0, 0x3c0,
+ MT8183_SMI_COMMON_SMI_CLAMP_VENC),
+ },
+ },
+ [MT8183_POWER_DOMAIN_VPU_TOP] = {
+ .name = "vpu_top",
+ .sta_mask = BIT(26),
+ .ctl_offs = 0x0324,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .basic_clk_name = {"vpu", "vpu1"},
+ .subsys_clk_prefix = "vpu",
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0, 0x2ec,
+ MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP),
+ BUS_PROT(IFR_TYPE, 0x2a0, 0x2a4, 0, 0x228,
+ MT8183_TOP_AXI_PROT_EN_VPU_TOP),
+ BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0, 0x2ec,
+ MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP_2ND),
+ BUS_PROT(SMI_TYPE, 0x3c4, 0x3c8, 0, 0x3c0,
+ MT8183_SMI_COMMON_SMI_CLAMP_VPU_TOP),
+ },
+ },
+ [MT8183_POWER_DOMAIN_VPU_CORE0] = {
+ .name = "vpu_core0",
+ .sta_mask = BIT(27),
+ .ctl_offs = 0x33c,
+ .sram_iso_ctrl = true,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(13, 12),
+ .basic_clk_name = {"vpu2"},
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0x2c4, 0x2c8, 0, 0x2e4,
+ MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0),
+ BUS_PROT(IFR_TYPE, 0x2c4, 0x2c8, 0, 0x2e4,
+ MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0_2ND),
+ },
+ },
+ [MT8183_POWER_DOMAIN_VPU_CORE1] = {
+ .name = "vpu_core1",
+ .sta_mask = BIT(28),
+ .ctl_offs = 0x0340,
+ .sram_iso_ctrl = true,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(13, 12),
+ .basic_clk_name = {"vpu3"},
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0x2c4, 0x2c8, 0, 0x2e4,
+ MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1),
+ BUS_PROT(IFR_TYPE, 0x2c4, 0x2c8, 0, 0x2e4,
+ MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1_2ND),
+ },
+ },
+};
+
+static const struct scp_subdomain scp_subdomain_mt8183[] = {
+ {MT8183_POWER_DOMAIN_MFG_ASYNC, MT8183_POWER_DOMAIN_MFG},
+ {MT8183_POWER_DOMAIN_MFG, MT8183_POWER_DOMAIN_MFG_2D},
+ {MT8183_POWER_DOMAIN_MFG, MT8183_POWER_DOMAIN_MFG_CORE0},
+ {MT8183_POWER_DOMAIN_MFG, MT8183_POWER_DOMAIN_MFG_CORE1},
+ {MT8183_POWER_DOMAIN_DISP, MT8183_POWER_DOMAIN_CAM},
+ {MT8183_POWER_DOMAIN_DISP, MT8183_POWER_DOMAIN_ISP},
+ {MT8183_POWER_DOMAIN_DISP, MT8183_POWER_DOMAIN_VDEC},
+ {MT8183_POWER_DOMAIN_DISP, MT8183_POWER_DOMAIN_VENC},
+ {MT8183_POWER_DOMAIN_DISP, MT8183_POWER_DOMAIN_VPU_TOP},
+ {MT8183_POWER_DOMAIN_VPU_TOP, MT8183_POWER_DOMAIN_VPU_CORE0},
+ {MT8183_POWER_DOMAIN_VPU_TOP, MT8183_POWER_DOMAIN_VPU_CORE1},
+};
+
static const struct scp_soc_data mt2701_data = {
.domains = scp_domain_data_mt2701,
.num_domains = ARRAY_SIZE(scp_domain_data_mt2701),
.regs = {
.pwr_sta_offs = SPM_PWR_STATUS,
- .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
+ .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
},
};
@@ -1098,7 +1305,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.num_subdomains = ARRAY_SIZE(scp_subdomain_mt2712),
.regs = {
.pwr_sta_offs = SPM_PWR_STATUS,
- .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
+ .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
},
};
@@ -1109,7 +1316,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.num_subdomains = ARRAY_SIZE(scp_subdomain_mt6797),
.regs = {
.pwr_sta_offs = SPM_PWR_STATUS_MT6797,
- .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND_MT6797
+ .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND_MT6797,
},
};
@@ -1118,7 +1325,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.num_domains = ARRAY_SIZE(scp_domain_data_mt7622),
.regs = {
.pwr_sta_offs = SPM_PWR_STATUS,
- .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
+ .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
},
};
@@ -1127,7 +1334,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.num_domains = ARRAY_SIZE(scp_domain_data_mt7623a),
.regs = {
.pwr_sta_offs = SPM_PWR_STATUS,
- .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
+ .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
},
};
@@ -1138,10 +1345,21 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.num_subdomains = ARRAY_SIZE(scp_subdomain_mt8173),
.regs = {
.pwr_sta_offs = SPM_PWR_STATUS,
- .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
+ .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
},
};
+static const struct scp_soc_data mt8183_data = {
+ .domains = scp_domain_data_mt8183,
+ .num_domains = ARRAY_SIZE(scp_domain_data_mt8183),
+ .subdomains = scp_subdomain_mt8183,
+ .num_subdomains = ARRAY_SIZE(scp_subdomain_mt8183),
+ .regs = {
+ .pwr_sta_offs = 0x0180,
+ .pwr_sta2nd_offs = 0x0184,
+ }
+};
+
/*
* scpsys driver init
*/
@@ -1166,6 +1384,9 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.compatible = "mediatek,mt8173-scpsys",
.data = &mt8173_data,
}, {
+ .compatible = "mediatek,mt8183-scpsys",
+ .data = &mt8183_data,
+ }, {
/* sentinel */
}
};
diff --git a/drivers/soc/mediatek/scpsys-ext.h b/drivers/soc/mediatek/scpsys-ext.h
index 458b2c5..0f90e5d 100644
--- a/drivers/soc/mediatek/scpsys-ext.h
+++ b/drivers/soc/mediatek/scpsys-ext.h
@@ -43,6 +43,34 @@
#define MT8173_TOP_AXI_PROT_EN_MFG_M1 BIT(22)
#define MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT BIT(23)
+#define MT8183_TOP_AXI_PROT_EN_DISP (BIT(10) | BIT(11))
+#define MT8183_TOP_AXI_PROT_EN_CONN (BIT(13) | BIT(14))
+#define MT8183_TOP_AXI_PROT_EN_MFG (BIT(21) | BIT(22))
+#define MT8183_TOP_AXI_PROT_EN_CAM BIT(28)
+#define MT8183_TOP_AXI_PROT_EN_VPU_TOP BIT(27)
+#define MT8183_TOP_AXI_PROT_EN_1_DISP (BIT(16) | BIT(17))
+#define MT8183_TOP_AXI_PROT_EN_1_MFG GENMASK(21, 19)
+#define MT8183_TOP_AXI_PROT_EN_MM_ISP (BIT(3) | BIT(8))
+#define MT8183_TOP_AXI_PROT_EN_MM_ISP_2ND BIT(10)
+#define MT8183_TOP_AXI_PROT_EN_MM_CAM (BIT(4) | BIT(5) | \
+ BIT(9) | BIT(13))
+#define MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP (GENMASK(9, 6) | \
+ BIT(12))
+#define MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP_2ND (BIT(10) | BIT(11))
+#define MT8183_TOP_AXI_PROT_EN_MM_CAM_2ND BIT(11)
+#define MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0_2ND (BIT(0) | BIT(2) | \
+ BIT(4))
+#define MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1_2ND (BIT(1) | BIT(3) | \
+ BIT(5))
+#define MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0 BIT(6)
+#define MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1 BIT(7)
+#define MT8183_SMI_COMMON_SMI_CLAMP_DISP GENMASK(7, 0)
+#define MT8183_SMI_COMMON_SMI_CLAMP_VENC BIT(1)
+#define MT8183_SMI_COMMON_SMI_CLAMP_ISP BIT(2)
+#define MT8183_SMI_COMMON_SMI_CLAMP_CAM (BIT(3) | BIT(4))
+#define MT8183_SMI_COMMON_SMI_CLAMP_VPU_TOP (BIT(5) | BIT(6))
+#define MT8183_SMI_COMMON_SMI_CLAMP_VDEC BIT(7)
+
enum regmap_type {
INVALID_TYPE = 0,
IFR_TYPE,
--
1.8.1.1.dirty
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH v11 09/10] arm64: dts: Add power controller device node of MT8183
2019-12-20 3:45 [PATCH v11 00/10] Mediatek MT8183 scpsys support Weiyi Lu
` (7 preceding siblings ...)
2019-12-20 3:46 ` [PATCH v11 08/10] soc: mediatek: Add MT8183 scpsys support Weiyi Lu
@ 2019-12-20 3:46 ` Weiyi Lu
2019-12-20 3:46 ` [PATCH v11 10/10] arm64: dts: Add power-domains properity to mfgcfg Weiyi Lu
2019-12-27 1:43 ` [PATCH v11 00/10] Mediatek MT8183 scpsys support Weiyi Lu
10 siblings, 0 replies; 33+ messages in thread
From: Weiyi Lu @ 2019-12-20 3:46 UTC (permalink / raw)
To: Nicolas Boichat, Matthias Brugger, Rob Herring, Sascha Hauer
Cc: James Liao, Fan Chen, linux-arm-kernel, linux-kernel,
linux-mediatek, srv_heupstream, Weiyi Lu
Add power controller node and smi-common node for MT8183
In scpsys node, it contains clocks and regmapping of
infracfg and smi-common for bus protection.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 62 ++++++++++++++++++++++++++++++++
1 file changed, 62 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 10b3247..91217e4f 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/clock/mt8183-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/power/mt8183-power.h>
#include "mt8183-pinfunc.h"
/ {
@@ -253,6 +254,62 @@
#interrupt-cells = <2>;
};
+ scpsys: syscon@10006000 {
+ compatible = "mediatek,mt8183-scpsys", "syscon";
+ #power-domain-cells = <1>;
+ reg = <0 0x10006000 0 0x1000>;
+ clocks = <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
+ <&infracfg CLK_INFRA_AUDIO>,
+ <&infracfg CLK_INFRA_AUDIO_26M_BCLK>,
+ <&topckgen CLK_TOP_MUX_MFG>,
+ <&topckgen CLK_TOP_MUX_MM>,
+ <&topckgen CLK_TOP_MUX_CAM>,
+ <&topckgen CLK_TOP_MUX_IMG>,
+ <&topckgen CLK_TOP_MUX_IPU_IF>,
+ <&topckgen CLK_TOP_MUX_DSP>,
+ <&topckgen CLK_TOP_MUX_DSP1>,
+ <&topckgen CLK_TOP_MUX_DSP2>,
+ <&mmsys CLK_MM_SMI_COMMON>,
+ <&mmsys CLK_MM_SMI_LARB0>,
+ <&mmsys CLK_MM_SMI_LARB1>,
+ <&mmsys CLK_MM_GALS_COMM0>,
+ <&mmsys CLK_MM_GALS_COMM1>,
+ <&mmsys CLK_MM_GALS_CCU2MM>,
+ <&mmsys CLK_MM_GALS_IPU12MM>,
+ <&mmsys CLK_MM_GALS_IMG2MM>,
+ <&mmsys CLK_MM_GALS_CAM2MM>,
+ <&mmsys CLK_MM_GALS_IPU2MM>,
+ <&imgsys CLK_IMG_LARB5>,
+ <&imgsys CLK_IMG_LARB2>,
+ <&camsys CLK_CAM_LARB6>,
+ <&camsys CLK_CAM_LARB3>,
+ <&camsys CLK_CAM_SENINF>,
+ <&camsys CLK_CAM_CAMSV0>,
+ <&camsys CLK_CAM_CAMSV1>,
+ <&camsys CLK_CAM_CAMSV2>,
+ <&camsys CLK_CAM_CCU>,
+ <&ipu_conn CLK_IPU_CONN_IPU>,
+ <&ipu_conn CLK_IPU_CONN_AHB>,
+ <&ipu_conn CLK_IPU_CONN_AXI>,
+ <&ipu_conn CLK_IPU_CONN_ISP>,
+ <&ipu_conn CLK_IPU_CONN_CAM_ADL>,
+ <&ipu_conn CLK_IPU_CONN_IMG_ADL>;
+ clock-names = "audio", "audio1", "audio2",
+ "mfg", "mm", "cam",
+ "isp", "vpu", "vpu1",
+ "vpu2", "vpu3", "mm-0",
+ "mm-1", "mm-2", "mm-3",
+ "mm-4", "mm-5", "mm-6",
+ "mm-7", "mm-8", "mm-9",
+ "isp-0", "isp-1", "cam-0",
+ "cam-1", "cam-2", "cam-3",
+ "cam-4", "cam-5", "cam-6",
+ "vpu-0", "vpu-1", "vpu-2",
+ "vpu-3", "vpu-4", "vpu-5";
+ infracfg = <&infracfg>;
+ smi_comm = <&smi_common>;
+ };
+
apmixedsys: syscon@1000c000 {
compatible = "mediatek,mt8183-apmixedsys", "syscon";
reg = <0 0x1000c000 0 0x1000>;
@@ -594,6 +651,11 @@
#clock-cells = <1>;
};
+ smi_common: smi@14019000 {
+ compatible = "mediatek,mt8183-smi-common", "syscon";
+ reg = <0 0x14019000 0 0x1000>;
+ };
+
imgsys: syscon@15020000 {
compatible = "mediatek,mt8183-imgsys", "syscon";
reg = <0 0x15020000 0 0x1000>;
--
1.8.1.1.dirty
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH v11 10/10] arm64: dts: Add power-domains properity to mfgcfg
2019-12-20 3:45 [PATCH v11 00/10] Mediatek MT8183 scpsys support Weiyi Lu
` (8 preceding siblings ...)
2019-12-20 3:46 ` [PATCH v11 09/10] arm64: dts: Add power controller device node of MT8183 Weiyi Lu
@ 2019-12-20 3:46 ` Weiyi Lu
2019-12-27 1:43 ` [PATCH v11 00/10] Mediatek MT8183 scpsys support Weiyi Lu
10 siblings, 0 replies; 33+ messages in thread
From: Weiyi Lu @ 2019-12-20 3:46 UTC (permalink / raw)
To: Nicolas Boichat, Matthias Brugger, Rob Herring, Sascha Hauer
Cc: James Liao, Fan Chen, linux-arm-kernel, linux-kernel,
linux-mediatek, srv_heupstream, Weiyi Lu
mfgcfg clock is under MFG_ASYNC power domain
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 91217e4f..40145dc 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -643,6 +643,7 @@
compatible = "mediatek,mt8183-mfgcfg", "syscon";
reg = <0 0x13000000 0 0x1000>;
#clock-cells = <1>;
+ power-domains = <&scpsys MT8183_POWER_DOMAIN_MFG_ASYNC>;
};
mmsys: syscon@14000000 {
--
1.8.1.1.dirty
^ permalink raw reply related [flat|nested] 33+ messages in thread
* Re: [PATCH v11 03/10] soc: mediatek: Add basic_clk_name to scp_power_data
2019-12-20 3:45 ` [PATCH v11 03/10] soc: mediatek: Add basic_clk_name to scp_power_data Weiyi Lu
@ 2019-12-20 4:05 ` Nicolas Boichat
0 siblings, 0 replies; 33+ messages in thread
From: Nicolas Boichat @ 2019-12-20 4:05 UTC (permalink / raw)
To: Weiyi Lu
Cc: Matthias Brugger, Rob Herring, Sascha Hauer, James Liao,
Fan Chen, linux-arm Mailing List, lkml,
moderated list:ARM/Mediatek SoC support, srv_heupstream
On Fri, Dec 20, 2019 at 11:46 AM Weiyi Lu <weiyi.lu@mediatek.com> wrote:
>
> Try to stop extending the clk_id or clk_names if there are
> more and more new BASIC clocks. To get its own clocks by the
> basic_clk_name of each power domain.
> And then use basic_clk_name strings for all compatibles, instead of
> mixing clk_id and clk_name.
>
> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Looks good, thanks!
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
> ---
> drivers/soc/mediatek/mtk-scpsys.c | 138 +++++++++++++-------------------------
> 1 file changed, 45 insertions(+), 93 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
> index f669d37..db35a28 100644
> --- a/drivers/soc/mediatek/mtk-scpsys.c
> +++ b/drivers/soc/mediatek/mtk-scpsys.c
> @@ -78,34 +78,6 @@
> #define PWR_STATUS_HIF1 BIT(26) /* MT7622 */
> #define PWR_STATUS_WB BIT(27) /* MT7622 */
>
> -enum clk_id {
> - CLK_NONE,
> - CLK_MM,
> - CLK_MFG,
> - CLK_VENC,
> - CLK_VENC_LT,
> - CLK_ETHIF,
> - CLK_VDEC,
> - CLK_HIFSEL,
> - CLK_JPGDEC,
> - CLK_AUDIO,
> - CLK_MAX,
> -};
> -
> -static const char * const clk_names[] = {
> - NULL,
> - "mm",
> - "mfg",
> - "venc",
> - "venc_lt",
> - "ethif",
> - "vdec",
> - "hif_sel",
> - "jpgdec",
> - "audio",
> - NULL,
> -};
> -
> #define MAX_CLKS 3
>
> /**
> @@ -116,7 +88,7 @@ enum clk_id {
> * @sram_pdn_bits: The mask for sram power control bits.
> * @sram_pdn_ack_bits: The mask for sram power control acked bits.
> * @bus_prot_mask: The mask for single step bus protection.
> - * @clk_id: The basic clocks required by this power domain.
> + * @basic_clk_name: The basic clocks required by this power domain.
> * @caps: The flag for active wake-up action.
> */
> struct scp_domain_data {
> @@ -126,7 +98,7 @@ struct scp_domain_data {
> u32 sram_pdn_bits;
> u32 sram_pdn_ack_bits;
> u32 bus_prot_mask;
> - enum clk_id clk_id[MAX_CLKS];
> + const char *basic_clk_name[MAX_CLKS];
> u8 caps;
> };
>
> @@ -411,12 +383,23 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
> return ret;
> }
>
> -static void init_clks(struct platform_device *pdev, struct clk **clk)
> +static int init_basic_clks(struct platform_device *pdev, struct clk **clk,
> + const char * const *name)
> {
> int i;
>
> - for (i = CLK_NONE + 1; i < CLK_MAX; i++)
> - clk[i] = devm_clk_get(&pdev->dev, clk_names[i]);
> + for (i = 0; i < MAX_CLKS && name[i]; i++) {
> + clk[i] = devm_clk_get(&pdev->dev, name[i]);
> +
> + if (IS_ERR(clk[i])) {
> + dev_err(&pdev->dev,
> + "get basic clk %s fail %ld\n",
> + name[i], PTR_ERR(clk[i]));
> + return PTR_ERR(clk[i]);
> + }
> + }
> +
> + return 0;
> }
>
> static struct scp *init_scp(struct platform_device *pdev,
> @@ -426,9 +409,8 @@ static struct scp *init_scp(struct platform_device *pdev,
> {
> struct genpd_onecell_data *pd_data;
> struct resource *res;
> - int i, j;
> + int i, ret;
> struct scp *scp;
> - struct clk *clk[CLK_MAX];
>
> scp = devm_kzalloc(&pdev->dev, sizeof(*scp), GFP_KERNEL);
> if (!scp)
> @@ -481,8 +463,6 @@ static struct scp *init_scp(struct platform_device *pdev,
>
> pd_data->num_domains = num;
>
> - init_clks(pdev, clk);
> -
> for (i = 0; i < num; i++) {
> struct scp_domain *scpd = &scp->domains[i];
> struct generic_pm_domain *genpd = &scpd->genpd;
> @@ -493,17 +473,9 @@ static struct scp *init_scp(struct platform_device *pdev,
>
> scpd->data = data;
>
> - for (j = 0; j < MAX_CLKS && data->clk_id[j]; j++) {
> - struct clk *c = clk[data->clk_id[j]];
> -
> - if (IS_ERR(c)) {
> - dev_err(&pdev->dev, "%s: clk unavailable\n",
> - data->name);
> - return ERR_CAST(c);
> - }
> -
> - scpd->clk[j] = c;
> - }
> + ret = init_basic_clks(pdev, scpd->clk, data->basic_clk_name);
> + if (ret)
> + return ERR_PTR(ret);
>
> genpd->name = data->name;
> genpd->power_off = scpsys_power_off;
> @@ -560,7 +532,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_CONN_PWR_CON,
> .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_CONN_M |
> MT2701_TOP_AXI_PROT_EN_CONN_S,
> - .clk_id = {CLK_NONE},
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> [MT2701_POWER_DOMAIN_DISP] = {
> @@ -568,7 +539,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .sta_mask = PWR_STATUS_DISP,
> .ctl_offs = SPM_DIS_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> - .clk_id = {CLK_MM},
> + .basic_clk_name = {"mm"},
> .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_MM_M0,
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> @@ -578,7 +549,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_MFG_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = GENMASK(12, 12),
> - .clk_id = {CLK_MFG},
> + .basic_clk_name = {"mfg"},
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> [MT2701_POWER_DOMAIN_VDEC] = {
> @@ -587,7 +558,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_VDE_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = GENMASK(12, 12),
> - .clk_id = {CLK_MM},
> + .basic_clk_name = {"mm"},
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> [MT2701_POWER_DOMAIN_ISP] = {
> @@ -596,7 +567,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_ISP_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = GENMASK(13, 12),
> - .clk_id = {CLK_MM},
> + .basic_clk_name = {"mm"},
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> [MT2701_POWER_DOMAIN_BDP] = {
> @@ -604,7 +575,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .sta_mask = PWR_STATUS_BDP,
> .ctl_offs = SPM_BDP_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> - .clk_id = {CLK_NONE},
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> [MT2701_POWER_DOMAIN_ETH] = {
> @@ -613,7 +583,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_ETH_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = GENMASK(15, 12),
> - .clk_id = {CLK_ETHIF},
> + .basic_clk_name = {"ethif"},
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> [MT2701_POWER_DOMAIN_HIF] = {
> @@ -622,14 +592,13 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_HIF_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = GENMASK(15, 12),
> - .clk_id = {CLK_ETHIF},
> + .basic_clk_name = {"ethif"},
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> [MT2701_POWER_DOMAIN_IFR_MSC] = {
> .name = "ifr_msc",
> .sta_mask = PWR_STATUS_IFR_MSC,
> .ctl_offs = SPM_IFR_MSC_PWR_CON,
> - .clk_id = {CLK_NONE},
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> };
> @@ -644,7 +613,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_DIS_PWR_CON,
> .sram_pdn_bits = GENMASK(8, 8),
> .sram_pdn_ack_bits = GENMASK(12, 12),
> - .clk_id = {CLK_MM},
> + .basic_clk_name = {"mm"},
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> [MT2712_POWER_DOMAIN_VDEC] = {
> @@ -653,7 +622,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_VDE_PWR_CON,
> .sram_pdn_bits = GENMASK(8, 8),
> .sram_pdn_ack_bits = GENMASK(12, 12),
> - .clk_id = {CLK_MM, CLK_VDEC},
> + .basic_clk_name = {"mm", "vdec"},
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> [MT2712_POWER_DOMAIN_VENC] = {
> @@ -662,7 +631,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_VEN_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = GENMASK(15, 12),
> - .clk_id = {CLK_MM, CLK_VENC, CLK_JPGDEC},
> + .basic_clk_name = {"mm", "venc", "jpgdec"},
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> [MT2712_POWER_DOMAIN_ISP] = {
> @@ -671,7 +640,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_ISP_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = GENMASK(13, 12),
> - .clk_id = {CLK_MM},
> + .basic_clk_name = {"mm"},
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> [MT2712_POWER_DOMAIN_AUDIO] = {
> @@ -680,7 +649,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_AUDIO_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = GENMASK(15, 12),
> - .clk_id = {CLK_AUDIO},
> + .basic_clk_name = {"audio"},
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> [MT2712_POWER_DOMAIN_USB] = {
> @@ -689,7 +658,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_USB_PWR_CON,
> .sram_pdn_bits = GENMASK(10, 8),
> .sram_pdn_ack_bits = GENMASK(14, 12),
> - .clk_id = {CLK_NONE},
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> [MT2712_POWER_DOMAIN_USB2] = {
> @@ -698,7 +666,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_USB2_PWR_CON,
> .sram_pdn_bits = GENMASK(10, 8),
> .sram_pdn_ack_bits = GENMASK(14, 12),
> - .clk_id = {CLK_NONE},
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> [MT2712_POWER_DOMAIN_MFG] = {
> @@ -707,7 +674,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_MFG_PWR_CON,
> .sram_pdn_bits = GENMASK(8, 8),
> .sram_pdn_ack_bits = GENMASK(16, 16),
> - .clk_id = {CLK_MFG},
> + .basic_clk_name = {"mfg"},
> .bus_prot_mask = BIT(14) | BIT(21) | BIT(23),
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> @@ -717,7 +684,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = 0x02c0,
> .sram_pdn_bits = GENMASK(8, 8),
> .sram_pdn_ack_bits = GENMASK(16, 16),
> - .clk_id = {CLK_NONE},
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> [MT2712_POWER_DOMAIN_MFG_SC2] = {
> @@ -726,7 +692,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = 0x02c4,
> .sram_pdn_bits = GENMASK(8, 8),
> .sram_pdn_ack_bits = GENMASK(16, 16),
> - .clk_id = {CLK_NONE},
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> [MT2712_POWER_DOMAIN_MFG_SC3] = {
> @@ -735,7 +700,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = 0x01f8,
> .sram_pdn_bits = GENMASK(8, 8),
> .sram_pdn_ack_bits = GENMASK(16, 16),
> - .clk_id = {CLK_NONE},
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> };
> @@ -760,7 +724,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = 0x300,
> .sram_pdn_bits = GENMASK(8, 8),
> .sram_pdn_ack_bits = GENMASK(12, 12),
> - .clk_id = {CLK_VDEC},
> + .basic_clk_name = {"vdec"},
> },
> [MT6797_POWER_DOMAIN_VENC] = {
> .name = "venc",
> @@ -768,7 +732,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = 0x304,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = GENMASK(15, 12),
> - .clk_id = {CLK_NONE},
> },
> [MT6797_POWER_DOMAIN_ISP] = {
> .name = "isp",
> @@ -776,7 +739,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = 0x308,
> .sram_pdn_bits = GENMASK(9, 8),
> .sram_pdn_ack_bits = GENMASK(13, 12),
> - .clk_id = {CLK_NONE},
> },
> [MT6797_POWER_DOMAIN_MM] = {
> .name = "mm",
> @@ -784,7 +746,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = 0x30C,
> .sram_pdn_bits = GENMASK(8, 8),
> .sram_pdn_ack_bits = GENMASK(12, 12),
> - .clk_id = {CLK_MM},
> + .basic_clk_name = {"mm"},
> .bus_prot_mask = (BIT(1) | BIT(2)),
> },
> [MT6797_POWER_DOMAIN_AUDIO] = {
> @@ -793,7 +755,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = 0x314,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = GENMASK(15, 12),
> - .clk_id = {CLK_NONE},
> },
> [MT6797_POWER_DOMAIN_MFG_ASYNC] = {
> .name = "mfg_async",
> @@ -801,7 +762,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = 0x334,
> .sram_pdn_bits = 0,
> .sram_pdn_ack_bits = 0,
> - .clk_id = {CLK_MFG},
> + .basic_clk_name = {"mfg"},
> },
> [MT6797_POWER_DOMAIN_MJC] = {
> .name = "mjc",
> @@ -809,7 +770,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = 0x310,
> .sram_pdn_bits = GENMASK(8, 8),
> .sram_pdn_ack_bits = GENMASK(12, 12),
> - .clk_id = {CLK_NONE},
> },
> };
>
> @@ -834,7 +794,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_ETHSYS_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = GENMASK(15, 12),
> - .clk_id = {CLK_NONE},
> .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_ETHSYS,
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> @@ -844,7 +803,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_HIF0_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = GENMASK(15, 12),
> - .clk_id = {CLK_HIFSEL},
> + .basic_clk_name = {"hif_sel"},
> .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_HIF0,
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> @@ -854,7 +813,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_HIF1_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = GENMASK(15, 12),
> - .clk_id = {CLK_HIFSEL},
> + .basic_clk_name = {"hif_sel"},
> .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_HIF1,
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> @@ -864,7 +823,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_WB_PWR_CON,
> .sram_pdn_bits = 0,
> .sram_pdn_ack_bits = 0,
> - .clk_id = {CLK_NONE},
> .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_WB,
> .caps = MTK_SCPD_ACTIVE_WAKEUP | MTK_SCPD_FWAIT_SRAM,
> },
> @@ -881,7 +839,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_CONN_PWR_CON,
> .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_CONN_M |
> MT2701_TOP_AXI_PROT_EN_CONN_S,
> - .clk_id = {CLK_NONE},
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> [MT7623A_POWER_DOMAIN_ETH] = {
> @@ -890,7 +847,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_ETH_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = GENMASK(15, 12),
> - .clk_id = {CLK_ETHIF},
> + .basic_clk_name = {"ethif"},
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> [MT7623A_POWER_DOMAIN_HIF] = {
> @@ -899,14 +856,13 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_HIF_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = GENMASK(15, 12),
> - .clk_id = {CLK_ETHIF},
> + .basic_clk_name = {"ethif"},
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> [MT7623A_POWER_DOMAIN_IFR_MSC] = {
> .name = "ifr_msc",
> .sta_mask = PWR_STATUS_IFR_MSC,
> .ctl_offs = SPM_IFR_MSC_PWR_CON,
> - .clk_id = {CLK_NONE},
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> };
> @@ -922,7 +878,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_VDE_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = GENMASK(12, 12),
> - .clk_id = {CLK_MM},
> + .basic_clk_name = {"mm"},
> },
> [MT8173_POWER_DOMAIN_VENC] = {
> .name = "venc",
> @@ -930,7 +886,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_VEN_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = GENMASK(15, 12),
> - .clk_id = {CLK_MM, CLK_VENC},
> + .basic_clk_name = {"mm", "venc"},
> },
> [MT8173_POWER_DOMAIN_ISP] = {
> .name = "isp",
> @@ -938,7 +894,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_ISP_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = GENMASK(13, 12),
> - .clk_id = {CLK_MM},
> + .basic_clk_name = {"mm"},
> },
> [MT8173_POWER_DOMAIN_MM] = {
> .name = "mm",
> @@ -946,7 +902,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_DIS_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = GENMASK(12, 12),
> - .clk_id = {CLK_MM},
> + .basic_clk_name = {"mm"},
> .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 |
> MT8173_TOP_AXI_PROT_EN_MM_M1,
> },
> @@ -956,7 +912,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_VEN2_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = GENMASK(15, 12),
> - .clk_id = {CLK_MM, CLK_VENC_LT},
> + .basic_clk_name = {"mm", "venc_lt"},
> },
> [MT8173_POWER_DOMAIN_AUDIO] = {
> .name = "audio",
> @@ -964,7 +920,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_AUDIO_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = GENMASK(15, 12),
> - .clk_id = {CLK_NONE},
> },
> [MT8173_POWER_DOMAIN_USB] = {
> .name = "usb",
> @@ -972,7 +927,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_USB_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = GENMASK(15, 12),
> - .clk_id = {CLK_NONE},
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> [MT8173_POWER_DOMAIN_MFG_ASYNC] = {
> @@ -981,7 +935,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_MFG_ASYNC_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = 0,
> - .clk_id = {CLK_MFG},
> + .basic_clk_name = {"mfg"},
> },
> [MT8173_POWER_DOMAIN_MFG_2D] = {
> .name = "mfg_2d",
> @@ -989,7 +943,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_MFG_2D_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = GENMASK(13, 12),
> - .clk_id = {CLK_NONE},
> },
> [MT8173_POWER_DOMAIN_MFG] = {
> .name = "mfg",
> @@ -997,7 +950,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_MFG_PWR_CON,
> .sram_pdn_bits = GENMASK(13, 8),
> .sram_pdn_ack_bits = GENMASK(21, 16),
> - .clk_id = {CLK_NONE},
> .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MFG_S |
> MT8173_TOP_AXI_PROT_EN_MFG_M0 |
> MT8173_TOP_AXI_PROT_EN_MFG_M1 |
> --
> 1.8.1.1.dirty
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v11 04/10] soc: mediatek: Add multiple step bus protection control
2019-12-20 3:45 ` [PATCH v11 04/10] soc: mediatek: Add multiple step bus protection control Weiyi Lu
@ 2019-12-20 4:09 ` Nicolas Boichat
2020-02-11 17:49 ` Matthias Brugger
1 sibling, 0 replies; 33+ messages in thread
From: Nicolas Boichat @ 2019-12-20 4:09 UTC (permalink / raw)
To: Weiyi Lu
Cc: Matthias Brugger, Rob Herring, Sascha Hauer, James Liao,
Fan Chen, linux-arm Mailing List, lkml,
moderated list:ARM/Mediatek SoC support, srv_heupstream
On Fri, Dec 20, 2019 at 11:46 AM Weiyi Lu <weiyi.lu@mediatek.com> wrote:
>
> Both MT8183 & MT6765 have more control steps of bus protection
> than previous project. And there add more bus protection registers
> reside at infracfg & smi-common. Also add new APIs for multiple
> step bus protection control with more customized arguments.
> And then use bp_table for bus protection of all compatibles,
> instead of mixing bus_prot_mask and bus_prot_reg_update.
>
> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
I think this looks much better, thanks!
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
> ---
> drivers/soc/mediatek/Makefile | 2 +-
> drivers/soc/mediatek/mtk-scpsys-ext.c | 101 +++++++++++++++++++++++++++++
> drivers/soc/mediatek/mtk-scpsys.c | 117 +++++++++++++++++++++-------------
> drivers/soc/mediatek/scpsys-ext.h | 67 +++++++++++++++++++
> 4 files changed, 240 insertions(+), 47 deletions(-)
> create mode 100644 drivers/soc/mediatek/mtk-scpsys-ext.c
> create mode 100644 drivers/soc/mediatek/scpsys-ext.h
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v11 05/10] soc: mediatek: Remove infracfg misc driver support
2019-12-20 3:45 ` [PATCH v11 05/10] soc: mediatek: Remove infracfg misc driver support Weiyi Lu
@ 2019-12-20 4:11 ` Nicolas Boichat
2019-12-20 5:00 ` Weiyi Lu
0 siblings, 1 reply; 33+ messages in thread
From: Nicolas Boichat @ 2019-12-20 4:11 UTC (permalink / raw)
To: Weiyi Lu
Cc: Matthias Brugger, Rob Herring, Sascha Hauer, James Liao,
Fan Chen, linux-arm Mailing List, lkml,
moderated list:ARM/Mediatek SoC support, srv_heupstream
On Fri, Dec 20, 2019 at 11:46 AM Weiyi Lu <weiyi.lu@mediatek.com> wrote:
>
> In previous patches, we introduce scpsys-ext driver that covers
> the functions which infracfg misc driver provided.
> And then replace bus_prot_mask with bp_table of all compatibles.
> Now, we're going to remove infracfg misc drvier which is no longer
> being used.
>
> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> ---
> drivers/soc/mediatek/Kconfig | 10 -----
> drivers/soc/mediatek/Makefile | 3 +-
> drivers/soc/mediatek/mtk-infracfg.c | 79 -----------------------------------
> include/linux/soc/mediatek/infracfg.h | 39 -----------------
> 4 files changed, 1 insertion(+), 130 deletions(-)
> delete mode 100644 drivers/soc/mediatek/mtk-infracfg.c
> delete mode 100644 include/linux/soc/mediatek/infracfg.h
> [snip]
> diff --git a/include/linux/soc/mediatek/infracfg.h b/include/linux/soc/mediatek/infracfg.h
> deleted file mode 100644
> index fd25f01..0000000
> --- a/include/linux/soc/mediatek/infracfg.h
> +++ /dev/null
> @@ -1,39 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0 */
> -#ifndef __SOC_MEDIATEK_INFRACFG_H
> -#define __SOC_MEDIATEK_INFRACFG_H
> -
> -#define MT8173_TOP_AXI_PROT_EN_MCI_M2 BIT(0)
> -#define MT8173_TOP_AXI_PROT_EN_MM_M0 BIT(1)
> -#define MT8173_TOP_AXI_PROT_EN_MM_M1 BIT(2)
> -#define MT8173_TOP_AXI_PROT_EN_MMAPB_S BIT(6)
> -#define MT8173_TOP_AXI_PROT_EN_L2C_M2 BIT(9)
> -#define MT8173_TOP_AXI_PROT_EN_L2SS_SMI BIT(11)
> -#define MT8173_TOP_AXI_PROT_EN_L2SS_ADD BIT(12)
> -#define MT8173_TOP_AXI_PROT_EN_CCI_M2 BIT(13)
> -#define MT8173_TOP_AXI_PROT_EN_MFG_S BIT(14)
> -#define MT8173_TOP_AXI_PROT_EN_PERI_M0 BIT(15)
> -#define MT8173_TOP_AXI_PROT_EN_PERI_M1 BIT(16)
> -#define MT8173_TOP_AXI_PROT_EN_DEBUGSYS BIT(17)
> -#define MT8173_TOP_AXI_PROT_EN_CQ_DMA BIT(18)
> -#define MT8173_TOP_AXI_PROT_EN_GCPU BIT(19)
> -#define MT8173_TOP_AXI_PROT_EN_IOMMU BIT(20)
> -#define MT8173_TOP_AXI_PROT_EN_MFG_M0 BIT(21)
> -#define MT8173_TOP_AXI_PROT_EN_MFG_M1 BIT(22)
> -#define MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT BIT(23)
> -
> -#define MT2701_TOP_AXI_PROT_EN_MM_M0 BIT(1)
> -#define MT2701_TOP_AXI_PROT_EN_CONN_M BIT(2)
> -#define MT2701_TOP_AXI_PROT_EN_CONN_S BIT(8)
> -
> -#define MT7622_TOP_AXI_PROT_EN_ETHSYS (BIT(3) | BIT(17))
> -#define MT7622_TOP_AXI_PROT_EN_HIF0 (BIT(24) | BIT(25))
> -#define MT7622_TOP_AXI_PROT_EN_HIF1 (BIT(26) | BIT(27) | \
> - BIT(28))
> -#define MT7622_TOP_AXI_PROT_EN_WB (BIT(2) | BIT(6) | \
> - BIT(7) | BIT(8))
Err wait, don't you need these values in patch 04/10?
> -
> -int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask,
> - bool reg_update);
> -int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask,
> - bool reg_update);
> -#endif /* __SOC_MEDIATEK_INFRACFG_H */
> --
> 1.8.1.1.dirty
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v11 05/10] soc: mediatek: Remove infracfg misc driver support
2019-12-20 4:11 ` Nicolas Boichat
@ 2019-12-20 5:00 ` Weiyi Lu
2019-12-20 5:09 ` Nicolas Boichat
0 siblings, 1 reply; 33+ messages in thread
From: Weiyi Lu @ 2019-12-20 5:00 UTC (permalink / raw)
To: Nicolas Boichat
Cc: Matthias Brugger, Rob Herring, Sascha Hauer, James Liao,
Fan Chen, linux-arm Mailing List, lkml,
moderated list:ARM/Mediatek SoC support, srv_heupstream
On Fri, 2019-12-20 at 12:11 +0800, Nicolas Boichat wrote:
> On Fri, Dec 20, 2019 at 11:46 AM Weiyi Lu <weiyi.lu@mediatek.com> wrote:
> >
> > In previous patches, we introduce scpsys-ext driver that covers
> > the functions which infracfg misc driver provided.
> > And then replace bus_prot_mask with bp_table of all compatibles.
> > Now, we're going to remove infracfg misc drvier which is no longer
> > being used.
> >
> > Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> > ---
> > drivers/soc/mediatek/Kconfig | 10 -----
> > drivers/soc/mediatek/Makefile | 3 +-
> > drivers/soc/mediatek/mtk-infracfg.c | 79 -----------------------------------
> > include/linux/soc/mediatek/infracfg.h | 39 -----------------
> > 4 files changed, 1 insertion(+), 130 deletions(-)
> > delete mode 100644 drivers/soc/mediatek/mtk-infracfg.c
> > delete mode 100644 include/linux/soc/mediatek/infracfg.h
> > [snip]
> > diff --git a/include/linux/soc/mediatek/infracfg.h b/include/linux/soc/mediatek/infracfg.h
> > deleted file mode 100644
> > index fd25f01..0000000
> > --- a/include/linux/soc/mediatek/infracfg.h
> > +++ /dev/null
> > @@ -1,39 +0,0 @@
> > -/* SPDX-License-Identifier: GPL-2.0 */
> > -#ifndef __SOC_MEDIATEK_INFRACFG_H
> > -#define __SOC_MEDIATEK_INFRACFG_H
> > -
> > -#define MT8173_TOP_AXI_PROT_EN_MCI_M2 BIT(0)
> > -#define MT8173_TOP_AXI_PROT_EN_MM_M0 BIT(1)
> > -#define MT8173_TOP_AXI_PROT_EN_MM_M1 BIT(2)
> > -#define MT8173_TOP_AXI_PROT_EN_MMAPB_S BIT(6)
> > -#define MT8173_TOP_AXI_PROT_EN_L2C_M2 BIT(9)
> > -#define MT8173_TOP_AXI_PROT_EN_L2SS_SMI BIT(11)
> > -#define MT8173_TOP_AXI_PROT_EN_L2SS_ADD BIT(12)
> > -#define MT8173_TOP_AXI_PROT_EN_CCI_M2 BIT(13)
> > -#define MT8173_TOP_AXI_PROT_EN_MFG_S BIT(14)
> > -#define MT8173_TOP_AXI_PROT_EN_PERI_M0 BIT(15)
> > -#define MT8173_TOP_AXI_PROT_EN_PERI_M1 BIT(16)
> > -#define MT8173_TOP_AXI_PROT_EN_DEBUGSYS BIT(17)
> > -#define MT8173_TOP_AXI_PROT_EN_CQ_DMA BIT(18)
> > -#define MT8173_TOP_AXI_PROT_EN_GCPU BIT(19)
> > -#define MT8173_TOP_AXI_PROT_EN_IOMMU BIT(20)
> > -#define MT8173_TOP_AXI_PROT_EN_MFG_M0 BIT(21)
> > -#define MT8173_TOP_AXI_PROT_EN_MFG_M1 BIT(22)
> > -#define MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT BIT(23)
> > -
> > -#define MT2701_TOP_AXI_PROT_EN_MM_M0 BIT(1)
> > -#define MT2701_TOP_AXI_PROT_EN_CONN_M BIT(2)
> > -#define MT2701_TOP_AXI_PROT_EN_CONN_S BIT(8)
> > -
> > -#define MT7622_TOP_AXI_PROT_EN_ETHSYS (BIT(3) | BIT(17))
> > -#define MT7622_TOP_AXI_PROT_EN_HIF0 (BIT(24) | BIT(25))
> > -#define MT7622_TOP_AXI_PROT_EN_HIF1 (BIT(26) | BIT(27) | \
> > - BIT(28))
> > -#define MT7622_TOP_AXI_PROT_EN_WB (BIT(2) | BIT(6) | \
> > - BIT(7) | BIT(8))
>
> Err wait, don't you need these values in patch 04/10?
>
Actually I already duplicated those being used into scpsys-ext.h and
then replace the header file in patch 04/10
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -11,7 +11,7 @@
-#include <linux/soc/mediatek/infracfg.h>
+#include "scpsys-ext.h"
so I remove the infracfg.h directly in this patch and add those new for
MT8183 in scpsys-ext.h
> > -
> > -int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask,
> > - bool reg_update);
> > -int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask,
> > - bool reg_update);
> > -#endif /* __SOC_MEDIATEK_INFRACFG_H */
> > --
> > 1.8.1.1.dirty
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v11 05/10] soc: mediatek: Remove infracfg misc driver support
2019-12-20 5:00 ` Weiyi Lu
@ 2019-12-20 5:09 ` Nicolas Boichat
0 siblings, 0 replies; 33+ messages in thread
From: Nicolas Boichat @ 2019-12-20 5:09 UTC (permalink / raw)
To: Weiyi Lu
Cc: Matthias Brugger, Rob Herring, Sascha Hauer, James Liao,
Fan Chen, linux-arm Mailing List, lkml,
moderated list:ARM/Mediatek SoC support, srv_heupstream
On Fri, Dec 20, 2019 at 1:00 PM Weiyi Lu <weiyi.lu@mediatek.com> wrote:
>
> On Fri, 2019-12-20 at 12:11 +0800, Nicolas Boichat wrote:
> > On Fri, Dec 20, 2019 at 11:46 AM Weiyi Lu <weiyi.lu@mediatek.com> wrote:
> > >
> > > In previous patches, we introduce scpsys-ext driver that covers
> > > the functions which infracfg misc driver provided.
> > > And then replace bus_prot_mask with bp_table of all compatibles.
> > > Now, we're going to remove infracfg misc drvier which is no longer
> > > being used.
> > >
> > > Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> > > ---
> > > drivers/soc/mediatek/Kconfig | 10 -----
> > > drivers/soc/mediatek/Makefile | 3 +-
> > > drivers/soc/mediatek/mtk-infracfg.c | 79 -----------------------------------
> > > include/linux/soc/mediatek/infracfg.h | 39 -----------------
> > > 4 files changed, 1 insertion(+), 130 deletions(-)
> > > delete mode 100644 drivers/soc/mediatek/mtk-infracfg.c
> > > delete mode 100644 include/linux/soc/mediatek/infracfg.h
> > > [snip]
> > > diff --git a/include/linux/soc/mediatek/infracfg.h b/include/linux/soc/mediatek/infracfg.h
> > > deleted file mode 100644
> > > index fd25f01..0000000
> > > --- a/include/linux/soc/mediatek/infracfg.h
> > > +++ /dev/null
> > > @@ -1,39 +0,0 @@
> > > -/* SPDX-License-Identifier: GPL-2.0 */
> > > -#ifndef __SOC_MEDIATEK_INFRACFG_H
> > > -#define __SOC_MEDIATEK_INFRACFG_H
> > > -
> > > -#define MT8173_TOP_AXI_PROT_EN_MCI_M2 BIT(0)
> > > -#define MT8173_TOP_AXI_PROT_EN_MM_M0 BIT(1)
> > > -#define MT8173_TOP_AXI_PROT_EN_MM_M1 BIT(2)
> > > -#define MT8173_TOP_AXI_PROT_EN_MMAPB_S BIT(6)
> > > -#define MT8173_TOP_AXI_PROT_EN_L2C_M2 BIT(9)
> > > -#define MT8173_TOP_AXI_PROT_EN_L2SS_SMI BIT(11)
> > > -#define MT8173_TOP_AXI_PROT_EN_L2SS_ADD BIT(12)
> > > -#define MT8173_TOP_AXI_PROT_EN_CCI_M2 BIT(13)
> > > -#define MT8173_TOP_AXI_PROT_EN_MFG_S BIT(14)
> > > -#define MT8173_TOP_AXI_PROT_EN_PERI_M0 BIT(15)
> > > -#define MT8173_TOP_AXI_PROT_EN_PERI_M1 BIT(16)
> > > -#define MT8173_TOP_AXI_PROT_EN_DEBUGSYS BIT(17)
> > > -#define MT8173_TOP_AXI_PROT_EN_CQ_DMA BIT(18)
> > > -#define MT8173_TOP_AXI_PROT_EN_GCPU BIT(19)
> > > -#define MT8173_TOP_AXI_PROT_EN_IOMMU BIT(20)
> > > -#define MT8173_TOP_AXI_PROT_EN_MFG_M0 BIT(21)
> > > -#define MT8173_TOP_AXI_PROT_EN_MFG_M1 BIT(22)
> > > -#define MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT BIT(23)
> > > -
> > > -#define MT2701_TOP_AXI_PROT_EN_MM_M0 BIT(1)
> > > -#define MT2701_TOP_AXI_PROT_EN_CONN_M BIT(2)
> > > -#define MT2701_TOP_AXI_PROT_EN_CONN_S BIT(8)
> > > -
> > > -#define MT7622_TOP_AXI_PROT_EN_ETHSYS (BIT(3) | BIT(17))
> > > -#define MT7622_TOP_AXI_PROT_EN_HIF0 (BIT(24) | BIT(25))
> > > -#define MT7622_TOP_AXI_PROT_EN_HIF1 (BIT(26) | BIT(27) | \
> > > - BIT(28))
> > > -#define MT7622_TOP_AXI_PROT_EN_WB (BIT(2) | BIT(6) | \
> > > - BIT(7) | BIT(8))
> >
> > Err wait, don't you need these values in patch 04/10?
> >
>
> Actually I already duplicated those being used into scpsys-ext.h and
> then replace the header file in patch 04/10
Oh, missed that, SGTM then.
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
> --- a/drivers/soc/mediatek/mtk-scpsys.c
> +++ b/drivers/soc/mediatek/mtk-scpsys.c
> @@ -11,7 +11,7 @@
> -#include <linux/soc/mediatek/infracfg.h>
> +#include "scpsys-ext.h"
>
> so I remove the infracfg.h directly in this patch and add those new for
> MT8183 in scpsys-ext.h
>
> > > -
> > > -int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask,
> > > - bool reg_update);
> > > -int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask,
> > > - bool reg_update);
> > > -#endif /* __SOC_MEDIATEK_INFRACFG_H */
> > > --
> > > 1.8.1.1.dirty
>
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v11 08/10] soc: mediatek: Add MT8183 scpsys support
2019-12-20 3:46 ` [PATCH v11 08/10] soc: mediatek: Add MT8183 scpsys support Weiyi Lu
@ 2019-12-20 5:11 ` Nicolas Boichat
0 siblings, 0 replies; 33+ messages in thread
From: Nicolas Boichat @ 2019-12-20 5:11 UTC (permalink / raw)
To: Weiyi Lu
Cc: Matthias Brugger, Rob Herring, Sascha Hauer, James Liao,
Fan Chen, linux-arm Mailing List, lkml,
moderated list:ARM/Mediatek SoC support, srv_heupstream
On Fri, Dec 20, 2019 at 11:46 AM Weiyi Lu <weiyi.lu@mediatek.com> wrote:
>
> Add scpsys driver for MT8183
> And minor fix to add a comma at the end
I'll leave it up to the maintainer, but those minor fixes outside of
new mt8183 code should probably be done as a separate CL.
>
> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
> ---
> drivers/soc/mediatek/mtk-scpsys.c | 233 +++++++++++++++++++++++++++++++++++++-
> drivers/soc/mediatek/scpsys-ext.h | 28 +++++
> 2 files changed, 255 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
> index 1972726..b8b72fa 100644
> --- a/drivers/soc/mediatek/mtk-scpsys.c
> +++ b/drivers/soc/mediatek/mtk-scpsys.c
> @@ -19,6 +19,7 @@
> #include <dt-bindings/power/mt7622-power.h>
> #include <dt-bindings/power/mt7623a-power.h>
> #include <dt-bindings/power/mt8173-power.h>
> +#include <dt-bindings/power/mt8183-power.h>
>
> #define MTK_POLL_DELAY_US 10
> #define MTK_POLL_TIMEOUT USEC_PER_SEC
> @@ -1082,12 +1083,218 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> {MT8173_POWER_DOMAIN_MFG_2D, MT8173_POWER_DOMAIN_MFG},
> };
>
> +/*
> + * MT8183 power domain support
> + */
> +
> +static const struct scp_domain_data scp_domain_data_mt8183[] = {
> + [MT8183_POWER_DOMAIN_AUDIO] = {
> + .name = "audio",
> + .sta_mask = PWR_STATUS_AUDIO,
> + .ctl_offs = 0x0314,
> + .sram_pdn_bits = GENMASK(11, 8),
> + .sram_pdn_ack_bits = GENMASK(15, 12),
> + .basic_clk_name = {"audio", "audio1", "audio2"},
> + },
> + [MT8183_POWER_DOMAIN_CONN] = {
> + .name = "conn",
> + .sta_mask = PWR_STATUS_CONN,
> + .ctl_offs = 0x032c,
> + .sram_pdn_bits = 0,
> + .sram_pdn_ack_bits = 0,
> + .bp_table = {
> + BUS_PROT(IFR_TYPE, 0x2a0, 0x2a4, 0, 0x228,
> + MT8183_TOP_AXI_PROT_EN_CONN),
> + },
> + },
> + [MT8183_POWER_DOMAIN_MFG_ASYNC] = {
> + .name = "mfg_async",
> + .sta_mask = PWR_STATUS_MFG_ASYNC,
> + .ctl_offs = 0x0334,
> + .sram_pdn_bits = 0,
> + .sram_pdn_ack_bits = 0,
> + .basic_clk_name = {"mfg"},
> + },
> + [MT8183_POWER_DOMAIN_MFG] = {
> + .name = "mfg",
> + .sta_mask = PWR_STATUS_MFG,
> + .ctl_offs = 0x0338,
> + .sram_pdn_bits = GENMASK(8, 8),
> + .sram_pdn_ack_bits = GENMASK(12, 12),
> + },
> + [MT8183_POWER_DOMAIN_MFG_CORE0] = {
> + .name = "mfg_core0",
> + .sta_mask = BIT(7),
> + .ctl_offs = 0x034c,
> + .sram_pdn_bits = GENMASK(8, 8),
> + .sram_pdn_ack_bits = GENMASK(12, 12),
> + },
> + [MT8183_POWER_DOMAIN_MFG_CORE1] = {
> + .name = "mfg_core1",
> + .sta_mask = BIT(20),
> + .ctl_offs = 0x0310,
> + .sram_pdn_bits = GENMASK(8, 8),
> + .sram_pdn_ack_bits = GENMASK(12, 12),
> + },
> + [MT8183_POWER_DOMAIN_MFG_2D] = {
> + .name = "mfg_2d",
> + .sta_mask = PWR_STATUS_MFG_2D,
> + .ctl_offs = 0x0348,
> + .sram_pdn_bits = GENMASK(8, 8),
> + .sram_pdn_ack_bits = GENMASK(12, 12),
> + .bp_table = {
> + BUS_PROT(IFR_TYPE, 0x2a8, 0x2ac, 0, 0x258,
> + MT8183_TOP_AXI_PROT_EN_1_MFG),
> + BUS_PROT(IFR_TYPE, 0x2a0, 0x2a4, 0, 0x228,
> + MT8183_TOP_AXI_PROT_EN_MFG),
> + },
> + },
> + [MT8183_POWER_DOMAIN_DISP] = {
> + .name = "disp",
> + .sta_mask = PWR_STATUS_DISP,
> + .ctl_offs = 0x030c,
> + .sram_pdn_bits = GENMASK(8, 8),
> + .sram_pdn_ack_bits = GENMASK(12, 12),
> + .basic_clk_name = {"mm"},
> + .subsys_clk_prefix = "mm",
> + .bp_table = {
> + BUS_PROT(IFR_TYPE, 0x2a8, 0x2ac, 0, 0x258,
> + MT8183_TOP_AXI_PROT_EN_1_DISP),
> + BUS_PROT(IFR_TYPE, 0x2a0, 0x2a4, 0, 0x228,
> + MT8183_TOP_AXI_PROT_EN_DISP),
> + BUS_PROT(SMI_TYPE, 0x3c4, 0x3c8, 0, 0x3c0,
> + MT8183_SMI_COMMON_SMI_CLAMP_DISP),
> + },
> + },
> + [MT8183_POWER_DOMAIN_CAM] = {
> + .name = "cam",
> + .sta_mask = BIT(25),
> + .ctl_offs = 0x0344,
> + .sram_pdn_bits = GENMASK(9, 8),
> + .sram_pdn_ack_bits = GENMASK(13, 12),
> + .basic_clk_name = {"cam"},
> + .subsys_clk_prefix = "cam",
> + .bp_table = {
> + BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0, 0x2ec,
> + MT8183_TOP_AXI_PROT_EN_MM_CAM),
> + BUS_PROT(IFR_TYPE, 0x2a0, 0x2a4, 0, 0x228,
> + MT8183_TOP_AXI_PROT_EN_CAM),
> + BUS_PROT_IGN(IFR_TYPE, 0x2d4, 0x2d8, 0, 0x2ec,
> + MT8183_TOP_AXI_PROT_EN_MM_CAM_2ND),
> + BUS_PROT(SMI_TYPE, 0x3c4, 0x3c8, 0, 0x3c0,
> + MT8183_SMI_COMMON_SMI_CLAMP_CAM),
> + },
> + },
> + [MT8183_POWER_DOMAIN_ISP] = {
> + .name = "isp",
> + .sta_mask = PWR_STATUS_ISP,
> + .ctl_offs = 0x0308,
> + .sram_pdn_bits = GENMASK(9, 8),
> + .sram_pdn_ack_bits = GENMASK(13, 12),
> + .basic_clk_name = {"isp"},
> + .subsys_clk_prefix = "isp",
> + .bp_table = {
> + BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0, 0x2ec,
> + MT8183_TOP_AXI_PROT_EN_MM_ISP),
> + BUS_PROT_IGN(IFR_TYPE, 0x2d4, 0x2d8, 0, 0x2ec,
> + MT8183_TOP_AXI_PROT_EN_MM_ISP_2ND),
> + BUS_PROT(SMI_TYPE, 0x3c4, 0x3c8, 0, 0x3c0,
> + MT8183_SMI_COMMON_SMI_CLAMP_ISP),
> + },
> + },
> + [MT8183_POWER_DOMAIN_VDEC] = {
> + .name = "vdec",
> + .sta_mask = BIT(31),
> + .ctl_offs = 0x0300,
> + .sram_pdn_bits = GENMASK(8, 8),
> + .sram_pdn_ack_bits = GENMASK(12, 12),
> + .bp_table = {
> + BUS_PROT(SMI_TYPE, 0x3c4, 0x3c8, 0, 0x3c0,
> + MT8183_SMI_COMMON_SMI_CLAMP_VDEC),
> + },
> + },
> + [MT8183_POWER_DOMAIN_VENC] = {
> + .name = "venc",
> + .sta_mask = PWR_STATUS_VENC,
> + .ctl_offs = 0x0304,
> + .sram_pdn_bits = GENMASK(11, 8),
> + .sram_pdn_ack_bits = GENMASK(15, 12),
> + .bp_table = {
> + BUS_PROT(SMI_TYPE, 0x3c4, 0x3c8, 0, 0x3c0,
> + MT8183_SMI_COMMON_SMI_CLAMP_VENC),
> + },
> + },
> + [MT8183_POWER_DOMAIN_VPU_TOP] = {
> + .name = "vpu_top",
> + .sta_mask = BIT(26),
> + .ctl_offs = 0x0324,
> + .sram_pdn_bits = GENMASK(8, 8),
> + .sram_pdn_ack_bits = GENMASK(12, 12),
> + .basic_clk_name = {"vpu", "vpu1"},
> + .subsys_clk_prefix = "vpu",
> + .bp_table = {
> + BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0, 0x2ec,
> + MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP),
> + BUS_PROT(IFR_TYPE, 0x2a0, 0x2a4, 0, 0x228,
> + MT8183_TOP_AXI_PROT_EN_VPU_TOP),
> + BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0, 0x2ec,
> + MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP_2ND),
> + BUS_PROT(SMI_TYPE, 0x3c4, 0x3c8, 0, 0x3c0,
> + MT8183_SMI_COMMON_SMI_CLAMP_VPU_TOP),
> + },
> + },
> + [MT8183_POWER_DOMAIN_VPU_CORE0] = {
> + .name = "vpu_core0",
> + .sta_mask = BIT(27),
> + .ctl_offs = 0x33c,
> + .sram_iso_ctrl = true,
> + .sram_pdn_bits = GENMASK(11, 8),
> + .sram_pdn_ack_bits = GENMASK(13, 12),
> + .basic_clk_name = {"vpu2"},
> + .bp_table = {
> + BUS_PROT(IFR_TYPE, 0x2c4, 0x2c8, 0, 0x2e4,
> + MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0),
> + BUS_PROT(IFR_TYPE, 0x2c4, 0x2c8, 0, 0x2e4,
> + MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0_2ND),
> + },
> + },
> + [MT8183_POWER_DOMAIN_VPU_CORE1] = {
> + .name = "vpu_core1",
> + .sta_mask = BIT(28),
> + .ctl_offs = 0x0340,
> + .sram_iso_ctrl = true,
> + .sram_pdn_bits = GENMASK(11, 8),
> + .sram_pdn_ack_bits = GENMASK(13, 12),
> + .basic_clk_name = {"vpu3"},
> + .bp_table = {
> + BUS_PROT(IFR_TYPE, 0x2c4, 0x2c8, 0, 0x2e4,
> + MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1),
> + BUS_PROT(IFR_TYPE, 0x2c4, 0x2c8, 0, 0x2e4,
> + MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1_2ND),
> + },
> + },
> +};
> +
> +static const struct scp_subdomain scp_subdomain_mt8183[] = {
> + {MT8183_POWER_DOMAIN_MFG_ASYNC, MT8183_POWER_DOMAIN_MFG},
> + {MT8183_POWER_DOMAIN_MFG, MT8183_POWER_DOMAIN_MFG_2D},
> + {MT8183_POWER_DOMAIN_MFG, MT8183_POWER_DOMAIN_MFG_CORE0},
> + {MT8183_POWER_DOMAIN_MFG, MT8183_POWER_DOMAIN_MFG_CORE1},
> + {MT8183_POWER_DOMAIN_DISP, MT8183_POWER_DOMAIN_CAM},
> + {MT8183_POWER_DOMAIN_DISP, MT8183_POWER_DOMAIN_ISP},
> + {MT8183_POWER_DOMAIN_DISP, MT8183_POWER_DOMAIN_VDEC},
> + {MT8183_POWER_DOMAIN_DISP, MT8183_POWER_DOMAIN_VENC},
> + {MT8183_POWER_DOMAIN_DISP, MT8183_POWER_DOMAIN_VPU_TOP},
> + {MT8183_POWER_DOMAIN_VPU_TOP, MT8183_POWER_DOMAIN_VPU_CORE0},
> + {MT8183_POWER_DOMAIN_VPU_TOP, MT8183_POWER_DOMAIN_VPU_CORE1},
> +};
> +
> static const struct scp_soc_data mt2701_data = {
> .domains = scp_domain_data_mt2701,
> .num_domains = ARRAY_SIZE(scp_domain_data_mt2701),
> .regs = {
> .pwr_sta_offs = SPM_PWR_STATUS,
> - .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
> + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
> },
> };
>
> @@ -1098,7 +1305,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .num_subdomains = ARRAY_SIZE(scp_subdomain_mt2712),
> .regs = {
> .pwr_sta_offs = SPM_PWR_STATUS,
> - .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
> + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
> },
> };
>
> @@ -1109,7 +1316,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .num_subdomains = ARRAY_SIZE(scp_subdomain_mt6797),
> .regs = {
> .pwr_sta_offs = SPM_PWR_STATUS_MT6797,
> - .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND_MT6797
> + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND_MT6797,
> },
> };
>
> @@ -1118,7 +1325,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .num_domains = ARRAY_SIZE(scp_domain_data_mt7622),
> .regs = {
> .pwr_sta_offs = SPM_PWR_STATUS,
> - .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
> + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
> },
> };
>
> @@ -1127,7 +1334,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .num_domains = ARRAY_SIZE(scp_domain_data_mt7623a),
> .regs = {
> .pwr_sta_offs = SPM_PWR_STATUS,
> - .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
> + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
> },
> };
>
> @@ -1138,10 +1345,21 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .num_subdomains = ARRAY_SIZE(scp_subdomain_mt8173),
> .regs = {
> .pwr_sta_offs = SPM_PWR_STATUS,
> - .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
> + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
> },
> };
>
> +static const struct scp_soc_data mt8183_data = {
> + .domains = scp_domain_data_mt8183,
> + .num_domains = ARRAY_SIZE(scp_domain_data_mt8183),
> + .subdomains = scp_subdomain_mt8183,
> + .num_subdomains = ARRAY_SIZE(scp_subdomain_mt8183),
> + .regs = {
> + .pwr_sta_offs = 0x0180,
> + .pwr_sta2nd_offs = 0x0184,
> + }
> +};
> +
> /*
> * scpsys driver init
> */
> @@ -1166,6 +1384,9 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .compatible = "mediatek,mt8173-scpsys",
> .data = &mt8173_data,
> }, {
> + .compatible = "mediatek,mt8183-scpsys",
> + .data = &mt8183_data,
> + }, {
> /* sentinel */
> }
> };
> diff --git a/drivers/soc/mediatek/scpsys-ext.h b/drivers/soc/mediatek/scpsys-ext.h
> index 458b2c5..0f90e5d 100644
> --- a/drivers/soc/mediatek/scpsys-ext.h
> +++ b/drivers/soc/mediatek/scpsys-ext.h
> @@ -43,6 +43,34 @@
> #define MT8173_TOP_AXI_PROT_EN_MFG_M1 BIT(22)
> #define MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT BIT(23)
>
> +#define MT8183_TOP_AXI_PROT_EN_DISP (BIT(10) | BIT(11))
> +#define MT8183_TOP_AXI_PROT_EN_CONN (BIT(13) | BIT(14))
> +#define MT8183_TOP_AXI_PROT_EN_MFG (BIT(21) | BIT(22))
> +#define MT8183_TOP_AXI_PROT_EN_CAM BIT(28)
> +#define MT8183_TOP_AXI_PROT_EN_VPU_TOP BIT(27)
> +#define MT8183_TOP_AXI_PROT_EN_1_DISP (BIT(16) | BIT(17))
> +#define MT8183_TOP_AXI_PROT_EN_1_MFG GENMASK(21, 19)
> +#define MT8183_TOP_AXI_PROT_EN_MM_ISP (BIT(3) | BIT(8))
> +#define MT8183_TOP_AXI_PROT_EN_MM_ISP_2ND BIT(10)
> +#define MT8183_TOP_AXI_PROT_EN_MM_CAM (BIT(4) | BIT(5) | \
> + BIT(9) | BIT(13))
> +#define MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP (GENMASK(9, 6) | \
> + BIT(12))
> +#define MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP_2ND (BIT(10) | BIT(11))
> +#define MT8183_TOP_AXI_PROT_EN_MM_CAM_2ND BIT(11)
> +#define MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0_2ND (BIT(0) | BIT(2) | \
> + BIT(4))
> +#define MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1_2ND (BIT(1) | BIT(3) | \
> + BIT(5))
> +#define MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0 BIT(6)
> +#define MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1 BIT(7)
> +#define MT8183_SMI_COMMON_SMI_CLAMP_DISP GENMASK(7, 0)
> +#define MT8183_SMI_COMMON_SMI_CLAMP_VENC BIT(1)
> +#define MT8183_SMI_COMMON_SMI_CLAMP_ISP BIT(2)
> +#define MT8183_SMI_COMMON_SMI_CLAMP_CAM (BIT(3) | BIT(4))
> +#define MT8183_SMI_COMMON_SMI_CLAMP_VPU_TOP (BIT(5) | BIT(6))
> +#define MT8183_SMI_COMMON_SMI_CLAMP_VDEC BIT(7)
> +
> enum regmap_type {
> INVALID_TYPE = 0,
> IFR_TYPE,
> --
> 1.8.1.1.dirty
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v11 00/10] Mediatek MT8183 scpsys support
2019-12-20 3:45 [PATCH v11 00/10] Mediatek MT8183 scpsys support Weiyi Lu
` (9 preceding siblings ...)
2019-12-20 3:46 ` [PATCH v11 10/10] arm64: dts: Add power-domains properity to mfgcfg Weiyi Lu
@ 2019-12-27 1:43 ` Weiyi Lu
10 siblings, 0 replies; 33+ messages in thread
From: Weiyi Lu @ 2019-12-27 1:43 UTC (permalink / raw)
To: Matthias Brugger
Cc: Nicolas Boichat, Rob Herring, Sascha Hauer, James Liao, Fan Chen,
linux-arm-kernel, linux-kernel, linux-mediatek, srv_heupstream
On Fri, 2019-12-20 at 11:45 +0800, Weiyi Lu wrote:
Hi Matthias,
Just gentle ping. Many thanks.
> This series is based on v5.5-rc1
>
> changes since v10:
> - squash PATCH 04 and PATCH 06 in v9 into its previous patch
> - add "ignore_clr_ack" for multiple step bus protection control to have a clean definition of power domain data
> - keep the mask register bit definitions and do the same for MT8183
>
> changes since v9:
> - add new PATCH 04 and PATCH 06 to replace by new method for all compatibles
> - add new PATCH 07 to remove infracfg misc driver
> - minor coding sytle fix
>
> changes since v7:
> - reword in binding document [PATCH 02/14]
> - fix error return checking bug in subsys clock control [PATCH 10/14]
> - add power domains properity to mfgcfg patch [PATCH 14/14] from
> https://patchwork.kernel.org/patch/11126199/
>
> changes since v6:
> - remove the patch of SPDX license identifier because it's already fixed
>
> changes since v5:
> - fix documentation in [PATCH 04/14]
> - remove useless variable checking and reuse API of clock control in [PATCH 06/14]
> - coding style fix of bus protection control in [PATCH 08/14]
> - fix naming of new added data in [PATCH 09/14]
> - small refactor of multiple step bus protection control in [PATCH 10/14]
>
> changes since v4:
> - add property to mt8183 smi-common
> - seperate refactor patches and new add function
> - add power controller device node
>
> Weiyi Lu (10):
> dt-bindings: mediatek: Add property to mt8183 smi-common
> dt-bindings: soc: Add MT8183 power dt-bindings
> soc: mediatek: Add basic_clk_name to scp_power_data
> soc: mediatek: Add multiple step bus protection control
> soc: mediatek: Remove infracfg misc driver support
> soc: mediatek: Add subsys clock control for bus protection
> soc: mediatek: Add extra sram control
> soc: mediatek: Add MT8183 scpsys support
> arm64: dts: Add power controller device node of MT8183
> arm64: dts: Add power-domains properity to mfgcfg
>
> .../memory-controllers/mediatek,smi-common.txt | 2 +-
> .../devicetree/bindings/soc/mediatek/scpsys.txt | 20 +-
> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 63 +++
> drivers/soc/mediatek/Kconfig | 10 -
> drivers/soc/mediatek/Makefile | 3 +-
> drivers/soc/mediatek/mtk-infracfg.c | 79 ---
> drivers/soc/mediatek/mtk-scpsys-ext.c | 101 ++++
> drivers/soc/mediatek/mtk-scpsys.c | 578 +++++++++++++++------
> drivers/soc/mediatek/scpsys-ext.h | 95 ++++
> include/dt-bindings/power/mt8183-power.h | 26 +
> include/linux/soc/mediatek/infracfg.h | 39 --
> 11 files changed, 736 insertions(+), 280 deletions(-)
> delete mode 100644 drivers/soc/mediatek/mtk-infracfg.c
> create mode 100644 drivers/soc/mediatek/mtk-scpsys-ext.c
> create mode 100644 drivers/soc/mediatek/scpsys-ext.h
> create mode 100644 include/dt-bindings/power/mt8183-power.h
> delete mode 100644 include/linux/soc/mediatek/infracfg.h
>
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v11 01/10] dt-bindings: mediatek: Add property to mt8183 smi-common
2019-12-20 3:45 ` [PATCH v11 01/10] dt-bindings: mediatek: Add property to mt8183 smi-common Weiyi Lu
@ 2020-01-15 5:45 ` Weiyi Lu
0 siblings, 0 replies; 33+ messages in thread
From: Weiyi Lu @ 2020-01-15 5:45 UTC (permalink / raw)
To: Matthias Brugger
Cc: Nicolas Boichat, Rob Herring, Sascha Hauer, James Liao, Fan Chen,
linux-arm-kernel, linux-kernel, linux-mediatek, srv_heupstream
On Fri, 2019-12-20 at 11:45 +0800, Weiyi Lu wrote:
> For scpsys driver using regmap based syscon driver API.
>
> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> ---
> .../devicetree/bindings/memory-controllers/mediatek,smi-common.txt | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
> index b478ade..01744ec 100644
> --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
> +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
> @@ -20,7 +20,7 @@ Required properties:
> "mediatek,mt2712-smi-common"
> "mediatek,mt7623-smi-common", "mediatek,mt2701-smi-common"
> "mediatek,mt8173-smi-common"
> - "mediatek,mt8183-smi-common"
> + "mediatek,mt8183-smi-common", "syscon"
> - reg : the register and size of the SMI block.
> - power-domains : a phandle to the power domain of this local arbiter.
> - clocks : Must contain an entry for each entry in clock-names.
Hi Matthias,
For the preparation of v12, may I have your comments on this v11
series ?
Many thanks.
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v11 07/10] soc: mediatek: Add extra sram control
2019-12-20 3:46 ` [PATCH v11 07/10] soc: mediatek: Add extra sram control Weiyi Lu
@ 2020-02-11 17:04 ` Matthias Brugger
2020-02-12 2:56 ` Weiyi Lu
0 siblings, 1 reply; 33+ messages in thread
From: Matthias Brugger @ 2020-02-11 17:04 UTC (permalink / raw)
To: Weiyi Lu, Nicolas Boichat, Rob Herring, Sascha Hauer
Cc: James Liao, Fan Chen, linux-arm-kernel, linux-kernel,
linux-mediatek, srv_heupstream
On 20/12/2019 04:46, Weiyi Lu wrote:
> For some power domains like vpu_core on MT8183 whose sram need to
> do clock and internal isolation while power on/off sram.
> We add a flag "sram_iso_ctrl" in scp_domain_data to judge if we
> need to do the extra sram isolation control or not.
>
> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
> ---
> drivers/soc/mediatek/mtk-scpsys.c | 24 ++++++++++++++++++++++--
> 1 file changed, 22 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
> index 32be4b3..1972726 100644
> --- a/drivers/soc/mediatek/mtk-scpsys.c
> +++ b/drivers/soc/mediatek/mtk-scpsys.c
> @@ -56,6 +56,8 @@
> #define PWR_ON_BIT BIT(2)
> #define PWR_ON_2ND_BIT BIT(3)
> #define PWR_CLK_DIS_BIT BIT(4)
> +#define PWR_SRAM_CLKISO_BIT BIT(5)
> +#define PWR_SRAM_ISOINT_B_BIT BIT(6)
>
> #define PWR_STATUS_CONN BIT(1)
> #define PWR_STATUS_DISP BIT(3)
> @@ -86,6 +88,8 @@
> * @name: The domain name.
> * @sta_mask: The mask for power on/off status bit.
> * @ctl_offs: The offset for main power control register.
> + * @sram_iso_ctrl: The flag to judge if the power domain need to do
> + * the extra sram isolation control.
> * @sram_pdn_bits: The mask for sram power control bits.
> * @sram_pdn_ack_bits: The mask for sram power control acked bits.
> * @basic_clk_name: The basic clocks required by this power domain.
> @@ -98,6 +102,7 @@ struct scp_domain_data {
> const char *name;
> u32 sta_mask;
> int ctl_offs;
> + bool sram_iso_ctrl;
Why don't we put that into the caps variable? We have plenty of space left there
and if needed we can bump up its value from u8 to u32.
> u32 sram_pdn_bits;
> u32 sram_pdn_ack_bits;
> const char *basic_clk_name[MAX_CLKS];
> @@ -233,6 +238,14 @@ static int scpsys_sram_enable(struct scp_domain *scpd, void __iomem *ctl_addr)
> return ret;
> }
>
> + if (scpd->data->sram_iso_ctrl) {
> + val = readl(ctl_addr) | PWR_SRAM_ISOINT_B_BIT;
> + writel(val, ctl_addr);
> + udelay(1);
> + val &= ~PWR_SRAM_CLKISO_BIT;
> + writel(val, ctl_addr);
> + }
> +
> return 0;
> }
>
> @@ -242,8 +255,15 @@ static int scpsys_sram_disable(struct scp_domain *scpd, void __iomem *ctl_addr)
> u32 pdn_ack = scpd->data->sram_pdn_ack_bits;
> int tmp;
>
> - val = readl(ctl_addr);
> - val |= scpd->data->sram_pdn_bits;
> + if (scpd->data->sram_iso_ctrl) {
> + val = readl(ctl_addr) | PWR_SRAM_CLKISO_BIT;
> + writel(val, ctl_addr);
> + val &= ~PWR_SRAM_ISOINT_B_BIT;
> + writel(val, ctl_addr);
> + udelay(1);
Why do we need to wait here?
> + }
> +
> + val = readl(ctl_addr) | scpd->data->sram_pdn_bits;
> writel(val, ctl_addr);
>
> /* Either wait until SRAM_PDN_ACK all 1 or 0 */
>
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v11 04/10] soc: mediatek: Add multiple step bus protection control
2019-12-20 3:45 ` [PATCH v11 04/10] soc: mediatek: Add multiple step bus protection control Weiyi Lu
2019-12-20 4:09 ` Nicolas Boichat
@ 2020-02-11 17:49 ` Matthias Brugger
2020-02-12 2:55 ` Weiyi Lu
1 sibling, 1 reply; 33+ messages in thread
From: Matthias Brugger @ 2020-02-11 17:49 UTC (permalink / raw)
To: Weiyi Lu, Nicolas Boichat, Rob Herring, Sascha Hauer
Cc: James Liao, Fan Chen, linux-arm-kernel, linux-kernel,
linux-mediatek, srv_heupstream
On 20/12/2019 04:45, Weiyi Lu wrote:
> Both MT8183 & MT6765 have more control steps of bus protection
> than previous project. And there add more bus protection registers
> reside at infracfg & smi-common. Also add new APIs for multiple
> step bus protection control with more customized arguments.
> And then use bp_table for bus protection of all compatibles,
> instead of mixing bus_prot_mask and bus_prot_reg_update.
>
> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> ---
> drivers/soc/mediatek/Makefile | 2 +-
> drivers/soc/mediatek/mtk-scpsys-ext.c | 101 +++++++++++++++++++++++++++++
> drivers/soc/mediatek/mtk-scpsys.c | 117 +++++++++++++++++++++-------------
> drivers/soc/mediatek/scpsys-ext.h | 67 +++++++++++++++++++
> 4 files changed, 240 insertions(+), 47 deletions(-)
> create mode 100644 drivers/soc/mediatek/mtk-scpsys-ext.c
> create mode 100644 drivers/soc/mediatek/scpsys-ext.h
>
> diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
> index b017330..b442be9 100644
> --- a/drivers/soc/mediatek/Makefile
> +++ b/drivers/soc/mediatek/Makefile
> @@ -1,5 +1,5 @@
> # SPDX-License-Identifier: GPL-2.0-only
> obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o
> -obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
> +obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o mtk-scpsys-ext.o
It seems that we would need another patch which get's rid of the mtk-infracfg
first and then add stuff like the possibility to have different steps.
> obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
> obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
> diff --git a/drivers/soc/mediatek/mtk-scpsys-ext.c b/drivers/soc/mediatek/mtk-scpsys-ext.c
> new file mode 100644
> index 0000000..df402ac
> --- /dev/null
> +++ b/drivers/soc/mediatek/mtk-scpsys-ext.c
I'm not quite sure why we should put this into a new file. I suppose the
rational behind it is the fact that we access other blocks through regmap.
> @@ -0,0 +1,101 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2018 MediaTek Inc.
> + * Author: Owen Chen <Owen.Chen@mediatek.com>
> + */
> +#include <linux/ktime.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/of_device.h>
> +#include <linux/regmap.h>
> +#include "scpsys-ext.h"
> +
> +#define MTK_POLL_DELAY_US 10
> +#define MTK_POLL_TIMEOUT USEC_PER_SEC
> +
> +static int set_bus_protection(struct regmap *map, u32 mask,
> + u32 reg_set, u32 reg_sta, u32 reg_en)
> +{
> + u32 val;
> +
> + if (reg_set)
> + regmap_write(map, reg_set, mask);
> + else
> + regmap_update_bits(map, reg_en, mask, mask);
> +
> + return regmap_read_poll_timeout(map, reg_sta,
> + val, (val & mask) == mask,
> + MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
> +}
> +
> +static int clear_bus_protection(struct regmap *map, u32 mask,
> + u32 reg_clr, u32 reg_sta, u32 reg_en, bool ignore_ack)
> +{
> + u32 val;
> +
> + if (reg_clr)
> + regmap_write(map, reg_clr, mask);
> + else
> + regmap_update_bits(map, reg_en, mask, 0);
> +
> + if (ignore_ack)
> + return 0;
> +
> + return regmap_read_poll_timeout(map, reg_sta,
> + val, !(val & mask),
> + MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
> +}
> +
> +int mtk_scpsys_ext_set_bus_protection(const struct bus_prot *bp_table,
> + struct regmap *infracfg, struct regmap *smi_common)
> +{
> + int i;
> +
> + for (i = 0; i < MAX_STEPS; i++) {
struct bus_prot bp_table = bp_table[i];
> + struct regmap *map = NULL;
> + int ret;
> +
> + if (bp_table[i].type == INVALID_TYPE)
> + break;
> + else if (bp_table[i].type == IFR_TYPE)
> + map = infracfg;
> + else if (bp_table[i].type == SMI_TYPE)
> + map = smi_common;
if (bp_table.type == IFR_TYPE)
map = infracfg;
else if (bp_table.type == SMI_TYPE)
map = smi_common;
else
break;
> +
> + ret = set_bus_protection(map,
> + bp_table[i].mask, bp_table[i].set_ofs,
> + bp_table[i].sta_ofs, bp_table[i].en_ofs);
passing map and bp_table here makes code much more readable. I always end-up
counting the variables when the names in the callee changes.
> +
> + if (ret)
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +int mtk_scpsys_ext_clear_bus_protection(const struct bus_prot *bp_table,
> + struct regmap *infracfg, struct regmap *smi_common)
> +{
> + int i;
> +
> + for (i = MAX_STEPS - 1; i >= 0; i--) {
> + struct regmap *map = NULL;
> + int ret;
> +
> + if (bp_table[i].type == INVALID_TYPE)
> + continue;
> + else if (bp_table[i].type == IFR_TYPE)
> + map = infracfg;
> + else if (bp_table[i].type == SMI_TYPE)
> + map = smi_common;
> +
> + ret = clear_bus_protection(map,
> + bp_table[i].mask, bp_table[i].clr_ofs,
> + bp_table[i].sta_ofs, bp_table[i].en_ofs,
> + bp_table[i].ignore_clr_ack);
> +
same here.
> + if (ret)
> + return ret;
> + }
> +
> + return 0;
> +}
> diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
> index db35a28..763ca58 100644
> --- a/drivers/soc/mediatek/mtk-scpsys.c
> +++ b/drivers/soc/mediatek/mtk-scpsys.c
> @@ -11,7 +11,7 @@
> #include <linux/platform_device.h>
> #include <linux/pm_domain.h>
> #include <linux/regulator/consumer.h>
> -#include <linux/soc/mediatek/infracfg.h>
> +#include "scpsys-ext.h"
>
> #include <dt-bindings/power/mt2701-power.h>
> #include <dt-bindings/power/mt2712-power.h>
> @@ -87,9 +87,9 @@
> * @ctl_offs: The offset for main power control register.
> * @sram_pdn_bits: The mask for sram power control bits.
> * @sram_pdn_ack_bits: The mask for sram power control acked bits.
> - * @bus_prot_mask: The mask for single step bus protection.
> * @basic_clk_name: The basic clocks required by this power domain.
> * @caps: The flag for active wake-up action.
> + * @bp_table: The mask table for multiple step bus protection.
> */
> struct scp_domain_data {
> const char *name;
> @@ -97,9 +97,9 @@ struct scp_domain_data {
> int ctl_offs;
> u32 sram_pdn_bits;
> u32 sram_pdn_ack_bits;
> - u32 bus_prot_mask;
> const char *basic_clk_name[MAX_CLKS];
> u8 caps;
> + struct bus_prot bp_table[MAX_STEPS];
> };
>
> struct scp;
> @@ -123,8 +123,8 @@ struct scp {
> struct device *dev;
> void __iomem *base;
> struct regmap *infracfg;
> + struct regmap *smi_common;
> struct scp_ctrl_reg ctrl_reg;
> - bool bus_prot_reg_update;
> };
>
> struct scp_subdomain {
> @@ -138,7 +138,6 @@ struct scp_soc_data {
> const struct scp_subdomain *subdomains;
> int num_subdomains;
> const struct scp_ctrl_reg regs;
> - bool bus_prot_reg_update;
> };
>
> static int scpsys_domain_is_on(struct scp_domain *scpd)
> @@ -252,24 +251,16 @@ static int scpsys_bus_protect_enable(struct scp_domain *scpd)
> {
> struct scp *scp = scpd->scp;
>
> - if (!scpd->data->bus_prot_mask)
> - return 0;
> -
> - return mtk_infracfg_set_bus_protection(scp->infracfg,
> - scpd->data->bus_prot_mask,
> - scp->bus_prot_reg_update);
> + return mtk_scpsys_ext_set_bus_protection(scpd->data->bp_table,
> + scp->infracfg, scp->smi_common);
Now that's just a wrapper which does add nothing but another indirection. We can
call mtk_scpsys_ext_set_bus_protection() directly (also I don't like the name,
actually why don't mtk_scpsys_set_bus_protection()?)
> }
>
> static int scpsys_bus_protect_disable(struct scp_domain *scpd)
> {
> struct scp *scp = scpd->scp;
>
> - if (!scpd->data->bus_prot_mask)
> - return 0;
> -
> - return mtk_infracfg_clear_bus_protection(scp->infracfg,
> - scpd->data->bus_prot_mask,
> - scp->bus_prot_reg_update);
> + return mtk_scpsys_ext_clear_bus_protection(scpd->data->bp_table,
> + scp->infracfg, scp->smi_common);
> }
>
> static int scpsys_power_on(struct generic_pm_domain *genpd)
> @@ -404,8 +395,7 @@ static int init_basic_clks(struct platform_device *pdev, struct clk **clk,
>
> static struct scp *init_scp(struct platform_device *pdev,
> const struct scp_domain_data *scp_domain_data, int num,
> - const struct scp_ctrl_reg *scp_ctrl_reg,
> - bool bus_prot_reg_update)
> + const struct scp_ctrl_reg *scp_ctrl_reg)
> {
> struct genpd_onecell_data *pd_data;
> struct resource *res;
> @@ -419,8 +409,6 @@ static struct scp *init_scp(struct platform_device *pdev,
> scp->ctrl_reg.pwr_sta_offs = scp_ctrl_reg->pwr_sta_offs;
> scp->ctrl_reg.pwr_sta2nd_offs = scp_ctrl_reg->pwr_sta2nd_offs;
>
> - scp->bus_prot_reg_update = bus_prot_reg_update;
> -
> scp->dev = &pdev->dev;
>
> res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> @@ -448,6 +436,17 @@ static struct scp *init_scp(struct platform_device *pdev,
> return ERR_CAST(scp->infracfg);
> }
>
> + scp->smi_common = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
> + "smi_comm");
> +
> + if (scp->smi_common == ERR_PTR(-ENODEV)) {
> + scp->smi_common = NULL;
> + } else if (IS_ERR(scp->smi_common)) {
> + dev_err(&pdev->dev, "Cannot find smi_common controller: %ld\n",
> + PTR_ERR(scp->smi_common));
> + return ERR_CAST(scp->smi_common);
> + }
> +
> for (i = 0; i < num; i++) {
> struct scp_domain *scpd = &scp->domains[i];
> const struct scp_domain_data *data = &scp_domain_data[i];
> @@ -530,8 +529,11 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .name = "conn",
> .sta_mask = PWR_STATUS_CONN,
> .ctl_offs = SPM_CONN_PWR_CON,
> - .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_CONN_M |
> - MT2701_TOP_AXI_PROT_EN_CONN_S,
> + .bp_table = {
> + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
> + MT2701_TOP_AXI_PROT_EN_CONN_M |
> + MT2701_TOP_AXI_PROT_EN_CONN_S),
> + },
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> [MT2701_POWER_DOMAIN_DISP] = {
> @@ -540,7 +542,10 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_DIS_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> .basic_clk_name = {"mm"},
> - .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_MM_M0,
> + .bp_table = {
> + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
> + MT2701_TOP_AXI_PROT_EN_MM_M0),
> + },
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> [MT2701_POWER_DOMAIN_MFG] = {
> @@ -675,7 +680,10 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .sram_pdn_bits = GENMASK(8, 8),
> .sram_pdn_ack_bits = GENMASK(16, 16),
> .basic_clk_name = {"mfg"},
> - .bus_prot_mask = BIT(14) | BIT(21) | BIT(23),
> + .bp_table = {
> + BUS_PROT(IFR_TYPE, 0x260, 0x264, 0x220, 0x228,
> + BIT(14) | BIT(21) | BIT(23)),
> + },
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> [MT2712_POWER_DOMAIN_MFG_SC1] = {
> @@ -747,7 +755,10 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .sram_pdn_bits = GENMASK(8, 8),
> .sram_pdn_ack_bits = GENMASK(12, 12),
> .basic_clk_name = {"mm"},
> - .bus_prot_mask = (BIT(1) | BIT(2)),
> + .bp_table = {
> + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
> + BIT(1) | BIT(2)),
> + },
> },
> [MT6797_POWER_DOMAIN_AUDIO] = {
> .name = "audio",
> @@ -794,7 +805,10 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_ETHSYS_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = GENMASK(15, 12),
> - .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_ETHSYS,
> + .bp_table = {
> + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
> + MT7622_TOP_AXI_PROT_EN_ETHSYS),
> + },
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> [MT7622_POWER_DOMAIN_HIF0] = {
> @@ -804,7 +818,10 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = GENMASK(15, 12),
> .basic_clk_name = {"hif_sel"},
> - .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_HIF0,
> + .bp_table = {
> + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
> + MT7622_TOP_AXI_PROT_EN_HIF0),
> + },
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> [MT7622_POWER_DOMAIN_HIF1] = {
> @@ -814,7 +831,10 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = GENMASK(15, 12),
> .basic_clk_name = {"hif_sel"},
> - .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_HIF1,
> + .bp_table = {
> + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
> + MT7622_TOP_AXI_PROT_EN_HIF1),
> + },
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> [MT7622_POWER_DOMAIN_WB] = {
> @@ -823,7 +843,10 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_WB_PWR_CON,
> .sram_pdn_bits = 0,
> .sram_pdn_ack_bits = 0,
> - .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_WB,
> + .bp_table = {
> + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
> + MT7622_TOP_AXI_PROT_EN_WB),
> + },
> .caps = MTK_SCPD_ACTIVE_WAKEUP | MTK_SCPD_FWAIT_SRAM,
> },
> };
> @@ -837,8 +860,11 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .name = "conn",
> .sta_mask = PWR_STATUS_CONN,
> .ctl_offs = SPM_CONN_PWR_CON,
> - .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_CONN_M |
> - MT2701_TOP_AXI_PROT_EN_CONN_S,
> + .bp_table = {
> + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
> + MT2701_TOP_AXI_PROT_EN_CONN_M |
> + MT2701_TOP_AXI_PROT_EN_CONN_S),
> + },
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> [MT7623A_POWER_DOMAIN_ETH] = {
> @@ -903,8 +929,11 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = GENMASK(12, 12),
> .basic_clk_name = {"mm"},
> - .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 |
> - MT8173_TOP_AXI_PROT_EN_MM_M1,
> + .bp_table = {
> + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
> + MT8173_TOP_AXI_PROT_EN_MM_M0 |
> + MT8173_TOP_AXI_PROT_EN_MM_M1),
> + },
> },
> [MT8173_POWER_DOMAIN_VENC_LT] = {
> .name = "venc_lt",
> @@ -950,10 +979,13 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_MFG_PWR_CON,
> .sram_pdn_bits = GENMASK(13, 8),
> .sram_pdn_ack_bits = GENMASK(21, 16),
> - .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MFG_S |
> - MT8173_TOP_AXI_PROT_EN_MFG_M0 |
> - MT8173_TOP_AXI_PROT_EN_MFG_M1 |
> - MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT,
> + .bp_table = {
> + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
> + MT8173_TOP_AXI_PROT_EN_MFG_S |
> + MT8173_TOP_AXI_PROT_EN_MFG_M0 |
> + MT8173_TOP_AXI_PROT_EN_MFG_M1 |
> + MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT),
> + },
> },
> };
>
> @@ -969,7 +1001,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .pwr_sta_offs = SPM_PWR_STATUS,
> .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
> },
> - .bus_prot_reg_update = true,
> };
>
> static const struct scp_soc_data mt2712_data = {
> @@ -981,7 +1012,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .pwr_sta_offs = SPM_PWR_STATUS,
> .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
> },
> - .bus_prot_reg_update = false,
> };
>
> static const struct scp_soc_data mt6797_data = {
> @@ -993,7 +1023,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .pwr_sta_offs = SPM_PWR_STATUS_MT6797,
> .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND_MT6797
> },
> - .bus_prot_reg_update = true,
> };
>
> static const struct scp_soc_data mt7622_data = {
> @@ -1003,7 +1032,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .pwr_sta_offs = SPM_PWR_STATUS,
> .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
> },
> - .bus_prot_reg_update = true,
> };
>
> static const struct scp_soc_data mt7623a_data = {
> @@ -1013,7 +1041,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .pwr_sta_offs = SPM_PWR_STATUS,
> .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
> },
> - .bus_prot_reg_update = true,
> };
>
> static const struct scp_soc_data mt8173_data = {
> @@ -1025,7 +1052,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .pwr_sta_offs = SPM_PWR_STATUS,
> .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
> },
> - .bus_prot_reg_update = true,
> };
>
> /*
> @@ -1066,8 +1092,7 @@ static int scpsys_probe(struct platform_device *pdev)
>
> soc = of_device_get_match_data(&pdev->dev);
>
> - scp = init_scp(pdev, soc->domains, soc->num_domains, &soc->regs,
> - soc->bus_prot_reg_update);
> + scp = init_scp(pdev, soc->domains, soc->num_domains, &soc->regs);
> if (IS_ERR(scp))
> return PTR_ERR(scp);
>
> diff --git a/drivers/soc/mediatek/scpsys-ext.h b/drivers/soc/mediatek/scpsys-ext.h
> new file mode 100644
> index 0000000..458b2c5
> --- /dev/null
> +++ b/drivers/soc/mediatek/scpsys-ext.h
> @@ -0,0 +1,67 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +#ifndef __SOC_MEDIATEK_SCPSYS_EXT_H
> +#define __SOC_MEDIATEK_SCPSYS_EXT_H
> +
> +#define MAX_STEPS 4
> +
> +#define _BUS_PROT(_type, _set_ofs, _clr_ofs, \
> + _en_ofs, _sta_ofs, _mask, _ignore_clr_ack) { \
> + .type = _type, \
> + .set_ofs = _set_ofs, \
> + .clr_ofs = _clr_ofs, \
> + .en_ofs = _en_ofs, \
> + .sta_ofs = _sta_ofs, \
> + .mask = _mask, \
> + .ignore_clr_ack = _ignore_clr_ack, \
> + }
> +
> +#define BUS_PROT(_type, _set_ofs, _clr_ofs, \
> + _en_ofs, _sta_ofs, _mask) \
> + _BUS_PROT(_type, _set_ofs, _clr_ofs, \
> + _en_ofs, _sta_ofs, _mask, false)
> +
> +#define BUS_PROT_IGN(_type, _set_ofs, _clr_ofs, \
> + _en_ofs, _sta_ofs, _mask) \
> + _BUS_PROT(_type, _set_ofs, _clr_ofs, \
> + _en_ofs, _sta_ofs, _mask, true)
> +
> +#define MT2701_TOP_AXI_PROT_EN_MM_M0 BIT(1)
> +#define MT2701_TOP_AXI_PROT_EN_CONN_M BIT(2)
> +#define MT2701_TOP_AXI_PROT_EN_CONN_S BIT(8)
> +
> +#define MT7622_TOP_AXI_PROT_EN_ETHSYS (BIT(3) | BIT(17))
> +#define MT7622_TOP_AXI_PROT_EN_HIF0 (BIT(24) | BIT(25))
> +#define MT7622_TOP_AXI_PROT_EN_HIF1 (BIT(26) | BIT(27) | \
> + BIT(28))
> +#define MT7622_TOP_AXI_PROT_EN_WB (BIT(2) | BIT(6) | \
> + BIT(7) | BIT(8))
> +
> +#define MT8173_TOP_AXI_PROT_EN_MM_M0 BIT(1)
> +#define MT8173_TOP_AXI_PROT_EN_MM_M1 BIT(2)
> +#define MT8173_TOP_AXI_PROT_EN_MFG_S BIT(14)
> +#define MT8173_TOP_AXI_PROT_EN_MFG_M0 BIT(21)
> +#define MT8173_TOP_AXI_PROT_EN_MFG_M1 BIT(22)
> +#define MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT BIT(23)
> +
> +enum regmap_type {
> + INVALID_TYPE = 0,
> + IFR_TYPE,
> + SMI_TYPE,
> +};
> +
> +struct bus_prot {
> + enum regmap_type type;
> + u32 set_ofs;
> + u32 clr_ofs;
Please try to keep variable names consistent. You change for example set_ofs to
reg_set. That makes the code more difficult to read and understand.
> + u32 en_ofs;
> + u32 sta_ofs;
> + u32 mask;
> + bool ignore_clr_ack;
> +};
> +
> +int mtk_scpsys_ext_set_bus_protection(const struct bus_prot *bp_table,
> + struct regmap *infracfg, struct regmap *smi_common);
> +int mtk_scpsys_ext_clear_bus_protection(const struct bus_prot *bp_table,
> + struct regmap *infracfg, struct regmap *smi_common);
> +
> +#endif /* __SOC_MEDIATEK_SCPSYS_EXT_H */
>
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v11 06/10] soc: mediatek: Add subsys clock control for bus protection
2019-12-20 3:46 ` [PATCH v11 06/10] soc: mediatek: Add subsys clock control for bus protection Weiyi Lu
@ 2020-02-11 17:54 ` Matthias Brugger
2020-02-12 2:55 ` Weiyi Lu
0 siblings, 1 reply; 33+ messages in thread
From: Matthias Brugger @ 2020-02-11 17:54 UTC (permalink / raw)
To: Weiyi Lu, Nicolas Boichat, Rob Herring, Sascha Hauer
Cc: James Liao, Fan Chen, linux-arm-kernel, linux-kernel,
linux-mediatek, srv_heupstream
On 20/12/2019 04:46, Weiyi Lu wrote:
> Add subsys CG control flow before/after the bus protect control
> due to bus protection need SMI bus relative CGs enabled to feedback
> its ack.
>
Sorry, I don't understand the commit message. Can you please rephrase and
explain better what this change is for.
> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
> ---
> drivers/soc/mediatek/mtk-scpsys.c | 72 +++++++++++++++++++++++++++++++++++++--
> 1 file changed, 70 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
> index 763ca58..32be4b3 100644
> --- a/drivers/soc/mediatek/mtk-scpsys.c
> +++ b/drivers/soc/mediatek/mtk-scpsys.c
> @@ -79,6 +79,7 @@
> #define PWR_STATUS_WB BIT(27) /* MT7622 */
>
> #define MAX_CLKS 3
> +#define MAX_SUBSYS_CLKS 10
>
> /**
> * struct scp_domain_data - scp domain data for power on/off flow
> @@ -88,6 +89,8 @@
> * @sram_pdn_bits: The mask for sram power control bits.
> * @sram_pdn_ack_bits: The mask for sram power control acked bits.
> * @basic_clk_name: The basic clocks required by this power domain.
> + * @subsys_clk_prefix: The prefix name of the clocks need to be enabled
> + * before releasing bus protection.
> * @caps: The flag for active wake-up action.
> * @bp_table: The mask table for multiple step bus protection.
> */
> @@ -98,6 +101,7 @@ struct scp_domain_data {
> u32 sram_pdn_bits;
> u32 sram_pdn_ack_bits;
> const char *basic_clk_name[MAX_CLKS];
> + const char *subsys_clk_prefix;
> u8 caps;
> struct bus_prot bp_table[MAX_STEPS];
> };
> @@ -108,6 +112,7 @@ struct scp_domain {
> struct generic_pm_domain genpd;
> struct scp *scp;
> struct clk *clk[MAX_CLKS];
> + struct clk *subsys_clk[MAX_SUBSYS_CLKS];
> const struct scp_domain_data *data;
> struct regulator *supply;
> };
> @@ -301,16 +306,22 @@ static int scpsys_power_on(struct generic_pm_domain *genpd)
> val |= PWR_RST_B_BIT;
> writel(val, ctl_addr);
>
> - ret = scpsys_sram_enable(scpd, ctl_addr);
> + ret = scpsys_clk_enable(scpd->subsys_clk, MAX_SUBSYS_CLKS);
Why can't we enable the subsystem clocks together with the rest just after
enabeling the regulator?
> if (ret < 0)
> goto err_pwr_ack;
>
> + ret = scpsys_sram_enable(scpd, ctl_addr);
> + if (ret < 0)
> + goto err_sram;
> +
> ret = scpsys_bus_protect_disable(scpd);
> if (ret < 0)
> - goto err_pwr_ack;
> + goto err_sram;
>
> return 0;
>
> +err_sram:
> + scpsys_clk_disable(scpd->subsys_clk, MAX_SUBSYS_CLKS);
> err_pwr_ack:
> scpsys_clk_disable(scpd->clk, MAX_CLKS);
> err_clk:
> @@ -337,6 +348,8 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
> if (ret < 0)
> goto out;
>
> + scpsys_clk_disable(scpd->subsys_clk, MAX_SUBSYS_CLKS);
> +
Same here, why can't we disable the clocks in the scpsys_clk_disable call?
> /* subsys power off */
> val = readl(ctl_addr);
> val |= PWR_ISO_BIT;
> @@ -374,6 +387,48 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
> return ret;
> }
>
> +static int init_subsys_clks(struct platform_device *pdev,
> + const char *prefix, struct clk **clk)
> +{
> + struct device_node *node = pdev->dev.of_node;
> + u32 prefix_len, sub_clk_cnt = 0;
> + struct property *prop;
> + const char *clk_name;
> +
> + if (!node) {
> + dev_err(&pdev->dev, "Cannot find scpsys node: %ld\n",
> + PTR_ERR(node));
> + return PTR_ERR(node);
> + }
> +
> + prefix_len = strlen(prefix);
> +
> + of_property_for_each_string(node, "clock-names", prop, clk_name) {
> + if (!strncmp(clk_name, prefix, prefix_len) &&
> + (clk_name[prefix_len] == '-')) {
> + if (sub_clk_cnt >= MAX_SUBSYS_CLKS) {
> + dev_err(&pdev->dev,
> + "subsys clk out of range %d\n",
> + sub_clk_cnt);
> + return -ENOMEM;
EINVAL maybe, ENOMEM seems wrong here.
> + }
> +
> + clk[sub_clk_cnt] = devm_clk_get(&pdev->dev,
> + clk_name);
Here we get hit by the bad design of this driver in the first place. As we need
the subsystem-name (eg mm-0, mm-1) to group clocks to one scp_domain.
I think we should better try to model the domains and subdomains in DTS and add
their clocks to it. This way we can also get rid of the scp_subdomain which can
hit it's limit anytime soon when we have a chip with a sub-subdomain.
That will need a new driver, but as it seems the mt8183 and the mt6765 have a
more complex design I think it is worth it.
That said, given that you are in v11 already I understand that your motivation
to start over isn't the biggest. The problem is, any new driver will have new
bindings and won't work with older DTS. So adding a lot of stuff on top of a not
really nice driver isn't something I'm very keen on. On the other hand you
already put a lot of work into this solution.
My proposal, I'll try to bake up a new driver this week. If I fail to deliver,
it's up to you to decide if you want to go on with the approach in this series
or try to work on the new one.
Regards,
Matthias
> +
> + if (IS_ERR(clk[sub_clk_cnt])) {
> + dev_err(&pdev->dev,
> + "Subsys clk get fail %ld\n",
> + PTR_ERR(clk[sub_clk_cnt]));
> + return PTR_ERR(clk[sub_clk_cnt]);
> + }
> + sub_clk_cnt++;
> + }
> + }
> +
> + return sub_clk_cnt;
> +}
> +
> static int init_basic_clks(struct platform_device *pdev, struct clk **clk,
> const char * const *name)
> {
> @@ -466,6 +521,7 @@ static struct scp *init_scp(struct platform_device *pdev,
> struct scp_domain *scpd = &scp->domains[i];
> struct generic_pm_domain *genpd = &scpd->genpd;
> const struct scp_domain_data *data = &scp_domain_data[i];
> + int clk_cnt;
clk_cnt sounds to me like clock count, but the variable actually is only used to
check the return value of init_subsys_clks. Please rename it to ret or something
like this.
>
> pd_data->domains[i] = genpd;
> scpd->scp = scp;
> @@ -476,6 +532,18 @@ static struct scp *init_scp(struct platform_device *pdev,
> if (ret)
> return ERR_PTR(ret);
>
> + if (data->subsys_clk_prefix) {
> + clk_cnt = init_subsys_clks(pdev,
> + data->subsys_clk_prefix,
> + scpd->subsys_clk);
> + if (clk_cnt < 0) {
> + dev_err(&pdev->dev,
> + "%s: subsys clk unavailable\n",
> + data->name);
> + return ERR_PTR(clk_cnt);
> + }
> + }
> +
> genpd->name = data->name;
> genpd->power_off = scpsys_power_off;
> genpd->power_on = scpsys_power_on;
>
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v11 06/10] soc: mediatek: Add subsys clock control for bus protection
2020-02-11 17:54 ` Matthias Brugger
@ 2020-02-12 2:55 ` Weiyi Lu
2020-02-12 11:02 ` Matthias Brugger
0 siblings, 1 reply; 33+ messages in thread
From: Weiyi Lu @ 2020-02-12 2:55 UTC (permalink / raw)
To: Matthias Brugger
Cc: Nicolas Boichat, Rob Herring, Sascha Hauer, James Liao, Fan Chen,
linux-arm-kernel, linux-kernel, linux-mediatek, srv_heupstream
On Tue, 2020-02-11 at 18:54 +0100, Matthias Brugger wrote:
>
> On 20/12/2019 04:46, Weiyi Lu wrote:
> > Add subsys CG control flow before/after the bus protect control
> > due to bus protection need SMI bus relative CGs enabled to feedback
> > its ack.
> >
>
> Sorry, I don't understand the commit message. Can you please rephrase and
> explain better what this change is for.
>
OK! I'll reword it.
> > Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> > Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
> > ---
> > drivers/soc/mediatek/mtk-scpsys.c | 72 +++++++++++++++++++++++++++++++++++++--
> > 1 file changed, 70 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
> > index 763ca58..32be4b3 100644
> > --- a/drivers/soc/mediatek/mtk-scpsys.c
> > +++ b/drivers/soc/mediatek/mtk-scpsys.c
> > @@ -79,6 +79,7 @@
> > #define PWR_STATUS_WB BIT(27) /* MT7622 */
> >
> > #define MAX_CLKS 3
> > +#define MAX_SUBSYS_CLKS 10
> >
> > /**
> > * struct scp_domain_data - scp domain data for power on/off flow
> > @@ -88,6 +89,8 @@
> > * @sram_pdn_bits: The mask for sram power control bits.
> > * @sram_pdn_ack_bits: The mask for sram power control acked bits.
> > * @basic_clk_name: The basic clocks required by this power domain.
> > + * @subsys_clk_prefix: The prefix name of the clocks need to be enabled
> > + * before releasing bus protection.
> > * @caps: The flag for active wake-up action.
> > * @bp_table: The mask table for multiple step bus protection.
> > */
> > @@ -98,6 +101,7 @@ struct scp_domain_data {
> > u32 sram_pdn_bits;
> > u32 sram_pdn_ack_bits;
> > const char *basic_clk_name[MAX_CLKS];
> > + const char *subsys_clk_prefix;
> > u8 caps;
> > struct bus_prot bp_table[MAX_STEPS];
> > };
> > @@ -108,6 +112,7 @@ struct scp_domain {
> > struct generic_pm_domain genpd;
> > struct scp *scp;
> > struct clk *clk[MAX_CLKS];
> > + struct clk *subsys_clk[MAX_SUBSYS_CLKS];
> > const struct scp_domain_data *data;
> > struct regulator *supply;
> > };
> > @@ -301,16 +306,22 @@ static int scpsys_power_on(struct generic_pm_domain *genpd)
> > val |= PWR_RST_B_BIT;
> > writel(val, ctl_addr);
> >
> > - ret = scpsys_sram_enable(scpd, ctl_addr);
> > + ret = scpsys_clk_enable(scpd->subsys_clk, MAX_SUBSYS_CLKS);
>
> Why can't we enable the subsystem clocks together with the rest just after
> enabeling the regulator?
>
Subsys CG could only be enabled when its own power domain is already
turned ON, and vice versa.
In the dt-binding doc we mentioned there would have two groups of
clocks.
e.g.,
BASIC clocks need to be enabled before enabling the corresponding power
domain.
SUBSYS clocks need to be enabled before releasing the bus protection.
> > if (ret < 0)
> > goto err_pwr_ack;
> >
> > + ret = scpsys_sram_enable(scpd, ctl_addr);
> > + if (ret < 0)
> > + goto err_sram;
> > +
> > ret = scpsys_bus_protect_disable(scpd);
> > if (ret < 0)
> > - goto err_pwr_ack;
> > + goto err_sram;
> >
> > return 0;
> >
> > +err_sram:
> > + scpsys_clk_disable(scpd->subsys_clk, MAX_SUBSYS_CLKS);
> > err_pwr_ack:
> > scpsys_clk_disable(scpd->clk, MAX_CLKS);
> > err_clk:
> > @@ -337,6 +348,8 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
> > if (ret < 0)
> > goto out;
> >
> > + scpsys_clk_disable(scpd->subsys_clk, MAX_SUBSYS_CLKS);
> > +
>
> Same here, why can't we disable the clocks in the scpsys_clk_disable call?
>
> > /* subsys power off */
> > val = readl(ctl_addr);
> > val |= PWR_ISO_BIT;
> > @@ -374,6 +387,48 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
> > return ret;
> > }
> >
> > +static int init_subsys_clks(struct platform_device *pdev,
> > + const char *prefix, struct clk **clk)
> > +{
> > + struct device_node *node = pdev->dev.of_node;
> > + u32 prefix_len, sub_clk_cnt = 0;
> > + struct property *prop;
> > + const char *clk_name;
> > +
> > + if (!node) {
> > + dev_err(&pdev->dev, "Cannot find scpsys node: %ld\n",
> > + PTR_ERR(node));
> > + return PTR_ERR(node);
> > + }
> > +
> > + prefix_len = strlen(prefix);
> > +
> > + of_property_for_each_string(node, "clock-names", prop, clk_name) {
> > + if (!strncmp(clk_name, prefix, prefix_len) &&
> > + (clk_name[prefix_len] == '-')) {
> > + if (sub_clk_cnt >= MAX_SUBSYS_CLKS) {
> > + dev_err(&pdev->dev,
> > + "subsys clk out of range %d\n",
> > + sub_clk_cnt);
> > + return -ENOMEM;
>
> EINVAL maybe, ENOMEM seems wrong here.
>
OK, I'll fix with correct error.
> > + }
> > +
> > + clk[sub_clk_cnt] = devm_clk_get(&pdev->dev,
> > + clk_name);
>
> Here we get hit by the bad design of this driver in the first place. As we need
> the subsystem-name (eg mm-0, mm-1) to group clocks to one scp_domain.
> I think we should better try to model the domains and subdomains in DTS and add
> their clocks to it. This way we can also get rid of the scp_subdomain which can
> hit it's limit anytime soon when we have a chip with a sub-subdomain.
> That will need a new driver, but as it seems the mt8183 and the mt6765 have a
> more complex design I think it is worth it.
>
> That said, given that you are in v11 already I understand that your motivation
> to start over isn't the biggest. The problem is, any new driver will have new
> bindings and won't work with older DTS. So adding a lot of stuff on top of a not
> really nice driver isn't something I'm very keen on. On the other hand you
> already put a lot of work into this solution.
>
> My proposal, I'll try to bake up a new driver this week. If I fail to deliver,
> it's up to you to decide if you want to go on with the approach in this series
> or try to work on the new one.
> Regards,
> Matthias
>
Thanks for considering our request.
> > +
> > + if (IS_ERR(clk[sub_clk_cnt])) {
> > + dev_err(&pdev->dev,
> > + "Subsys clk get fail %ld\n",
> > + PTR_ERR(clk[sub_clk_cnt]));
> > + return PTR_ERR(clk[sub_clk_cnt]);
> > + }
> > + sub_clk_cnt++;
> > + }
> > + }
> > +
> > + return sub_clk_cnt;
> > +}
> > +
> > static int init_basic_clks(struct platform_device *pdev, struct clk **clk,
> > const char * const *name)
> > {
> > @@ -466,6 +521,7 @@ static struct scp *init_scp(struct platform_device *pdev,
> > struct scp_domain *scpd = &scp->domains[i];
> > struct generic_pm_domain *genpd = &scpd->genpd;
> > const struct scp_domain_data *data = &scp_domain_data[i];
> > + int clk_cnt;
>
> clk_cnt sounds to me like clock count, but the variable actually is only used to
> check the return value of init_subsys_clks. Please rename it to ret or something
> like this.
>
OK, I'll fix it.
> >
> > pd_data->domains[i] = genpd;
> > scpd->scp = scp;
> > @@ -476,6 +532,18 @@ static struct scp *init_scp(struct platform_device *pdev,
> > if (ret)
> > return ERR_PTR(ret);
> >
> > + if (data->subsys_clk_prefix) {
> > + clk_cnt = init_subsys_clks(pdev,
> > + data->subsys_clk_prefix,
> > + scpd->subsys_clk);
> > + if (clk_cnt < 0) {
> > + dev_err(&pdev->dev,
> > + "%s: subsys clk unavailable\n",
> > + data->name);
> > + return ERR_PTR(clk_cnt);
> > + }
> > + }
> > +
> > genpd->name = data->name;
> > genpd->power_off = scpsys_power_off;
> > genpd->power_on = scpsys_power_on;
> >
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v11 04/10] soc: mediatek: Add multiple step bus protection control
2020-02-11 17:49 ` Matthias Brugger
@ 2020-02-12 2:55 ` Weiyi Lu
2020-02-12 9:23 ` Matthias Brugger
0 siblings, 1 reply; 33+ messages in thread
From: Weiyi Lu @ 2020-02-12 2:55 UTC (permalink / raw)
To: Matthias Brugger
Cc: Nicolas Boichat, Rob Herring, Sascha Hauer, James Liao, Fan Chen,
linux-arm-kernel, linux-kernel, linux-mediatek, srv_heupstream
On Tue, 2020-02-11 at 18:49 +0100, Matthias Brugger wrote:
>
> On 20/12/2019 04:45, Weiyi Lu wrote:
> > Both MT8183 & MT6765 have more control steps of bus protection
> > than previous project. And there add more bus protection registers
> > reside at infracfg & smi-common. Also add new APIs for multiple
> > step bus protection control with more customized arguments.
> > And then use bp_table for bus protection of all compatibles,
> > instead of mixing bus_prot_mask and bus_prot_reg_update.
> >
> > Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> > ---
> > drivers/soc/mediatek/Makefile | 2 +-
> > drivers/soc/mediatek/mtk-scpsys-ext.c | 101 +++++++++++++++++++++++++++++
> > drivers/soc/mediatek/mtk-scpsys.c | 117 +++++++++++++++++++++-------------
> > drivers/soc/mediatek/scpsys-ext.h | 67 +++++++++++++++++++
> > 4 files changed, 240 insertions(+), 47 deletions(-)
> > create mode 100644 drivers/soc/mediatek/mtk-scpsys-ext.c
> > create mode 100644 drivers/soc/mediatek/scpsys-ext.h
> >
> > diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
> > index b017330..b442be9 100644
> > --- a/drivers/soc/mediatek/Makefile
> > +++ b/drivers/soc/mediatek/Makefile
> > @@ -1,5 +1,5 @@
> > # SPDX-License-Identifier: GPL-2.0-only
> > obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o
> > -obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
> > +obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o mtk-scpsys-ext.o
>
> It seems that we would need another patch which get's rid of the mtk-infracfg
> first and then add stuff like the possibility to have different steps.
>
Actually I have a PATCH 05/11 to remove the mtk-infracfg.
In this patch, I have some changes, like calling
mtk_scpsys_ext_set_bus_protection(...) instead of
mtk_infracfg_set_bus_protection(...) in scpsys_bus_protect_enable(...)
and replacing bus_prot_mask by bp_table.
I thought I should introduce the new method first and remove useless one
later. What do you think?
> > obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
> > obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
> > diff --git a/drivers/soc/mediatek/mtk-scpsys-ext.c b/drivers/soc/mediatek/mtk-scpsys-ext.c
> > new file mode 100644
> > index 0000000..df402ac
> > --- /dev/null
> > +++ b/drivers/soc/mediatek/mtk-scpsys-ext.c
>
> I'm not quite sure why we should put this into a new file. I suppose the
> rational behind it is the fact that we access other blocks through regmap.
>
Yes, those operation are accross infracfg and smi-common so we put these
into new files.
> > @@ -0,0 +1,101 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (c) 2018 MediaTek Inc.
> > + * Author: Owen Chen <Owen.Chen@mediatek.com>
> > + */
> > +#include <linux/ktime.h>
> > +#include <linux/mfd/syscon.h>
> > +#include <linux/of_device.h>
> > +#include <linux/regmap.h>
> > +#include "scpsys-ext.h"
> > +
> > +#define MTK_POLL_DELAY_US 10
> > +#define MTK_POLL_TIMEOUT USEC_PER_SEC
> > +
> > +static int set_bus_protection(struct regmap *map, u32 mask,
> > + u32 reg_set, u32 reg_sta, u32 reg_en)
> > +{
> > + u32 val;
> > +
> > + if (reg_set)
> > + regmap_write(map, reg_set, mask);
> > + else
> > + regmap_update_bits(map, reg_en, mask, mask);
> > +
> > + return regmap_read_poll_timeout(map, reg_sta,
> > + val, (val & mask) == mask,
> > + MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
> > +}
> > +
> > +static int clear_bus_protection(struct regmap *map, u32 mask,
> > + u32 reg_clr, u32 reg_sta, u32 reg_en, bool ignore_ack)
> > +{
> > + u32 val;
> > +
> > + if (reg_clr)
> > + regmap_write(map, reg_clr, mask);
> > + else
> > + regmap_update_bits(map, reg_en, mask, 0);
> > +
> > + if (ignore_ack)
> > + return 0;
> > +
> > + return regmap_read_poll_timeout(map, reg_sta,
> > + val, !(val & mask),
> > + MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
> > +}
> > +
> > +int mtk_scpsys_ext_set_bus_protection(const struct bus_prot *bp_table,
> > + struct regmap *infracfg, struct regmap *smi_common)
> > +{
> > + int i;
> > +
> > + for (i = 0; i < MAX_STEPS; i++) {
>
> struct bus_prot bp_table = bp_table[i];
>
OK, got it.
> > + struct regmap *map = NULL;
> > + int ret;
> > +
> > + if (bp_table[i].type == INVALID_TYPE)
> > + break;
> > + else if (bp_table[i].type == IFR_TYPE)
> > + map = infracfg;
> > + else if (bp_table[i].type == SMI_TYPE)
> > + map = smi_common;
>
> if (bp_table.type == IFR_TYPE)
> map = infracfg;
> else if (bp_table.type == SMI_TYPE)
> map = smi_common;
> else
> break;
>
OK, got it.
> > +
> > + ret = set_bus_protection(map,
> > + bp_table[i].mask, bp_table[i].set_ofs,
> > + bp_table[i].sta_ofs, bp_table[i].en_ofs);
>
> passing map and bp_table here makes code much more readable. I always end-up
> counting the variables when the names in the callee changes.
>
OK, I'll fix it.
> > +
> > + if (ret)
> > + return ret;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +int mtk_scpsys_ext_clear_bus_protection(const struct bus_prot *bp_table,
> > + struct regmap *infracfg, struct regmap *smi_common)
> > +{
> > + int i;
> > +
> > + for (i = MAX_STEPS - 1; i >= 0; i--) {
> > + struct regmap *map = NULL;
> > + int ret;
> > +
> > + if (bp_table[i].type == INVALID_TYPE)
> > + continue;
> > + else if (bp_table[i].type == IFR_TYPE)
> > + map = infracfg;
> > + else if (bp_table[i].type == SMI_TYPE)
> > + map = smi_common;
> > +
> > + ret = clear_bus_protection(map,
> > + bp_table[i].mask, bp_table[i].clr_ofs,
> > + bp_table[i].sta_ofs, bp_table[i].en_ofs,
> > + bp_table[i].ignore_clr_ack);
> > +
>
> same here.
>
Got it.
> > + if (ret)
> > + return ret;
> > + }
> > +
> > + return 0;
> > +}
> > diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
> > index db35a28..763ca58 100644
> > --- a/drivers/soc/mediatek/mtk-scpsys.c
> > +++ b/drivers/soc/mediatek/mtk-scpsys.c
> > @@ -11,7 +11,7 @@
> > #include <linux/platform_device.h>
> > #include <linux/pm_domain.h>
> > #include <linux/regulator/consumer.h>
> > -#include <linux/soc/mediatek/infracfg.h>
> > +#include "scpsys-ext.h"
> >
> > #include <dt-bindings/power/mt2701-power.h>
> > #include <dt-bindings/power/mt2712-power.h>
> > @@ -87,9 +87,9 @@
> > * @ctl_offs: The offset for main power control register.
> > * @sram_pdn_bits: The mask for sram power control bits.
> > * @sram_pdn_ack_bits: The mask for sram power control acked bits.
> > - * @bus_prot_mask: The mask for single step bus protection.
> > * @basic_clk_name: The basic clocks required by this power domain.
> > * @caps: The flag for active wake-up action.
> > + * @bp_table: The mask table for multiple step bus protection.
> > */
> > struct scp_domain_data {
> > const char *name;
> > @@ -97,9 +97,9 @@ struct scp_domain_data {
> > int ctl_offs;
> > u32 sram_pdn_bits;
> > u32 sram_pdn_ack_bits;
> > - u32 bus_prot_mask;
> > const char *basic_clk_name[MAX_CLKS];
> > u8 caps;
> > + struct bus_prot bp_table[MAX_STEPS];
> > };
> >
> > struct scp;
> > @@ -123,8 +123,8 @@ struct scp {
> > struct device *dev;
> > void __iomem *base;
> > struct regmap *infracfg;
> > + struct regmap *smi_common;
> > struct scp_ctrl_reg ctrl_reg;
> > - bool bus_prot_reg_update;
> > };
> >
> > struct scp_subdomain {
> > @@ -138,7 +138,6 @@ struct scp_soc_data {
> > const struct scp_subdomain *subdomains;
> > int num_subdomains;
> > const struct scp_ctrl_reg regs;
> > - bool bus_prot_reg_update;
> > };
> >
> > static int scpsys_domain_is_on(struct scp_domain *scpd)
> > @@ -252,24 +251,16 @@ static int scpsys_bus_protect_enable(struct scp_domain *scpd)
> > {
> > struct scp *scp = scpd->scp;
> >
> > - if (!scpd->data->bus_prot_mask)
> > - return 0;
> > -
> > - return mtk_infracfg_set_bus_protection(scp->infracfg,
> > - scpd->data->bus_prot_mask,
> > - scp->bus_prot_reg_update);
> > + return mtk_scpsys_ext_set_bus_protection(scpd->data->bp_table,
> > + scp->infracfg, scp->smi_common);
>
> Now that's just a wrapper which does add nothing but another indirection. We can
> call mtk_scpsys_ext_set_bus_protection() directly (also I don't like the name,
> actually why don't mtk_scpsys_set_bus_protection()?)
>
You're right. I'll called mtk_scpsys_ext_set_bus_protection() directly.
> > }
> >
> > static int scpsys_bus_protect_disable(struct scp_domain *scpd)
> > {
> > struct scp *scp = scpd->scp;
> >
> > - if (!scpd->data->bus_prot_mask)
> > - return 0;
> > -
> > - return mtk_infracfg_clear_bus_protection(scp->infracfg,
> > - scpd->data->bus_prot_mask,
> > - scp->bus_prot_reg_update);
> > + return mtk_scpsys_ext_clear_bus_protection(scpd->data->bp_table,
> > + scp->infracfg, scp->smi_common);
> > }
> >
> > static int scpsys_power_on(struct generic_pm_domain *genpd)
> > @@ -404,8 +395,7 @@ static int init_basic_clks(struct platform_device *pdev, struct clk **clk,
> >
> > static struct scp *init_scp(struct platform_device *pdev,
> > const struct scp_domain_data *scp_domain_data, int num,
> > - const struct scp_ctrl_reg *scp_ctrl_reg,
> > - bool bus_prot_reg_update)
> > + const struct scp_ctrl_reg *scp_ctrl_reg)
> > {
> > struct genpd_onecell_data *pd_data;
> > struct resource *res;
> > @@ -419,8 +409,6 @@ static struct scp *init_scp(struct platform_device *pdev,
> > scp->ctrl_reg.pwr_sta_offs = scp_ctrl_reg->pwr_sta_offs;
> > scp->ctrl_reg.pwr_sta2nd_offs = scp_ctrl_reg->pwr_sta2nd_offs;
> >
> > - scp->bus_prot_reg_update = bus_prot_reg_update;
> > -
> > scp->dev = &pdev->dev;
> >
> > res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > @@ -448,6 +436,17 @@ static struct scp *init_scp(struct platform_device *pdev,
> > return ERR_CAST(scp->infracfg);
> > }
> >
> > + scp->smi_common = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
> > + "smi_comm");
> > +
> > + if (scp->smi_common == ERR_PTR(-ENODEV)) {
> > + scp->smi_common = NULL;
> > + } else if (IS_ERR(scp->smi_common)) {
> > + dev_err(&pdev->dev, "Cannot find smi_common controller: %ld\n",
> > + PTR_ERR(scp->smi_common));
> > + return ERR_CAST(scp->smi_common);
> > + }
> > +
> > for (i = 0; i < num; i++) {
> > struct scp_domain *scpd = &scp->domains[i];
> > const struct scp_domain_data *data = &scp_domain_data[i];
> > @@ -530,8 +529,11 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > .name = "conn",
> > .sta_mask = PWR_STATUS_CONN,
> > .ctl_offs = SPM_CONN_PWR_CON,
> > - .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_CONN_M |
> > - MT2701_TOP_AXI_PROT_EN_CONN_S,
> > + .bp_table = {
> > + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
> > + MT2701_TOP_AXI_PROT_EN_CONN_M |
> > + MT2701_TOP_AXI_PROT_EN_CONN_S),
> > + },
> > .caps = MTK_SCPD_ACTIVE_WAKEUP,
> > },
> > [MT2701_POWER_DOMAIN_DISP] = {
> > @@ -540,7 +542,10 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > .ctl_offs = SPM_DIS_PWR_CON,
> > .sram_pdn_bits = GENMASK(11, 8),
> > .basic_clk_name = {"mm"},
> > - .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_MM_M0,
> > + .bp_table = {
> > + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
> > + MT2701_TOP_AXI_PROT_EN_MM_M0),
> > + },
> > .caps = MTK_SCPD_ACTIVE_WAKEUP,
> > },
> > [MT2701_POWER_DOMAIN_MFG] = {
> > @@ -675,7 +680,10 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > .sram_pdn_bits = GENMASK(8, 8),
> > .sram_pdn_ack_bits = GENMASK(16, 16),
> > .basic_clk_name = {"mfg"},
> > - .bus_prot_mask = BIT(14) | BIT(21) | BIT(23),
> > + .bp_table = {
> > + BUS_PROT(IFR_TYPE, 0x260, 0x264, 0x220, 0x228,
> > + BIT(14) | BIT(21) | BIT(23)),
> > + },
> > .caps = MTK_SCPD_ACTIVE_WAKEUP,
> > },
> > [MT2712_POWER_DOMAIN_MFG_SC1] = {
> > @@ -747,7 +755,10 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > .sram_pdn_bits = GENMASK(8, 8),
> > .sram_pdn_ack_bits = GENMASK(12, 12),
> > .basic_clk_name = {"mm"},
> > - .bus_prot_mask = (BIT(1) | BIT(2)),
> > + .bp_table = {
> > + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
> > + BIT(1) | BIT(2)),
> > + },
> > },
> > [MT6797_POWER_DOMAIN_AUDIO] = {
> > .name = "audio",
> > @@ -794,7 +805,10 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > .ctl_offs = SPM_ETHSYS_PWR_CON,
> > .sram_pdn_bits = GENMASK(11, 8),
> > .sram_pdn_ack_bits = GENMASK(15, 12),
> > - .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_ETHSYS,
> > + .bp_table = {
> > + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
> > + MT7622_TOP_AXI_PROT_EN_ETHSYS),
> > + },
> > .caps = MTK_SCPD_ACTIVE_WAKEUP,
> > },
> > [MT7622_POWER_DOMAIN_HIF0] = {
> > @@ -804,7 +818,10 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > .sram_pdn_bits = GENMASK(11, 8),
> > .sram_pdn_ack_bits = GENMASK(15, 12),
> > .basic_clk_name = {"hif_sel"},
> > - .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_HIF0,
> > + .bp_table = {
> > + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
> > + MT7622_TOP_AXI_PROT_EN_HIF0),
> > + },
> > .caps = MTK_SCPD_ACTIVE_WAKEUP,
> > },
> > [MT7622_POWER_DOMAIN_HIF1] = {
> > @@ -814,7 +831,10 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > .sram_pdn_bits = GENMASK(11, 8),
> > .sram_pdn_ack_bits = GENMASK(15, 12),
> > .basic_clk_name = {"hif_sel"},
> > - .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_HIF1,
> > + .bp_table = {
> > + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
> > + MT7622_TOP_AXI_PROT_EN_HIF1),
> > + },
> > .caps = MTK_SCPD_ACTIVE_WAKEUP,
> > },
> > [MT7622_POWER_DOMAIN_WB] = {
> > @@ -823,7 +843,10 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > .ctl_offs = SPM_WB_PWR_CON,
> > .sram_pdn_bits = 0,
> > .sram_pdn_ack_bits = 0,
> > - .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_WB,
> > + .bp_table = {
> > + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
> > + MT7622_TOP_AXI_PROT_EN_WB),
> > + },
> > .caps = MTK_SCPD_ACTIVE_WAKEUP | MTK_SCPD_FWAIT_SRAM,
> > },
> > };
> > @@ -837,8 +860,11 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > .name = "conn",
> > .sta_mask = PWR_STATUS_CONN,
> > .ctl_offs = SPM_CONN_PWR_CON,
> > - .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_CONN_M |
> > - MT2701_TOP_AXI_PROT_EN_CONN_S,
> > + .bp_table = {
> > + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
> > + MT2701_TOP_AXI_PROT_EN_CONN_M |
> > + MT2701_TOP_AXI_PROT_EN_CONN_S),
> > + },
> > .caps = MTK_SCPD_ACTIVE_WAKEUP,
> > },
> > [MT7623A_POWER_DOMAIN_ETH] = {
> > @@ -903,8 +929,11 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > .sram_pdn_bits = GENMASK(11, 8),
> > .sram_pdn_ack_bits = GENMASK(12, 12),
> > .basic_clk_name = {"mm"},
> > - .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 |
> > - MT8173_TOP_AXI_PROT_EN_MM_M1,
> > + .bp_table = {
> > + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
> > + MT8173_TOP_AXI_PROT_EN_MM_M0 |
> > + MT8173_TOP_AXI_PROT_EN_MM_M1),
> > + },
> > },
> > [MT8173_POWER_DOMAIN_VENC_LT] = {
> > .name = "venc_lt",
> > @@ -950,10 +979,13 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > .ctl_offs = SPM_MFG_PWR_CON,
> > .sram_pdn_bits = GENMASK(13, 8),
> > .sram_pdn_ack_bits = GENMASK(21, 16),
> > - .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MFG_S |
> > - MT8173_TOP_AXI_PROT_EN_MFG_M0 |
> > - MT8173_TOP_AXI_PROT_EN_MFG_M1 |
> > - MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT,
> > + .bp_table = {
> > + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
> > + MT8173_TOP_AXI_PROT_EN_MFG_S |
> > + MT8173_TOP_AXI_PROT_EN_MFG_M0 |
> > + MT8173_TOP_AXI_PROT_EN_MFG_M1 |
> > + MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT),
> > + },
> > },
> > };
> >
> > @@ -969,7 +1001,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > .pwr_sta_offs = SPM_PWR_STATUS,
> > .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
> > },
> > - .bus_prot_reg_update = true,
> > };
> >
> > static const struct scp_soc_data mt2712_data = {
> > @@ -981,7 +1012,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > .pwr_sta_offs = SPM_PWR_STATUS,
> > .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
> > },
> > - .bus_prot_reg_update = false,
> > };
> >
> > static const struct scp_soc_data mt6797_data = {
> > @@ -993,7 +1023,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > .pwr_sta_offs = SPM_PWR_STATUS_MT6797,
> > .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND_MT6797
> > },
> > - .bus_prot_reg_update = true,
> > };
> >
> > static const struct scp_soc_data mt7622_data = {
> > @@ -1003,7 +1032,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > .pwr_sta_offs = SPM_PWR_STATUS,
> > .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
> > },
> > - .bus_prot_reg_update = true,
> > };
> >
> > static const struct scp_soc_data mt7623a_data = {
> > @@ -1013,7 +1041,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > .pwr_sta_offs = SPM_PWR_STATUS,
> > .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
> > },
> > - .bus_prot_reg_update = true,
> > };
> >
> > static const struct scp_soc_data mt8173_data = {
> > @@ -1025,7 +1052,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > .pwr_sta_offs = SPM_PWR_STATUS,
> > .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
> > },
> > - .bus_prot_reg_update = true,
> > };
> >
> > /*
> > @@ -1066,8 +1092,7 @@ static int scpsys_probe(struct platform_device *pdev)
> >
> > soc = of_device_get_match_data(&pdev->dev);
> >
> > - scp = init_scp(pdev, soc->domains, soc->num_domains, &soc->regs,
> > - soc->bus_prot_reg_update);
> > + scp = init_scp(pdev, soc->domains, soc->num_domains, &soc->regs);
> > if (IS_ERR(scp))
> > return PTR_ERR(scp);
> >
> > diff --git a/drivers/soc/mediatek/scpsys-ext.h b/drivers/soc/mediatek/scpsys-ext.h
> > new file mode 100644
> > index 0000000..458b2c5
> > --- /dev/null
> > +++ b/drivers/soc/mediatek/scpsys-ext.h
> > @@ -0,0 +1,67 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +#ifndef __SOC_MEDIATEK_SCPSYS_EXT_H
> > +#define __SOC_MEDIATEK_SCPSYS_EXT_H
> > +
> > +#define MAX_STEPS 4
> > +
> > +#define _BUS_PROT(_type, _set_ofs, _clr_ofs, \
> > + _en_ofs, _sta_ofs, _mask, _ignore_clr_ack) { \
> > + .type = _type, \
> > + .set_ofs = _set_ofs, \
> > + .clr_ofs = _clr_ofs, \
> > + .en_ofs = _en_ofs, \
> > + .sta_ofs = _sta_ofs, \
> > + .mask = _mask, \
> > + .ignore_clr_ack = _ignore_clr_ack, \
> > + }
> > +
> > +#define BUS_PROT(_type, _set_ofs, _clr_ofs, \
> > + _en_ofs, _sta_ofs, _mask) \
> > + _BUS_PROT(_type, _set_ofs, _clr_ofs, \
> > + _en_ofs, _sta_ofs, _mask, false)
> > +
> > +#define BUS_PROT_IGN(_type, _set_ofs, _clr_ofs, \
> > + _en_ofs, _sta_ofs, _mask) \
> > + _BUS_PROT(_type, _set_ofs, _clr_ofs, \
> > + _en_ofs, _sta_ofs, _mask, true)
> > +
> > +#define MT2701_TOP_AXI_PROT_EN_MM_M0 BIT(1)
> > +#define MT2701_TOP_AXI_PROT_EN_CONN_M BIT(2)
> > +#define MT2701_TOP_AXI_PROT_EN_CONN_S BIT(8)
> > +
> > +#define MT7622_TOP_AXI_PROT_EN_ETHSYS (BIT(3) | BIT(17))
> > +#define MT7622_TOP_AXI_PROT_EN_HIF0 (BIT(24) | BIT(25))
> > +#define MT7622_TOP_AXI_PROT_EN_HIF1 (BIT(26) | BIT(27) | \
> > + BIT(28))
> > +#define MT7622_TOP_AXI_PROT_EN_WB (BIT(2) | BIT(6) | \
> > + BIT(7) | BIT(8))
> > +
> > +#define MT8173_TOP_AXI_PROT_EN_MM_M0 BIT(1)
> > +#define MT8173_TOP_AXI_PROT_EN_MM_M1 BIT(2)
> > +#define MT8173_TOP_AXI_PROT_EN_MFG_S BIT(14)
> > +#define MT8173_TOP_AXI_PROT_EN_MFG_M0 BIT(21)
> > +#define MT8173_TOP_AXI_PROT_EN_MFG_M1 BIT(22)
> > +#define MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT BIT(23)
> > +
> > +enum regmap_type {
> > + INVALID_TYPE = 0,
> > + IFR_TYPE,
> > + SMI_TYPE,
> > +};
> > +
> > +struct bus_prot {
> > + enum regmap_type type;
> > + u32 set_ofs;
> > + u32 clr_ofs;
>
> Please try to keep variable names consistent. You change for example set_ofs to
> reg_set. That makes the code more difficult to read and understand.
>
OK, I'll keep those names consistent.
> > + u32 en_ofs;
> > + u32 sta_ofs;
> > + u32 mask;
> > + bool ignore_clr_ack;
> > +};
> > +
> > +int mtk_scpsys_ext_set_bus_protection(const struct bus_prot *bp_table,
> > + struct regmap *infracfg, struct regmap *smi_common);
> > +int mtk_scpsys_ext_clear_bus_protection(const struct bus_prot *bp_table,
> > + struct regmap *infracfg, struct regmap *smi_common);
> > +
> > +#endif /* __SOC_MEDIATEK_SCPSYS_EXT_H */
> >
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v11 07/10] soc: mediatek: Add extra sram control
2020-02-11 17:04 ` Matthias Brugger
@ 2020-02-12 2:56 ` Weiyi Lu
0 siblings, 0 replies; 33+ messages in thread
From: Weiyi Lu @ 2020-02-12 2:56 UTC (permalink / raw)
To: Matthias Brugger
Cc: Nicolas Boichat, Rob Herring, Sascha Hauer, James Liao,
srv_heupstream, linux-kernel, Fan Chen, linux-mediatek,
linux-arm-kernel
On Tue, 2020-02-11 at 18:04 +0100, Matthias Brugger wrote:
>
> On 20/12/2019 04:46, Weiyi Lu wrote:
> > For some power domains like vpu_core on MT8183 whose sram need to
> > do clock and internal isolation while power on/off sram.
> > We add a flag "sram_iso_ctrl" in scp_domain_data to judge if we
> > need to do the extra sram isolation control or not.
> >
> > Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> > Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
> > ---
> > drivers/soc/mediatek/mtk-scpsys.c | 24 ++++++++++++++++++++++--
> > 1 file changed, 22 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
> > index 32be4b3..1972726 100644
> > --- a/drivers/soc/mediatek/mtk-scpsys.c
> > +++ b/drivers/soc/mediatek/mtk-scpsys.c
> > @@ -56,6 +56,8 @@
> > #define PWR_ON_BIT BIT(2)
> > #define PWR_ON_2ND_BIT BIT(3)
> > #define PWR_CLK_DIS_BIT BIT(4)
> > +#define PWR_SRAM_CLKISO_BIT BIT(5)
> > +#define PWR_SRAM_ISOINT_B_BIT BIT(6)
> >
> > #define PWR_STATUS_CONN BIT(1)
> > #define PWR_STATUS_DISP BIT(3)
> > @@ -86,6 +88,8 @@
> > * @name: The domain name.
> > * @sta_mask: The mask for power on/off status bit.
> > * @ctl_offs: The offset for main power control register.
> > + * @sram_iso_ctrl: The flag to judge if the power domain need to do
> > + * the extra sram isolation control.
> > * @sram_pdn_bits: The mask for sram power control bits.
> > * @sram_pdn_ack_bits: The mask for sram power control acked bits.
> > * @basic_clk_name: The basic clocks required by this power domain.
> > @@ -98,6 +102,7 @@ struct scp_domain_data {
> > const char *name;
> > u32 sta_mask;
> > int ctl_offs;
> > + bool sram_iso_ctrl;
>
> Why don't we put that into the caps variable? We have plenty of space left there
> and if needed we can bump up its value from u8 to u32.
>
Thanks for reminding, I'll put into caps in next version.
> > u32 sram_pdn_bits;
> > u32 sram_pdn_ack_bits;
> > const char *basic_clk_name[MAX_CLKS];
> > @@ -233,6 +238,14 @@ static int scpsys_sram_enable(struct scp_domain *scpd, void __iomem *ctl_addr)
> > return ret;
> > }
> >
> > + if (scpd->data->sram_iso_ctrl) {
> > + val = readl(ctl_addr) | PWR_SRAM_ISOINT_B_BIT;
> > + writel(val, ctl_addr);
> > + udelay(1);
> > + val &= ~PWR_SRAM_CLKISO_BIT;
> > + writel(val, ctl_addr);
> > + }
> > +
> > return 0;
> > }
> >
> > @@ -242,8 +255,15 @@ static int scpsys_sram_disable(struct scp_domain *scpd, void __iomem *ctl_addr)
> > u32 pdn_ack = scpd->data->sram_pdn_ack_bits;
> > int tmp;
> >
> > - val = readl(ctl_addr);
> > - val |= scpd->data->sram_pdn_bits;
> > + if (scpd->data->sram_iso_ctrl) {
> > + val = readl(ctl_addr) | PWR_SRAM_CLKISO_BIT;
> > + writel(val, ctl_addr);
> > + val &= ~PWR_SRAM_ISOINT_B_BIT;
> > + writel(val, ctl_addr);
> > + udelay(1);
>
> Why do we need to wait here?
>
It's the restriction of sram isolation for both enable and disable stage
and we've confirmed 1us is safe.
> > + }
> > +
> > + val = readl(ctl_addr) | scpd->data->sram_pdn_bits;
> > writel(val, ctl_addr);
> >
> > /* Either wait until SRAM_PDN_ACK all 1 or 0 */
> >
>
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v11 04/10] soc: mediatek: Add multiple step bus protection control
2020-02-12 2:55 ` Weiyi Lu
@ 2020-02-12 9:23 ` Matthias Brugger
2020-02-13 2:15 ` Weiyi Lu
0 siblings, 1 reply; 33+ messages in thread
From: Matthias Brugger @ 2020-02-12 9:23 UTC (permalink / raw)
To: Weiyi Lu
Cc: Nicolas Boichat, Rob Herring, Sascha Hauer, James Liao, Fan Chen,
linux-arm-kernel, linux-kernel, linux-mediatek, srv_heupstream
On 12/02/2020 03:55, Weiyi Lu wrote:
> On Tue, 2020-02-11 at 18:49 +0100, Matthias Brugger wrote:
>>
>> On 20/12/2019 04:45, Weiyi Lu wrote:
>>> Both MT8183 & MT6765 have more control steps of bus protection
>>> than previous project. And there add more bus protection registers
>>> reside at infracfg & smi-common. Also add new APIs for multiple
>>> step bus protection control with more customized arguments.
>>> And then use bp_table for bus protection of all compatibles,
>>> instead of mixing bus_prot_mask and bus_prot_reg_update.
>>>
>>> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
>>> ---
>>> drivers/soc/mediatek/Makefile | 2 +-
>>> drivers/soc/mediatek/mtk-scpsys-ext.c | 101 +++++++++++++++++++++++++++++
>>> drivers/soc/mediatek/mtk-scpsys.c | 117 +++++++++++++++++++++-------------
>>> drivers/soc/mediatek/scpsys-ext.h | 67 +++++++++++++++++++
>>> 4 files changed, 240 insertions(+), 47 deletions(-)
>>> create mode 100644 drivers/soc/mediatek/mtk-scpsys-ext.c
>>> create mode 100644 drivers/soc/mediatek/scpsys-ext.h
>>>
>>> diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
>>> index b017330..b442be9 100644
>>> --- a/drivers/soc/mediatek/Makefile
>>> +++ b/drivers/soc/mediatek/Makefile
>>> @@ -1,5 +1,5 @@
>>> # SPDX-License-Identifier: GPL-2.0-only
>>> obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o
>>> -obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
>>> +obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o mtk-scpsys-ext.o
>>
>> It seems that we would need another patch which get's rid of the mtk-infracfg
>> first and then add stuff like the possibility to have different steps.
>>
>
> Actually I have a PATCH 05/11 to remove the mtk-infracfg.
> In this patch, I have some changes, like calling
> mtk_scpsys_ext_set_bus_protection(...) instead of
> mtk_infracfg_set_bus_protection(...) in scpsys_bus_protect_enable(...)
> and replacing bus_prot_mask by bp_table.
> I thought I should introduce the new method first and remove useless one
> later. What do you think?
Yes, but first patch would be a step to get rid of mtk-infracfg and a second
patch add bp_table and the like.
>
>>> obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
>>> obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
>>> diff --git a/drivers/soc/mediatek/mtk-scpsys-ext.c b/drivers/soc/mediatek/mtk-scpsys-ext.c
>>> new file mode 100644
>>> index 0000000..df402ac
>>> --- /dev/null
>>> +++ b/drivers/soc/mediatek/mtk-scpsys-ext.c
>>
>> I'm not quite sure why we should put this into a new file. I suppose the
>> rational behind it is the fact that we access other blocks through regmap.
>>
>
> Yes, those operation are accross infracfg and smi-common so we put these
> into new files.
Are you exepct other drivers to use this functions? If not I will have to think
again, but I don't see any reason to put it into a new file.
>
>>> @@ -0,0 +1,101 @@
>>> +// SPDX-License-Identifier: GPL-2.0
>>> +/*
>>> + * Copyright (c) 2018 MediaTek Inc.
>>> + * Author: Owen Chen <Owen.Chen@mediatek.com>
>>> + */
>>> +#include <linux/ktime.h>
>>> +#include <linux/mfd/syscon.h>
>>> +#include <linux/of_device.h>
>>> +#include <linux/regmap.h>
>>> +#include "scpsys-ext.h"
>>> +
>>> +#define MTK_POLL_DELAY_US 10
>>> +#define MTK_POLL_TIMEOUT USEC_PER_SEC
>>> +
>>> +static int set_bus_protection(struct regmap *map, u32 mask,
>>> + u32 reg_set, u32 reg_sta, u32 reg_en)
>>> +{
>>> + u32 val;
>>> +
>>> + if (reg_set)
>>> + regmap_write(map, reg_set, mask);
>>> + else
>>> + regmap_update_bits(map, reg_en, mask, mask);
>>> +
>>> + return regmap_read_poll_timeout(map, reg_sta,
>>> + val, (val & mask) == mask,
>>> + MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
>>> +}
>>> +
>>> +static int clear_bus_protection(struct regmap *map, u32 mask,
>>> + u32 reg_clr, u32 reg_sta, u32 reg_en, bool ignore_ack)
>>> +{
>>> + u32 val;
>>> +
>>> + if (reg_clr)
>>> + regmap_write(map, reg_clr, mask);
>>> + else
>>> + regmap_update_bits(map, reg_en, mask, 0);
>>> +
>>> + if (ignore_ack)
>>> + return 0;
>>> +
>>> + return regmap_read_poll_timeout(map, reg_sta,
>>> + val, !(val & mask),
>>> + MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
>>> +}
>>> +
>>> +int mtk_scpsys_ext_set_bus_protection(const struct bus_prot *bp_table,
>>> + struct regmap *infracfg, struct regmap *smi_common)
>>> +{
>>> + int i;
>>> +
>>> + for (i = 0; i < MAX_STEPS; i++) {
>>
>> struct bus_prot bp_table = bp_table[i];
>>
>
> OK, got it.
>
>>> + struct regmap *map = NULL;
>>> + int ret;
>>> +
>>> + if (bp_table[i].type == INVALID_TYPE)
>>> + break;
>>> + else if (bp_table[i].type == IFR_TYPE)
>>> + map = infracfg;
>>> + else if (bp_table[i].type == SMI_TYPE)
>>> + map = smi_common;
>>
>> if (bp_table.type == IFR_TYPE)
>> map = infracfg;
>> else if (bp_table.type == SMI_TYPE)
>> map = smi_common;
>> else
>> break;
>>
>
> OK, got it.
>
>>> +
>>> + ret = set_bus_protection(map,
>>> + bp_table[i].mask, bp_table[i].set_ofs,
>>> + bp_table[i].sta_ofs, bp_table[i].en_ofs);
>>
>> passing map and bp_table here makes code much more readable. I always end-up
>> counting the variables when the names in the callee changes.
>>
>
> OK, I'll fix it.
>
>>> +
>>> + if (ret)
>>> + return ret;
>>> + }
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +int mtk_scpsys_ext_clear_bus_protection(const struct bus_prot *bp_table,
>>> + struct regmap *infracfg, struct regmap *smi_common)
>>> +{
>>> + int i;
>>> +
>>> + for (i = MAX_STEPS - 1; i >= 0; i--) {
>>> + struct regmap *map = NULL;
>>> + int ret;
>>> +
>>> + if (bp_table[i].type == INVALID_TYPE)
>>> + continue;
>>> + else if (bp_table[i].type == IFR_TYPE)
>>> + map = infracfg;
>>> + else if (bp_table[i].type == SMI_TYPE)
>>> + map = smi_common;
>>> +
>>> + ret = clear_bus_protection(map,
>>> + bp_table[i].mask, bp_table[i].clr_ofs,
>>> + bp_table[i].sta_ofs, bp_table[i].en_ofs,
>>> + bp_table[i].ignore_clr_ack);
>>> +
>>
>> same here.
>>
>
> Got it.
>
>>> + if (ret)
>>> + return ret;
>>> + }
>>> +
>>> + return 0;
>>> +}
>>> diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
>>> index db35a28..763ca58 100644
>>> --- a/drivers/soc/mediatek/mtk-scpsys.c
>>> +++ b/drivers/soc/mediatek/mtk-scpsys.c
>>> @@ -11,7 +11,7 @@
>>> #include <linux/platform_device.h>
>>> #include <linux/pm_domain.h>
>>> #include <linux/regulator/consumer.h>
>>> -#include <linux/soc/mediatek/infracfg.h>
>>> +#include "scpsys-ext.h"
>>>
>>> #include <dt-bindings/power/mt2701-power.h>
>>> #include <dt-bindings/power/mt2712-power.h>
>>> @@ -87,9 +87,9 @@
>>> * @ctl_offs: The offset for main power control register.
>>> * @sram_pdn_bits: The mask for sram power control bits.
>>> * @sram_pdn_ack_bits: The mask for sram power control acked bits.
>>> - * @bus_prot_mask: The mask for single step bus protection.
>>> * @basic_clk_name: The basic clocks required by this power domain.
>>> * @caps: The flag for active wake-up action.
>>> + * @bp_table: The mask table for multiple step bus protection.
>>> */
>>> struct scp_domain_data {
>>> const char *name;
>>> @@ -97,9 +97,9 @@ struct scp_domain_data {
>>> int ctl_offs;
>>> u32 sram_pdn_bits;
>>> u32 sram_pdn_ack_bits;
>>> - u32 bus_prot_mask;
>>> const char *basic_clk_name[MAX_CLKS];
>>> u8 caps;
>>> + struct bus_prot bp_table[MAX_STEPS];
>>> };
>>>
>>> struct scp;
>>> @@ -123,8 +123,8 @@ struct scp {
>>> struct device *dev;
>>> void __iomem *base;
>>> struct regmap *infracfg;
>>> + struct regmap *smi_common;
>>> struct scp_ctrl_reg ctrl_reg;
>>> - bool bus_prot_reg_update;
>>> };
>>>
>>> struct scp_subdomain {
>>> @@ -138,7 +138,6 @@ struct scp_soc_data {
>>> const struct scp_subdomain *subdomains;
>>> int num_subdomains;
>>> const struct scp_ctrl_reg regs;
>>> - bool bus_prot_reg_update;
>>> };
>>>
>>> static int scpsys_domain_is_on(struct scp_domain *scpd)
>>> @@ -252,24 +251,16 @@ static int scpsys_bus_protect_enable(struct scp_domain *scpd)
>>> {
>>> struct scp *scp = scpd->scp;
>>>
>>> - if (!scpd->data->bus_prot_mask)
>>> - return 0;
>>> -
>>> - return mtk_infracfg_set_bus_protection(scp->infracfg,
>>> - scpd->data->bus_prot_mask,
>>> - scp->bus_prot_reg_update);
>>> + return mtk_scpsys_ext_set_bus_protection(scpd->data->bp_table,
>>> + scp->infracfg, scp->smi_common);
>>
>> Now that's just a wrapper which does add nothing but another indirection. We can
>> call mtk_scpsys_ext_set_bus_protection() directly (also I don't like the name,
>> actually why don't mtk_scpsys_set_bus_protection()?)
>>
>
> You're right. I'll called mtk_scpsys_ext_set_bus_protection() directly.
>
>>> }
>>>
>>> static int scpsys_bus_protect_disable(struct scp_domain *scpd)
>>> {
>>> struct scp *scp = scpd->scp;
>>>
>>> - if (!scpd->data->bus_prot_mask)
>>> - return 0;
>>> -
>>> - return mtk_infracfg_clear_bus_protection(scp->infracfg,
>>> - scpd->data->bus_prot_mask,
>>> - scp->bus_prot_reg_update);
>>> + return mtk_scpsys_ext_clear_bus_protection(scpd->data->bp_table,
>>> + scp->infracfg, scp->smi_common);
>>> }
>>>
>>> static int scpsys_power_on(struct generic_pm_domain *genpd)
>>> @@ -404,8 +395,7 @@ static int init_basic_clks(struct platform_device *pdev, struct clk **clk,
>>>
>>> static struct scp *init_scp(struct platform_device *pdev,
>>> const struct scp_domain_data *scp_domain_data, int num,
>>> - const struct scp_ctrl_reg *scp_ctrl_reg,
>>> - bool bus_prot_reg_update)
>>> + const struct scp_ctrl_reg *scp_ctrl_reg)
>>> {
>>> struct genpd_onecell_data *pd_data;
>>> struct resource *res;
>>> @@ -419,8 +409,6 @@ static struct scp *init_scp(struct platform_device *pdev,
>>> scp->ctrl_reg.pwr_sta_offs = scp_ctrl_reg->pwr_sta_offs;
>>> scp->ctrl_reg.pwr_sta2nd_offs = scp_ctrl_reg->pwr_sta2nd_offs;
>>>
>>> - scp->bus_prot_reg_update = bus_prot_reg_update;
>>> -
>>> scp->dev = &pdev->dev;
>>>
>>> res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>>> @@ -448,6 +436,17 @@ static struct scp *init_scp(struct platform_device *pdev,
>>> return ERR_CAST(scp->infracfg);
>>> }
>>>
>>> + scp->smi_common = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
>>> + "smi_comm");
>>> +
>>> + if (scp->smi_common == ERR_PTR(-ENODEV)) {
>>> + scp->smi_common = NULL;
>>> + } else if (IS_ERR(scp->smi_common)) {
>>> + dev_err(&pdev->dev, "Cannot find smi_common controller: %ld\n",
>>> + PTR_ERR(scp->smi_common));
>>> + return ERR_CAST(scp->smi_common);
>>> + }
>>> +
>>> for (i = 0; i < num; i++) {
>>> struct scp_domain *scpd = &scp->domains[i];
>>> const struct scp_domain_data *data = &scp_domain_data[i];
>>> @@ -530,8 +529,11 @@ static void mtk_register_power_domains(struct platform_device *pdev,
>>> .name = "conn",
>>> .sta_mask = PWR_STATUS_CONN,
>>> .ctl_offs = SPM_CONN_PWR_CON,
>>> - .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_CONN_M |
>>> - MT2701_TOP_AXI_PROT_EN_CONN_S,
>>> + .bp_table = {
>>> + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
>>> + MT2701_TOP_AXI_PROT_EN_CONN_M |
>>> + MT2701_TOP_AXI_PROT_EN_CONN_S),
>>> + },
>>> .caps = MTK_SCPD_ACTIVE_WAKEUP,
>>> },
>>> [MT2701_POWER_DOMAIN_DISP] = {
>>> @@ -540,7 +542,10 @@ static void mtk_register_power_domains(struct platform_device *pdev,
>>> .ctl_offs = SPM_DIS_PWR_CON,
>>> .sram_pdn_bits = GENMASK(11, 8),
>>> .basic_clk_name = {"mm"},
>>> - .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_MM_M0,
>>> + .bp_table = {
>>> + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
>>> + MT2701_TOP_AXI_PROT_EN_MM_M0),
>>> + },
>>> .caps = MTK_SCPD_ACTIVE_WAKEUP,
>>> },
>>> [MT2701_POWER_DOMAIN_MFG] = {
>>> @@ -675,7 +680,10 @@ static void mtk_register_power_domains(struct platform_device *pdev,
>>> .sram_pdn_bits = GENMASK(8, 8),
>>> .sram_pdn_ack_bits = GENMASK(16, 16),
>>> .basic_clk_name = {"mfg"},
>>> - .bus_prot_mask = BIT(14) | BIT(21) | BIT(23),
>>> + .bp_table = {
>>> + BUS_PROT(IFR_TYPE, 0x260, 0x264, 0x220, 0x228,
>>> + BIT(14) | BIT(21) | BIT(23)),
>>> + },
>>> .caps = MTK_SCPD_ACTIVE_WAKEUP,
>>> },
>>> [MT2712_POWER_DOMAIN_MFG_SC1] = {
>>> @@ -747,7 +755,10 @@ static void mtk_register_power_domains(struct platform_device *pdev,
>>> .sram_pdn_bits = GENMASK(8, 8),
>>> .sram_pdn_ack_bits = GENMASK(12, 12),
>>> .basic_clk_name = {"mm"},
>>> - .bus_prot_mask = (BIT(1) | BIT(2)),
>>> + .bp_table = {
>>> + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
>>> + BIT(1) | BIT(2)),
>>> + },
>>> },
>>> [MT6797_POWER_DOMAIN_AUDIO] = {
>>> .name = "audio",
>>> @@ -794,7 +805,10 @@ static void mtk_register_power_domains(struct platform_device *pdev,
>>> .ctl_offs = SPM_ETHSYS_PWR_CON,
>>> .sram_pdn_bits = GENMASK(11, 8),
>>> .sram_pdn_ack_bits = GENMASK(15, 12),
>>> - .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_ETHSYS,
>>> + .bp_table = {
>>> + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
>>> + MT7622_TOP_AXI_PROT_EN_ETHSYS),
>>> + },
>>> .caps = MTK_SCPD_ACTIVE_WAKEUP,
>>> },
>>> [MT7622_POWER_DOMAIN_HIF0] = {
>>> @@ -804,7 +818,10 @@ static void mtk_register_power_domains(struct platform_device *pdev,
>>> .sram_pdn_bits = GENMASK(11, 8),
>>> .sram_pdn_ack_bits = GENMASK(15, 12),
>>> .basic_clk_name = {"hif_sel"},
>>> - .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_HIF0,
>>> + .bp_table = {
>>> + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
>>> + MT7622_TOP_AXI_PROT_EN_HIF0),
>>> + },
>>> .caps = MTK_SCPD_ACTIVE_WAKEUP,
>>> },
>>> [MT7622_POWER_DOMAIN_HIF1] = {
>>> @@ -814,7 +831,10 @@ static void mtk_register_power_domains(struct platform_device *pdev,
>>> .sram_pdn_bits = GENMASK(11, 8),
>>> .sram_pdn_ack_bits = GENMASK(15, 12),
>>> .basic_clk_name = {"hif_sel"},
>>> - .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_HIF1,
>>> + .bp_table = {
>>> + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
>>> + MT7622_TOP_AXI_PROT_EN_HIF1),
>>> + },
>>> .caps = MTK_SCPD_ACTIVE_WAKEUP,
>>> },
>>> [MT7622_POWER_DOMAIN_WB] = {
>>> @@ -823,7 +843,10 @@ static void mtk_register_power_domains(struct platform_device *pdev,
>>> .ctl_offs = SPM_WB_PWR_CON,
>>> .sram_pdn_bits = 0,
>>> .sram_pdn_ack_bits = 0,
>>> - .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_WB,
>>> + .bp_table = {
>>> + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
>>> + MT7622_TOP_AXI_PROT_EN_WB),
>>> + },
>>> .caps = MTK_SCPD_ACTIVE_WAKEUP | MTK_SCPD_FWAIT_SRAM,
>>> },
>>> };
>>> @@ -837,8 +860,11 @@ static void mtk_register_power_domains(struct platform_device *pdev,
>>> .name = "conn",
>>> .sta_mask = PWR_STATUS_CONN,
>>> .ctl_offs = SPM_CONN_PWR_CON,
>>> - .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_CONN_M |
>>> - MT2701_TOP_AXI_PROT_EN_CONN_S,
>>> + .bp_table = {
>>> + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
>>> + MT2701_TOP_AXI_PROT_EN_CONN_M |
>>> + MT2701_TOP_AXI_PROT_EN_CONN_S),
>>> + },
>>> .caps = MTK_SCPD_ACTIVE_WAKEUP,
>>> },
>>> [MT7623A_POWER_DOMAIN_ETH] = {
>>> @@ -903,8 +929,11 @@ static void mtk_register_power_domains(struct platform_device *pdev,
>>> .sram_pdn_bits = GENMASK(11, 8),
>>> .sram_pdn_ack_bits = GENMASK(12, 12),
>>> .basic_clk_name = {"mm"},
>>> - .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 |
>>> - MT8173_TOP_AXI_PROT_EN_MM_M1,
>>> + .bp_table = {
>>> + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
>>> + MT8173_TOP_AXI_PROT_EN_MM_M0 |
>>> + MT8173_TOP_AXI_PROT_EN_MM_M1),
>>> + },
>>> },
>>> [MT8173_POWER_DOMAIN_VENC_LT] = {
>>> .name = "venc_lt",
>>> @@ -950,10 +979,13 @@ static void mtk_register_power_domains(struct platform_device *pdev,
>>> .ctl_offs = SPM_MFG_PWR_CON,
>>> .sram_pdn_bits = GENMASK(13, 8),
>>> .sram_pdn_ack_bits = GENMASK(21, 16),
>>> - .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MFG_S |
>>> - MT8173_TOP_AXI_PROT_EN_MFG_M0 |
>>> - MT8173_TOP_AXI_PROT_EN_MFG_M1 |
>>> - MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT,
>>> + .bp_table = {
>>> + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
>>> + MT8173_TOP_AXI_PROT_EN_MFG_S |
>>> + MT8173_TOP_AXI_PROT_EN_MFG_M0 |
>>> + MT8173_TOP_AXI_PROT_EN_MFG_M1 |
>>> + MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT),
>>> + },
>>> },
>>> };
>>>
>>> @@ -969,7 +1001,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
>>> .pwr_sta_offs = SPM_PWR_STATUS,
>>> .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
>>> },
>>> - .bus_prot_reg_update = true,
>>> };
>>>
>>> static const struct scp_soc_data mt2712_data = {
>>> @@ -981,7 +1012,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
>>> .pwr_sta_offs = SPM_PWR_STATUS,
>>> .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
>>> },
>>> - .bus_prot_reg_update = false,
>>> };
>>>
>>> static const struct scp_soc_data mt6797_data = {
>>> @@ -993,7 +1023,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
>>> .pwr_sta_offs = SPM_PWR_STATUS_MT6797,
>>> .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND_MT6797
>>> },
>>> - .bus_prot_reg_update = true,
>>> };
>>>
>>> static const struct scp_soc_data mt7622_data = {
>>> @@ -1003,7 +1032,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
>>> .pwr_sta_offs = SPM_PWR_STATUS,
>>> .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
>>> },
>>> - .bus_prot_reg_update = true,
>>> };
>>>
>>> static const struct scp_soc_data mt7623a_data = {
>>> @@ -1013,7 +1041,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
>>> .pwr_sta_offs = SPM_PWR_STATUS,
>>> .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
>>> },
>>> - .bus_prot_reg_update = true,
>>> };
>>>
>>> static const struct scp_soc_data mt8173_data = {
>>> @@ -1025,7 +1052,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
>>> .pwr_sta_offs = SPM_PWR_STATUS,
>>> .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
>>> },
>>> - .bus_prot_reg_update = true,
>>> };
>>>
>>> /*
>>> @@ -1066,8 +1092,7 @@ static int scpsys_probe(struct platform_device *pdev)
>>>
>>> soc = of_device_get_match_data(&pdev->dev);
>>>
>>> - scp = init_scp(pdev, soc->domains, soc->num_domains, &soc->regs,
>>> - soc->bus_prot_reg_update);
>>> + scp = init_scp(pdev, soc->domains, soc->num_domains, &soc->regs);
>>> if (IS_ERR(scp))
>>> return PTR_ERR(scp);
>>>
>>> diff --git a/drivers/soc/mediatek/scpsys-ext.h b/drivers/soc/mediatek/scpsys-ext.h
>>> new file mode 100644
>>> index 0000000..458b2c5
>>> --- /dev/null
>>> +++ b/drivers/soc/mediatek/scpsys-ext.h
>>> @@ -0,0 +1,67 @@
>>> +/* SPDX-License-Identifier: GPL-2.0 */
>>> +#ifndef __SOC_MEDIATEK_SCPSYS_EXT_H
>>> +#define __SOC_MEDIATEK_SCPSYS_EXT_H
>>> +
>>> +#define MAX_STEPS 4
>>> +
>>> +#define _BUS_PROT(_type, _set_ofs, _clr_ofs, \
>>> + _en_ofs, _sta_ofs, _mask, _ignore_clr_ack) { \
>>> + .type = _type, \
>>> + .set_ofs = _set_ofs, \
>>> + .clr_ofs = _clr_ofs, \
>>> + .en_ofs = _en_ofs, \
>>> + .sta_ofs = _sta_ofs, \
>>> + .mask = _mask, \
>>> + .ignore_clr_ack = _ignore_clr_ack, \
>>> + }
>>> +
>>> +#define BUS_PROT(_type, _set_ofs, _clr_ofs, \
>>> + _en_ofs, _sta_ofs, _mask) \
>>> + _BUS_PROT(_type, _set_ofs, _clr_ofs, \
>>> + _en_ofs, _sta_ofs, _mask, false)
>>> +
>>> +#define BUS_PROT_IGN(_type, _set_ofs, _clr_ofs, \
>>> + _en_ofs, _sta_ofs, _mask) \
>>> + _BUS_PROT(_type, _set_ofs, _clr_ofs, \
>>> + _en_ofs, _sta_ofs, _mask, true)
>>> +
>>> +#define MT2701_TOP_AXI_PROT_EN_MM_M0 BIT(1)
>>> +#define MT2701_TOP_AXI_PROT_EN_CONN_M BIT(2)
>>> +#define MT2701_TOP_AXI_PROT_EN_CONN_S BIT(8)
>>> +
>>> +#define MT7622_TOP_AXI_PROT_EN_ETHSYS (BIT(3) | BIT(17))
>>> +#define MT7622_TOP_AXI_PROT_EN_HIF0 (BIT(24) | BIT(25))
>>> +#define MT7622_TOP_AXI_PROT_EN_HIF1 (BIT(26) | BIT(27) | \
>>> + BIT(28))
>>> +#define MT7622_TOP_AXI_PROT_EN_WB (BIT(2) | BIT(6) | \
>>> + BIT(7) | BIT(8))
>>> +
>>> +#define MT8173_TOP_AXI_PROT_EN_MM_M0 BIT(1)
>>> +#define MT8173_TOP_AXI_PROT_EN_MM_M1 BIT(2)
>>> +#define MT8173_TOP_AXI_PROT_EN_MFG_S BIT(14)
>>> +#define MT8173_TOP_AXI_PROT_EN_MFG_M0 BIT(21)
>>> +#define MT8173_TOP_AXI_PROT_EN_MFG_M1 BIT(22)
>>> +#define MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT BIT(23)
>>> +
>>> +enum regmap_type {
>>> + INVALID_TYPE = 0,
>>> + IFR_TYPE,
>>> + SMI_TYPE,
>>> +};
>>> +
>>> +struct bus_prot {
>>> + enum regmap_type type;
>>> + u32 set_ofs;
>>> + u32 clr_ofs;
>>
>> Please try to keep variable names consistent. You change for example set_ofs to
>> reg_set. That makes the code more difficult to read and understand.
>>
>
> OK, I'll keep those names consistent.
>
>>> + u32 en_ofs;
>>> + u32 sta_ofs;
>>> + u32 mask;
>>> + bool ignore_clr_ack;
>>> +};
>>> +
>>> +int mtk_scpsys_ext_set_bus_protection(const struct bus_prot *bp_table,
>>> + struct regmap *infracfg, struct regmap *smi_common);
>>> +int mtk_scpsys_ext_clear_bus_protection(const struct bus_prot *bp_table,
>>> + struct regmap *infracfg, struct regmap *smi_common);
>>> +
>>> +#endif /* __SOC_MEDIATEK_SCPSYS_EXT_H */
>>>
>
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v11 06/10] soc: mediatek: Add subsys clock control for bus protection
2020-02-12 2:55 ` Weiyi Lu
@ 2020-02-12 11:02 ` Matthias Brugger
2020-02-13 2:46 ` Weiyi Lu
0 siblings, 1 reply; 33+ messages in thread
From: Matthias Brugger @ 2020-02-12 11:02 UTC (permalink / raw)
To: Weiyi Lu
Cc: Nicolas Boichat, Rob Herring, Sascha Hauer, James Liao, Fan Chen,
linux-arm-kernel, linux-kernel, linux-mediatek, srv_heupstream
On 12/02/2020 03:55, Weiyi Lu wrote:
> On Tue, 2020-02-11 at 18:54 +0100, Matthias Brugger wrote:
>>
>> On 20/12/2019 04:46, Weiyi Lu wrote:
>>> Add subsys CG control flow before/after the bus protect control
>>> due to bus protection need SMI bus relative CGs enabled to feedback
>>> its ack.
>>>
>>
>> Sorry, I don't understand the commit message. Can you please rephrase and
>> explain better what this change is for.
>>
>
> OK! I'll reword it.
>
>>> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
>>> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
>>> ---
>>> drivers/soc/mediatek/mtk-scpsys.c | 72 +++++++++++++++++++++++++++++++++++++--
>>> 1 file changed, 70 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
>>> index 763ca58..32be4b3 100644
>>> --- a/drivers/soc/mediatek/mtk-scpsys.c
>>> +++ b/drivers/soc/mediatek/mtk-scpsys.c
>>> @@ -79,6 +79,7 @@
>>> #define PWR_STATUS_WB BIT(27) /* MT7622 */
>>>
>>> #define MAX_CLKS 3
>>> +#define MAX_SUBSYS_CLKS 10
>>>
>>> /**
>>> * struct scp_domain_data - scp domain data for power on/off flow
>>> @@ -88,6 +89,8 @@
>>> * @sram_pdn_bits: The mask for sram power control bits.
>>> * @sram_pdn_ack_bits: The mask for sram power control acked bits.
>>> * @basic_clk_name: The basic clocks required by this power domain.
>>> + * @subsys_clk_prefix: The prefix name of the clocks need to be enabled
>>> + * before releasing bus protection.
>>> * @caps: The flag for active wake-up action.
>>> * @bp_table: The mask table for multiple step bus protection.
>>> */
>>> @@ -98,6 +101,7 @@ struct scp_domain_data {
>>> u32 sram_pdn_bits;
>>> u32 sram_pdn_ack_bits;
>>> const char *basic_clk_name[MAX_CLKS];
>>> + const char *subsys_clk_prefix;
>>> u8 caps;
>>> struct bus_prot bp_table[MAX_STEPS];
>>> };
>>> @@ -108,6 +112,7 @@ struct scp_domain {
>>> struct generic_pm_domain genpd;
>>> struct scp *scp;
>>> struct clk *clk[MAX_CLKS];
>>> + struct clk *subsys_clk[MAX_SUBSYS_CLKS];
>>> const struct scp_domain_data *data;
>>> struct regulator *supply;
>>> };
>>> @@ -301,16 +306,22 @@ static int scpsys_power_on(struct generic_pm_domain *genpd)
>>> val |= PWR_RST_B_BIT;
>>> writel(val, ctl_addr);
>>>
>>> - ret = scpsys_sram_enable(scpd, ctl_addr);
>>> + ret = scpsys_clk_enable(scpd->subsys_clk, MAX_SUBSYS_CLKS);
>>
>> Why can't we enable the subsystem clocks together with the rest just after
>> enabeling the regulator?
>>
>
> Subsys CG could only be enabled when its own power domain is already
> turned ON, and vice versa.
> In the dt-binding doc we mentioned there would have two groups of
> clocks.
> e.g.,
> BASIC clocks need to be enabled before enabling the corresponding power
> domain.
> SUBSYS clocks need to be enabled before releasing the bus protection.
>
Do I understand correctly that we could enable/disable all clocks in the same
place as long as we make sure that the the basic clocks are turned on before we
turn on the subsys clocks, correct?
So why do we need to implement this logic in the power-controller driver?
Shouldn't that be part of the common clock driver?
Regards,
Matthias
>>> if (ret < 0)
>>> goto err_pwr_ack;
>>>
>>> + ret = scpsys_sram_enable(scpd, ctl_addr);
>>> + if (ret < 0)
>>> + goto err_sram;
>>> +
>>> ret = scpsys_bus_protect_disable(scpd);
>>> if (ret < 0)
>>> - goto err_pwr_ack;
>>> + goto err_sram;
>>>
>>> return 0;
>>>
>>> +err_sram:
>>> + scpsys_clk_disable(scpd->subsys_clk, MAX_SUBSYS_CLKS);
>>> err_pwr_ack:
>>> scpsys_clk_disable(scpd->clk, MAX_CLKS);
>>> err_clk:
>>> @@ -337,6 +348,8 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
>>> if (ret < 0)
>>> goto out;
>>>
>>> + scpsys_clk_disable(scpd->subsys_clk, MAX_SUBSYS_CLKS);
>>> +
>>
>> Same here, why can't we disable the clocks in the scpsys_clk_disable call?
>>
>>> /* subsys power off */
>>> val = readl(ctl_addr);
>>> val |= PWR_ISO_BIT;
>>> @@ -374,6 +387,48 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
>>> return ret;
>>> }
>>>
>>> +static int init_subsys_clks(struct platform_device *pdev,
>>> + const char *prefix, struct clk **clk)
>>> +{
>>> + struct device_node *node = pdev->dev.of_node;
>>> + u32 prefix_len, sub_clk_cnt = 0;
>>> + struct property *prop;
>>> + const char *clk_name;
>>> +
>>> + if (!node) {
>>> + dev_err(&pdev->dev, "Cannot find scpsys node: %ld\n",
>>> + PTR_ERR(node));
>>> + return PTR_ERR(node);
>>> + }
>>> +
>>> + prefix_len = strlen(prefix);
>>> +
>>> + of_property_for_each_string(node, "clock-names", prop, clk_name) {
>>> + if (!strncmp(clk_name, prefix, prefix_len) &&
>>> + (clk_name[prefix_len] == '-')) {
>>> + if (sub_clk_cnt >= MAX_SUBSYS_CLKS) {
>>> + dev_err(&pdev->dev,
>>> + "subsys clk out of range %d\n",
>>> + sub_clk_cnt);
>>> + return -ENOMEM;
>>
>> EINVAL maybe, ENOMEM seems wrong here.
>>
>
> OK, I'll fix with correct error.
>
>>> + }
>>> +
>>> + clk[sub_clk_cnt] = devm_clk_get(&pdev->dev,
>>> + clk_name);
>>
>> Here we get hit by the bad design of this driver in the first place. As we need
>> the subsystem-name (eg mm-0, mm-1) to group clocks to one scp_domain.
>> I think we should better try to model the domains and subdomains in DTS and add
>> their clocks to it. This way we can also get rid of the scp_subdomain which can
>> hit it's limit anytime soon when we have a chip with a sub-subdomain.
>> That will need a new driver, but as it seems the mt8183 and the mt6765 have a
>> more complex design I think it is worth it.
>>
>> That said, given that you are in v11 already I understand that your motivation
>> to start over isn't the biggest. The problem is, any new driver will have new
>> bindings and won't work with older DTS. So adding a lot of stuff on top of a not
>> really nice driver isn't something I'm very keen on. On the other hand you
>> already put a lot of work into this solution.
>>
>> My proposal, I'll try to bake up a new driver this week. If I fail to deliver,
>> it's up to you to decide if you want to go on with the approach in this series
>> or try to work on the new one.
>
>> Regards,
>> Matthias
>>
>
> Thanks for considering our request.
>
>>> +
>>> + if (IS_ERR(clk[sub_clk_cnt])) {
>>> + dev_err(&pdev->dev,
>>> + "Subsys clk get fail %ld\n",
>>> + PTR_ERR(clk[sub_clk_cnt]));
>>> + return PTR_ERR(clk[sub_clk_cnt]);
>>> + }
>>> + sub_clk_cnt++;
>>> + }
>>> + }
>>> +
>>> + return sub_clk_cnt;
>>> +}
>>> +
>>> static int init_basic_clks(struct platform_device *pdev, struct clk **clk,
>>> const char * const *name)
>>> {
>>> @@ -466,6 +521,7 @@ static struct scp *init_scp(struct platform_device *pdev,
>>> struct scp_domain *scpd = &scp->domains[i];
>>> struct generic_pm_domain *genpd = &scpd->genpd;
>>> const struct scp_domain_data *data = &scp_domain_data[i];
>>> + int clk_cnt;
>>
>> clk_cnt sounds to me like clock count, but the variable actually is only used to
>> check the return value of init_subsys_clks. Please rename it to ret or something
>> like this.
>>
>
> OK, I'll fix it.
>
>>>
>>> pd_data->domains[i] = genpd;
>>> scpd->scp = scp;
>>> @@ -476,6 +532,18 @@ static struct scp *init_scp(struct platform_device *pdev,
>>> if (ret)
>>> return ERR_PTR(ret);
>>>
>>> + if (data->subsys_clk_prefix) {
>>> + clk_cnt = init_subsys_clks(pdev,
>>> + data->subsys_clk_prefix,
>>> + scpd->subsys_clk);
>>> + if (clk_cnt < 0) {
>>> + dev_err(&pdev->dev,
>>> + "%s: subsys clk unavailable\n",
>>> + data->name);
>>> + return ERR_PTR(clk_cnt);
>>> + }
>>> + }
>>> +
>>> genpd->name = data->name;
>>> genpd->power_off = scpsys_power_off;
>>> genpd->power_on = scpsys_power_on;
>>>
>
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v11 04/10] soc: mediatek: Add multiple step bus protection control
2020-02-12 9:23 ` Matthias Brugger
@ 2020-02-13 2:15 ` Weiyi Lu
2020-02-13 11:11 ` Matthias Brugger
0 siblings, 1 reply; 33+ messages in thread
From: Weiyi Lu @ 2020-02-13 2:15 UTC (permalink / raw)
To: Matthias Brugger
Cc: Nicolas Boichat, Rob Herring, Sascha Hauer, James Liao, Fan Chen,
linux-arm-kernel, linux-kernel, linux-mediatek, srv_heupstream
On Wed, 2020-02-12 at 10:23 +0100, Matthias Brugger wrote:
>
> On 12/02/2020 03:55, Weiyi Lu wrote:
> > On Tue, 2020-02-11 at 18:49 +0100, Matthias Brugger wrote:
> >>
> >> On 20/12/2019 04:45, Weiyi Lu wrote:
> >>> Both MT8183 & MT6765 have more control steps of bus protection
> >>> than previous project. And there add more bus protection registers
> >>> reside at infracfg & smi-common. Also add new APIs for multiple
> >>> step bus protection control with more customized arguments.
> >>> And then use bp_table for bus protection of all compatibles,
> >>> instead of mixing bus_prot_mask and bus_prot_reg_update.
> >>>
> >>> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> >>> ---
> >>> drivers/soc/mediatek/Makefile | 2 +-
> >>> drivers/soc/mediatek/mtk-scpsys-ext.c | 101 +++++++++++++++++++++++++++++
> >>> drivers/soc/mediatek/mtk-scpsys.c | 117 +++++++++++++++++++++-------------
> >>> drivers/soc/mediatek/scpsys-ext.h | 67 +++++++++++++++++++
> >>> 4 files changed, 240 insertions(+), 47 deletions(-)
> >>> create mode 100644 drivers/soc/mediatek/mtk-scpsys-ext.c
> >>> create mode 100644 drivers/soc/mediatek/scpsys-ext.h
> >>>
> >>> diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
> >>> index b017330..b442be9 100644
> >>> --- a/drivers/soc/mediatek/Makefile
> >>> +++ b/drivers/soc/mediatek/Makefile
> >>> @@ -1,5 +1,5 @@
> >>> # SPDX-License-Identifier: GPL-2.0-only
> >>> obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o
> >>> -obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
> >>> +obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o mtk-scpsys-ext.o
> >>
> >> It seems that we would need another patch which get's rid of the mtk-infracfg
> >> first and then add stuff like the possibility to have different steps.
> >>
> >
> > Actually I have a PATCH 05/11 to remove the mtk-infracfg.
> > In this patch, I have some changes, like calling
> > mtk_scpsys_ext_set_bus_protection(...) instead of
> > mtk_infracfg_set_bus_protection(...) in scpsys_bus_protect_enable(...)
> > and replacing bus_prot_mask by bp_table.
> > I thought I should introduce the new method first and remove useless one
> > later. What do you think?
>
> Yes, but first patch would be a step to get rid of mtk-infracfg and a second
> patch add bp_table and the like.
>
OK, I'll split into such sequence.
> >
> >>> obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
> >>> obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
> >>> diff --git a/drivers/soc/mediatek/mtk-scpsys-ext.c b/drivers/soc/mediatek/mtk-scpsys-ext.c
> >>> new file mode 100644
> >>> index 0000000..df402ac
> >>> --- /dev/null
> >>> +++ b/drivers/soc/mediatek/mtk-scpsys-ext.c
> >>
> >> I'm not quite sure why we should put this into a new file. I suppose the
> >> rational behind it is the fact that we access other blocks through regmap.
> >>
> >
> > Yes, those operation are accross infracfg and smi-common so we put these
> > into new files.
>
> Are you exepct other drivers to use this functions? If not I will have to think
> again, but I don't see any reason to put it into a new file.
>
I thought no other driver would use these functions unless there will
have drivers want to take over the bus protection process by themselves.
Do you prefer just putting these functions into mtk-scpsys.c?
> >
> >>> @@ -0,0 +1,101 @@
> >>> +// SPDX-License-Identifier: GPL-2.0
> >>> +/*
> >>> + * Copyright (c) 2018 MediaTek Inc.
> >>> + * Author: Owen Chen <Owen.Chen@mediatek.com>
> >>> + */
> >>> +#include <linux/ktime.h>
> >>> +#include <linux/mfd/syscon.h>
> >>> +#include <linux/of_device.h>
> >>> +#include <linux/regmap.h>
> >>> +#include "scpsys-ext.h"
> >>> +
> >>> +#define MTK_POLL_DELAY_US 10
> >>> +#define MTK_POLL_TIMEOUT USEC_PER_SEC
> >>> +
> >>> +static int set_bus_protection(struct regmap *map, u32 mask,
> >>> + u32 reg_set, u32 reg_sta, u32 reg_en)
> >>> +{
> >>> + u32 val;
> >>> +
> >>> + if (reg_set)
> >>> + regmap_write(map, reg_set, mask);
> >>> + else
> >>> + regmap_update_bits(map, reg_en, mask, mask);
> >>> +
> >>> + return regmap_read_poll_timeout(map, reg_sta,
> >>> + val, (val & mask) == mask,
> >>> + MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
> >>> +}
> >>> +
> >>> +static int clear_bus_protection(struct regmap *map, u32 mask,
> >>> + u32 reg_clr, u32 reg_sta, u32 reg_en, bool ignore_ack)
> >>> +{
> >>> + u32 val;
> >>> +
> >>> + if (reg_clr)
> >>> + regmap_write(map, reg_clr, mask);
> >>> + else
> >>> + regmap_update_bits(map, reg_en, mask, 0);
> >>> +
> >>> + if (ignore_ack)
> >>> + return 0;
> >>> +
> >>> + return regmap_read_poll_timeout(map, reg_sta,
> >>> + val, !(val & mask),
> >>> + MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
> >>> +}
> >>> +
> >>> +int mtk_scpsys_ext_set_bus_protection(const struct bus_prot *bp_table,
> >>> + struct regmap *infracfg, struct regmap *smi_common)
> >>> +{
> >>> + int i;
> >>> +
> >>> + for (i = 0; i < MAX_STEPS; i++) {
> >>
> >> struct bus_prot bp_table = bp_table[i];
> >>
> >
> > OK, got it.
> >
> >>> + struct regmap *map = NULL;
> >>> + int ret;
> >>> +
> >>> + if (bp_table[i].type == INVALID_TYPE)
> >>> + break;
> >>> + else if (bp_table[i].type == IFR_TYPE)
> >>> + map = infracfg;
> >>> + else if (bp_table[i].type == SMI_TYPE)
> >>> + map = smi_common;
> >>
> >> if (bp_table.type == IFR_TYPE)
> >> map = infracfg;
> >> else if (bp_table.type == SMI_TYPE)
> >> map = smi_common;
> >> else
> >> break;
> >>
> >
> > OK, got it.
> >
> >>> +
> >>> + ret = set_bus_protection(map,
> >>> + bp_table[i].mask, bp_table[i].set_ofs,
> >>> + bp_table[i].sta_ofs, bp_table[i].en_ofs);
> >>
> >> passing map and bp_table here makes code much more readable. I always end-up
> >> counting the variables when the names in the callee changes.
> >>
> >
> > OK, I'll fix it.
> >
> >>> +
> >>> + if (ret)
> >>> + return ret;
> >>> + }
> >>> +
> >>> + return 0;
> >>> +}
> >>> +
> >>> +int mtk_scpsys_ext_clear_bus_protection(const struct bus_prot *bp_table,
> >>> + struct regmap *infracfg, struct regmap *smi_common)
> >>> +{
> >>> + int i;
> >>> +
> >>> + for (i = MAX_STEPS - 1; i >= 0; i--) {
> >>> + struct regmap *map = NULL;
> >>> + int ret;
> >>> +
> >>> + if (bp_table[i].type == INVALID_TYPE)
> >>> + continue;
> >>> + else if (bp_table[i].type == IFR_TYPE)
> >>> + map = infracfg;
> >>> + else if (bp_table[i].type == SMI_TYPE)
> >>> + map = smi_common;
> >>> +
> >>> + ret = clear_bus_protection(map,
> >>> + bp_table[i].mask, bp_table[i].clr_ofs,
> >>> + bp_table[i].sta_ofs, bp_table[i].en_ofs,
> >>> + bp_table[i].ignore_clr_ack);
> >>> +
> >>
> >> same here.
> >>
> >
> > Got it.
> >
> >>> + if (ret)
> >>> + return ret;
> >>> + }
> >>> +
> >>> + return 0;
> >>> +}
> >>> diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
> >>> index db35a28..763ca58 100644
> >>> --- a/drivers/soc/mediatek/mtk-scpsys.c
> >>> +++ b/drivers/soc/mediatek/mtk-scpsys.c
> >>> @@ -11,7 +11,7 @@
> >>> #include <linux/platform_device.h>
> >>> #include <linux/pm_domain.h>
> >>> #include <linux/regulator/consumer.h>
> >>> -#include <linux/soc/mediatek/infracfg.h>
> >>> +#include "scpsys-ext.h"
> >>>
> >>> #include <dt-bindings/power/mt2701-power.h>
> >>> #include <dt-bindings/power/mt2712-power.h>
> >>> @@ -87,9 +87,9 @@
> >>> * @ctl_offs: The offset for main power control register.
> >>> * @sram_pdn_bits: The mask for sram power control bits.
> >>> * @sram_pdn_ack_bits: The mask for sram power control acked bits.
> >>> - * @bus_prot_mask: The mask for single step bus protection.
> >>> * @basic_clk_name: The basic clocks required by this power domain.
> >>> * @caps: The flag for active wake-up action.
> >>> + * @bp_table: The mask table for multiple step bus protection.
> >>> */
> >>> struct scp_domain_data {
> >>> const char *name;
> >>> @@ -97,9 +97,9 @@ struct scp_domain_data {
> >>> int ctl_offs;
> >>> u32 sram_pdn_bits;
> >>> u32 sram_pdn_ack_bits;
> >>> - u32 bus_prot_mask;
> >>> const char *basic_clk_name[MAX_CLKS];
> >>> u8 caps;
> >>> + struct bus_prot bp_table[MAX_STEPS];
> >>> };
> >>>
> >>> struct scp;
> >>> @@ -123,8 +123,8 @@ struct scp {
> >>> struct device *dev;
> >>> void __iomem *base;
> >>> struct regmap *infracfg;
> >>> + struct regmap *smi_common;
> >>> struct scp_ctrl_reg ctrl_reg;
> >>> - bool bus_prot_reg_update;
> >>> };
> >>>
> >>> struct scp_subdomain {
> >>> @@ -138,7 +138,6 @@ struct scp_soc_data {
> >>> const struct scp_subdomain *subdomains;
> >>> int num_subdomains;
> >>> const struct scp_ctrl_reg regs;
> >>> - bool bus_prot_reg_update;
> >>> };
> >>>
> >>> static int scpsys_domain_is_on(struct scp_domain *scpd)
> >>> @@ -252,24 +251,16 @@ static int scpsys_bus_protect_enable(struct scp_domain *scpd)
> >>> {
> >>> struct scp *scp = scpd->scp;
> >>>
> >>> - if (!scpd->data->bus_prot_mask)
> >>> - return 0;
> >>> -
> >>> - return mtk_infracfg_set_bus_protection(scp->infracfg,
> >>> - scpd->data->bus_prot_mask,
> >>> - scp->bus_prot_reg_update);
> >>> + return mtk_scpsys_ext_set_bus_protection(scpd->data->bp_table,
> >>> + scp->infracfg, scp->smi_common);
> >>
> >> Now that's just a wrapper which does add nothing but another indirection. We can
> >> call mtk_scpsys_ext_set_bus_protection() directly (also I don't like the name,
> >> actually why don't mtk_scpsys_set_bus_protection()?)
> >>
> >
> > You're right. I'll called mtk_scpsys_ext_set_bus_protection() directly.
> >
> >>> }
> >>>
> >>> static int scpsys_bus_protect_disable(struct scp_domain *scpd)
> >>> {
> >>> struct scp *scp = scpd->scp;
> >>>
> >>> - if (!scpd->data->bus_prot_mask)
> >>> - return 0;
> >>> -
> >>> - return mtk_infracfg_clear_bus_protection(scp->infracfg,
> >>> - scpd->data->bus_prot_mask,
> >>> - scp->bus_prot_reg_update);
> >>> + return mtk_scpsys_ext_clear_bus_protection(scpd->data->bp_table,
> >>> + scp->infracfg, scp->smi_common);
> >>> }
> >>>
> >>> static int scpsys_power_on(struct generic_pm_domain *genpd)
> >>> @@ -404,8 +395,7 @@ static int init_basic_clks(struct platform_device *pdev, struct clk **clk,
> >>>
> >>> static struct scp *init_scp(struct platform_device *pdev,
> >>> const struct scp_domain_data *scp_domain_data, int num,
> >>> - const struct scp_ctrl_reg *scp_ctrl_reg,
> >>> - bool bus_prot_reg_update)
> >>> + const struct scp_ctrl_reg *scp_ctrl_reg)
> >>> {
> >>> struct genpd_onecell_data *pd_data;
> >>> struct resource *res;
> >>> @@ -419,8 +409,6 @@ static struct scp *init_scp(struct platform_device *pdev,
> >>> scp->ctrl_reg.pwr_sta_offs = scp_ctrl_reg->pwr_sta_offs;
> >>> scp->ctrl_reg.pwr_sta2nd_offs = scp_ctrl_reg->pwr_sta2nd_offs;
> >>>
> >>> - scp->bus_prot_reg_update = bus_prot_reg_update;
> >>> -
> >>> scp->dev = &pdev->dev;
> >>>
> >>> res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> >>> @@ -448,6 +436,17 @@ static struct scp *init_scp(struct platform_device *pdev,
> >>> return ERR_CAST(scp->infracfg);
> >>> }
> >>>
> >>> + scp->smi_common = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
> >>> + "smi_comm");
> >>> +
> >>> + if (scp->smi_common == ERR_PTR(-ENODEV)) {
> >>> + scp->smi_common = NULL;
> >>> + } else if (IS_ERR(scp->smi_common)) {
> >>> + dev_err(&pdev->dev, "Cannot find smi_common controller: %ld\n",
> >>> + PTR_ERR(scp->smi_common));
> >>> + return ERR_CAST(scp->smi_common);
> >>> + }
> >>> +
> >>> for (i = 0; i < num; i++) {
> >>> struct scp_domain *scpd = &scp->domains[i];
> >>> const struct scp_domain_data *data = &scp_domain_data[i];
> >>> @@ -530,8 +529,11 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> >>> .name = "conn",
> >>> .sta_mask = PWR_STATUS_CONN,
> >>> .ctl_offs = SPM_CONN_PWR_CON,
> >>> - .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_CONN_M |
> >>> - MT2701_TOP_AXI_PROT_EN_CONN_S,
> >>> + .bp_table = {
> >>> + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
> >>> + MT2701_TOP_AXI_PROT_EN_CONN_M |
> >>> + MT2701_TOP_AXI_PROT_EN_CONN_S),
> >>> + },
> >>> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> >>> },
> >>> [MT2701_POWER_DOMAIN_DISP] = {
> >>> @@ -540,7 +542,10 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> >>> .ctl_offs = SPM_DIS_PWR_CON,
> >>> .sram_pdn_bits = GENMASK(11, 8),
> >>> .basic_clk_name = {"mm"},
> >>> - .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_MM_M0,
> >>> + .bp_table = {
> >>> + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
> >>> + MT2701_TOP_AXI_PROT_EN_MM_M0),
> >>> + },
> >>> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> >>> },
> >>> [MT2701_POWER_DOMAIN_MFG] = {
> >>> @@ -675,7 +680,10 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> >>> .sram_pdn_bits = GENMASK(8, 8),
> >>> .sram_pdn_ack_bits = GENMASK(16, 16),
> >>> .basic_clk_name = {"mfg"},
> >>> - .bus_prot_mask = BIT(14) | BIT(21) | BIT(23),
> >>> + .bp_table = {
> >>> + BUS_PROT(IFR_TYPE, 0x260, 0x264, 0x220, 0x228,
> >>> + BIT(14) | BIT(21) | BIT(23)),
> >>> + },
> >>> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> >>> },
> >>> [MT2712_POWER_DOMAIN_MFG_SC1] = {
> >>> @@ -747,7 +755,10 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> >>> .sram_pdn_bits = GENMASK(8, 8),
> >>> .sram_pdn_ack_bits = GENMASK(12, 12),
> >>> .basic_clk_name = {"mm"},
> >>> - .bus_prot_mask = (BIT(1) | BIT(2)),
> >>> + .bp_table = {
> >>> + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
> >>> + BIT(1) | BIT(2)),
> >>> + },
> >>> },
> >>> [MT6797_POWER_DOMAIN_AUDIO] = {
> >>> .name = "audio",
> >>> @@ -794,7 +805,10 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> >>> .ctl_offs = SPM_ETHSYS_PWR_CON,
> >>> .sram_pdn_bits = GENMASK(11, 8),
> >>> .sram_pdn_ack_bits = GENMASK(15, 12),
> >>> - .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_ETHSYS,
> >>> + .bp_table = {
> >>> + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
> >>> + MT7622_TOP_AXI_PROT_EN_ETHSYS),
> >>> + },
> >>> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> >>> },
> >>> [MT7622_POWER_DOMAIN_HIF0] = {
> >>> @@ -804,7 +818,10 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> >>> .sram_pdn_bits = GENMASK(11, 8),
> >>> .sram_pdn_ack_bits = GENMASK(15, 12),
> >>> .basic_clk_name = {"hif_sel"},
> >>> - .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_HIF0,
> >>> + .bp_table = {
> >>> + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
> >>> + MT7622_TOP_AXI_PROT_EN_HIF0),
> >>> + },
> >>> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> >>> },
> >>> [MT7622_POWER_DOMAIN_HIF1] = {
> >>> @@ -814,7 +831,10 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> >>> .sram_pdn_bits = GENMASK(11, 8),
> >>> .sram_pdn_ack_bits = GENMASK(15, 12),
> >>> .basic_clk_name = {"hif_sel"},
> >>> - .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_HIF1,
> >>> + .bp_table = {
> >>> + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
> >>> + MT7622_TOP_AXI_PROT_EN_HIF1),
> >>> + },
> >>> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> >>> },
> >>> [MT7622_POWER_DOMAIN_WB] = {
> >>> @@ -823,7 +843,10 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> >>> .ctl_offs = SPM_WB_PWR_CON,
> >>> .sram_pdn_bits = 0,
> >>> .sram_pdn_ack_bits = 0,
> >>> - .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_WB,
> >>> + .bp_table = {
> >>> + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
> >>> + MT7622_TOP_AXI_PROT_EN_WB),
> >>> + },
> >>> .caps = MTK_SCPD_ACTIVE_WAKEUP | MTK_SCPD_FWAIT_SRAM,
> >>> },
> >>> };
> >>> @@ -837,8 +860,11 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> >>> .name = "conn",
> >>> .sta_mask = PWR_STATUS_CONN,
> >>> .ctl_offs = SPM_CONN_PWR_CON,
> >>> - .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_CONN_M |
> >>> - MT2701_TOP_AXI_PROT_EN_CONN_S,
> >>> + .bp_table = {
> >>> + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
> >>> + MT2701_TOP_AXI_PROT_EN_CONN_M |
> >>> + MT2701_TOP_AXI_PROT_EN_CONN_S),
> >>> + },
> >>> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> >>> },
> >>> [MT7623A_POWER_DOMAIN_ETH] = {
> >>> @@ -903,8 +929,11 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> >>> .sram_pdn_bits = GENMASK(11, 8),
> >>> .sram_pdn_ack_bits = GENMASK(12, 12),
> >>> .basic_clk_name = {"mm"},
> >>> - .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 |
> >>> - MT8173_TOP_AXI_PROT_EN_MM_M1,
> >>> + .bp_table = {
> >>> + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
> >>> + MT8173_TOP_AXI_PROT_EN_MM_M0 |
> >>> + MT8173_TOP_AXI_PROT_EN_MM_M1),
> >>> + },
> >>> },
> >>> [MT8173_POWER_DOMAIN_VENC_LT] = {
> >>> .name = "venc_lt",
> >>> @@ -950,10 +979,13 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> >>> .ctl_offs = SPM_MFG_PWR_CON,
> >>> .sram_pdn_bits = GENMASK(13, 8),
> >>> .sram_pdn_ack_bits = GENMASK(21, 16),
> >>> - .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MFG_S |
> >>> - MT8173_TOP_AXI_PROT_EN_MFG_M0 |
> >>> - MT8173_TOP_AXI_PROT_EN_MFG_M1 |
> >>> - MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT,
> >>> + .bp_table = {
> >>> + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
> >>> + MT8173_TOP_AXI_PROT_EN_MFG_S |
> >>> + MT8173_TOP_AXI_PROT_EN_MFG_M0 |
> >>> + MT8173_TOP_AXI_PROT_EN_MFG_M1 |
> >>> + MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT),
> >>> + },
> >>> },
> >>> };
> >>>
> >>> @@ -969,7 +1001,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> >>> .pwr_sta_offs = SPM_PWR_STATUS,
> >>> .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
> >>> },
> >>> - .bus_prot_reg_update = true,
> >>> };
> >>>
> >>> static const struct scp_soc_data mt2712_data = {
> >>> @@ -981,7 +1012,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> >>> .pwr_sta_offs = SPM_PWR_STATUS,
> >>> .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
> >>> },
> >>> - .bus_prot_reg_update = false,
> >>> };
> >>>
> >>> static const struct scp_soc_data mt6797_data = {
> >>> @@ -993,7 +1023,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> >>> .pwr_sta_offs = SPM_PWR_STATUS_MT6797,
> >>> .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND_MT6797
> >>> },
> >>> - .bus_prot_reg_update = true,
> >>> };
> >>>
> >>> static const struct scp_soc_data mt7622_data = {
> >>> @@ -1003,7 +1032,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> >>> .pwr_sta_offs = SPM_PWR_STATUS,
> >>> .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
> >>> },
> >>> - .bus_prot_reg_update = true,
> >>> };
> >>>
> >>> static const struct scp_soc_data mt7623a_data = {
> >>> @@ -1013,7 +1041,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> >>> .pwr_sta_offs = SPM_PWR_STATUS,
> >>> .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
> >>> },
> >>> - .bus_prot_reg_update = true,
> >>> };
> >>>
> >>> static const struct scp_soc_data mt8173_data = {
> >>> @@ -1025,7 +1052,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> >>> .pwr_sta_offs = SPM_PWR_STATUS,
> >>> .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
> >>> },
> >>> - .bus_prot_reg_update = true,
> >>> };
> >>>
> >>> /*
> >>> @@ -1066,8 +1092,7 @@ static int scpsys_probe(struct platform_device *pdev)
> >>>
> >>> soc = of_device_get_match_data(&pdev->dev);
> >>>
> >>> - scp = init_scp(pdev, soc->domains, soc->num_domains, &soc->regs,
> >>> - soc->bus_prot_reg_update);
> >>> + scp = init_scp(pdev, soc->domains, soc->num_domains, &soc->regs);
> >>> if (IS_ERR(scp))
> >>> return PTR_ERR(scp);
> >>>
> >>> diff --git a/drivers/soc/mediatek/scpsys-ext.h b/drivers/soc/mediatek/scpsys-ext.h
> >>> new file mode 100644
> >>> index 0000000..458b2c5
> >>> --- /dev/null
> >>> +++ b/drivers/soc/mediatek/scpsys-ext.h
> >>> @@ -0,0 +1,67 @@
> >>> +/* SPDX-License-Identifier: GPL-2.0 */
> >>> +#ifndef __SOC_MEDIATEK_SCPSYS_EXT_H
> >>> +#define __SOC_MEDIATEK_SCPSYS_EXT_H
> >>> +
> >>> +#define MAX_STEPS 4
> >>> +
> >>> +#define _BUS_PROT(_type, _set_ofs, _clr_ofs, \
> >>> + _en_ofs, _sta_ofs, _mask, _ignore_clr_ack) { \
> >>> + .type = _type, \
> >>> + .set_ofs = _set_ofs, \
> >>> + .clr_ofs = _clr_ofs, \
> >>> + .en_ofs = _en_ofs, \
> >>> + .sta_ofs = _sta_ofs, \
> >>> + .mask = _mask, \
> >>> + .ignore_clr_ack = _ignore_clr_ack, \
> >>> + }
> >>> +
> >>> +#define BUS_PROT(_type, _set_ofs, _clr_ofs, \
> >>> + _en_ofs, _sta_ofs, _mask) \
> >>> + _BUS_PROT(_type, _set_ofs, _clr_ofs, \
> >>> + _en_ofs, _sta_ofs, _mask, false)
> >>> +
> >>> +#define BUS_PROT_IGN(_type, _set_ofs, _clr_ofs, \
> >>> + _en_ofs, _sta_ofs, _mask) \
> >>> + _BUS_PROT(_type, _set_ofs, _clr_ofs, \
> >>> + _en_ofs, _sta_ofs, _mask, true)
> >>> +
> >>> +#define MT2701_TOP_AXI_PROT_EN_MM_M0 BIT(1)
> >>> +#define MT2701_TOP_AXI_PROT_EN_CONN_M BIT(2)
> >>> +#define MT2701_TOP_AXI_PROT_EN_CONN_S BIT(8)
> >>> +
> >>> +#define MT7622_TOP_AXI_PROT_EN_ETHSYS (BIT(3) | BIT(17))
> >>> +#define MT7622_TOP_AXI_PROT_EN_HIF0 (BIT(24) | BIT(25))
> >>> +#define MT7622_TOP_AXI_PROT_EN_HIF1 (BIT(26) | BIT(27) | \
> >>> + BIT(28))
> >>> +#define MT7622_TOP_AXI_PROT_EN_WB (BIT(2) | BIT(6) | \
> >>> + BIT(7) | BIT(8))
> >>> +
> >>> +#define MT8173_TOP_AXI_PROT_EN_MM_M0 BIT(1)
> >>> +#define MT8173_TOP_AXI_PROT_EN_MM_M1 BIT(2)
> >>> +#define MT8173_TOP_AXI_PROT_EN_MFG_S BIT(14)
> >>> +#define MT8173_TOP_AXI_PROT_EN_MFG_M0 BIT(21)
> >>> +#define MT8173_TOP_AXI_PROT_EN_MFG_M1 BIT(22)
> >>> +#define MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT BIT(23)
> >>> +
> >>> +enum regmap_type {
> >>> + INVALID_TYPE = 0,
> >>> + IFR_TYPE,
> >>> + SMI_TYPE,
> >>> +};
> >>> +
> >>> +struct bus_prot {
> >>> + enum regmap_type type;
> >>> + u32 set_ofs;
> >>> + u32 clr_ofs;
> >>
> >> Please try to keep variable names consistent. You change for example set_ofs to
> >> reg_set. That makes the code more difficult to read and understand.
> >>
> >
> > OK, I'll keep those names consistent.
> >
> >>> + u32 en_ofs;
> >>> + u32 sta_ofs;
> >>> + u32 mask;
> >>> + bool ignore_clr_ack;
> >>> +};
> >>> +
> >>> +int mtk_scpsys_ext_set_bus_protection(const struct bus_prot *bp_table,
> >>> + struct regmap *infracfg, struct regmap *smi_common);
> >>> +int mtk_scpsys_ext_clear_bus_protection(const struct bus_prot *bp_table,
> >>> + struct regmap *infracfg, struct regmap *smi_common);
> >>> +
> >>> +#endif /* __SOC_MEDIATEK_SCPSYS_EXT_H */
> >>>
> >
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v11 06/10] soc: mediatek: Add subsys clock control for bus protection
2020-02-12 11:02 ` Matthias Brugger
@ 2020-02-13 2:46 ` Weiyi Lu
2020-02-13 12:56 ` Matthias Brugger
0 siblings, 1 reply; 33+ messages in thread
From: Weiyi Lu @ 2020-02-13 2:46 UTC (permalink / raw)
To: Matthias Brugger
Cc: Rob Herring, Nicolas Boichat, srv_heupstream, James Liao,
linux-kernel, Fan Chen, linux-mediatek, Sascha Hauer,
linux-arm-kernel
On Wed, 2020-02-12 at 12:02 +0100, Matthias Brugger wrote:
>
> On 12/02/2020 03:55, Weiyi Lu wrote:
> > On Tue, 2020-02-11 at 18:54 +0100, Matthias Brugger wrote:
> >>
> >> On 20/12/2019 04:46, Weiyi Lu wrote:
> >>> Add subsys CG control flow before/after the bus protect control
> >>> due to bus protection need SMI bus relative CGs enabled to feedback
> >>> its ack.
> >>>
> >>
> >> Sorry, I don't understand the commit message. Can you please rephrase and
> >> explain better what this change is for.
> >>
> >
> > OK! I'll reword it.
> >
> >>> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> >>> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
> >>> ---
> >>> drivers/soc/mediatek/mtk-scpsys.c | 72 +++++++++++++++++++++++++++++++++++++--
> >>> 1 file changed, 70 insertions(+), 2 deletions(-)
> >>>
> >>> diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
> >>> index 763ca58..32be4b3 100644
> >>> --- a/drivers/soc/mediatek/mtk-scpsys.c
> >>> +++ b/drivers/soc/mediatek/mtk-scpsys.c
> >>> @@ -79,6 +79,7 @@
> >>> #define PWR_STATUS_WB BIT(27) /* MT7622 */
> >>>
> >>> #define MAX_CLKS 3
> >>> +#define MAX_SUBSYS_CLKS 10
> >>>
> >>> /**
> >>> * struct scp_domain_data - scp domain data for power on/off flow
> >>> @@ -88,6 +89,8 @@
> >>> * @sram_pdn_bits: The mask for sram power control bits.
> >>> * @sram_pdn_ack_bits: The mask for sram power control acked bits.
> >>> * @basic_clk_name: The basic clocks required by this power domain.
> >>> + * @subsys_clk_prefix: The prefix name of the clocks need to be enabled
> >>> + * before releasing bus protection.
> >>> * @caps: The flag for active wake-up action.
> >>> * @bp_table: The mask table for multiple step bus protection.
> >>> */
> >>> @@ -98,6 +101,7 @@ struct scp_domain_data {
> >>> u32 sram_pdn_bits;
> >>> u32 sram_pdn_ack_bits;
> >>> const char *basic_clk_name[MAX_CLKS];
> >>> + const char *subsys_clk_prefix;
> >>> u8 caps;
> >>> struct bus_prot bp_table[MAX_STEPS];
> >>> };
> >>> @@ -108,6 +112,7 @@ struct scp_domain {
> >>> struct generic_pm_domain genpd;
> >>> struct scp *scp;
> >>> struct clk *clk[MAX_CLKS];
> >>> + struct clk *subsys_clk[MAX_SUBSYS_CLKS];
> >>> const struct scp_domain_data *data;
> >>> struct regulator *supply;
> >>> };
> >>> @@ -301,16 +306,22 @@ static int scpsys_power_on(struct generic_pm_domain *genpd)
> >>> val |= PWR_RST_B_BIT;
> >>> writel(val, ctl_addr);
> >>>
> >>> - ret = scpsys_sram_enable(scpd, ctl_addr);
> >>> + ret = scpsys_clk_enable(scpd->subsys_clk, MAX_SUBSYS_CLKS);
> >>
> >> Why can't we enable the subsystem clocks together with the rest just after
> >> enabeling the regulator?
> >>
> >
> > Subsys CG could only be enabled when its own power domain is already
> > turned ON, and vice versa.
> > In the dt-binding doc we mentioned there would have two groups of
> > clocks.
> > e.g.,
> > BASIC clocks need to be enabled before enabling the corresponding power
> > domain.
> > SUBSYS clocks need to be enabled before releasing the bus protection.
> >
>
> Do I understand correctly that we could enable/disable all clocks in the same
> place as long as we make sure that the the basic clocks are turned on before we
> turn on the subsys clocks, correct?
>
simply, yes
> So why do we need to implement this logic in the power-controller driver?
> Shouldn't that be part of the common clock driver?
>
we implement the subsys clock logic here just due to we already
implement the bus protection flow in the power-controller driver.
And If we don't enable the subsys clocks, bus protection cannot work.
Hence, even the subsys power is on but the HW modules under this subsys
power cannot access the bus though.
> Regards,
> Matthias
>
> >>> if (ret < 0)
> >>> goto err_pwr_ack;
> >>>
> >>> + ret = scpsys_sram_enable(scpd, ctl_addr);
> >>> + if (ret < 0)
> >>> + goto err_sram;
> >>> +
> >>> ret = scpsys_bus_protect_disable(scpd);
> >>> if (ret < 0)
> >>> - goto err_pwr_ack;
> >>> + goto err_sram;
> >>>
> >>> return 0;
> >>>
> >>> +err_sram:
> >>> + scpsys_clk_disable(scpd->subsys_clk, MAX_SUBSYS_CLKS);
> >>> err_pwr_ack:
> >>> scpsys_clk_disable(scpd->clk, MAX_CLKS);
> >>> err_clk:
> >>> @@ -337,6 +348,8 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
> >>> if (ret < 0)
> >>> goto out;
> >>>
> >>> + scpsys_clk_disable(scpd->subsys_clk, MAX_SUBSYS_CLKS);
> >>> +
> >>
> >> Same here, why can't we disable the clocks in the scpsys_clk_disable call?
> >>
> >>> /* subsys power off */
> >>> val = readl(ctl_addr);
> >>> val |= PWR_ISO_BIT;
> >>> @@ -374,6 +387,48 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
> >>> return ret;
> >>> }
> >>>
> >>> +static int init_subsys_clks(struct platform_device *pdev,
> >>> + const char *prefix, struct clk **clk)
> >>> +{
> >>> + struct device_node *node = pdev->dev.of_node;
> >>> + u32 prefix_len, sub_clk_cnt = 0;
> >>> + struct property *prop;
> >>> + const char *clk_name;
> >>> +
> >>> + if (!node) {
> >>> + dev_err(&pdev->dev, "Cannot find scpsys node: %ld\n",
> >>> + PTR_ERR(node));
> >>> + return PTR_ERR(node);
> >>> + }
> >>> +
> >>> + prefix_len = strlen(prefix);
> >>> +
> >>> + of_property_for_each_string(node, "clock-names", prop, clk_name) {
> >>> + if (!strncmp(clk_name, prefix, prefix_len) &&
> >>> + (clk_name[prefix_len] == '-')) {
> >>> + if (sub_clk_cnt >= MAX_SUBSYS_CLKS) {
> >>> + dev_err(&pdev->dev,
> >>> + "subsys clk out of range %d\n",
> >>> + sub_clk_cnt);
> >>> + return -ENOMEM;
> >>
> >> EINVAL maybe, ENOMEM seems wrong here.
> >>
> >
> > OK, I'll fix with correct error.
> >
> >>> + }
> >>> +
> >>> + clk[sub_clk_cnt] = devm_clk_get(&pdev->dev,
> >>> + clk_name);
> >>
> >> Here we get hit by the bad design of this driver in the first place. As we need
> >> the subsystem-name (eg mm-0, mm-1) to group clocks to one scp_domain.
> >> I think we should better try to model the domains and subdomains in DTS and add
> >> their clocks to it. This way we can also get rid of the scp_subdomain which can
> >> hit it's limit anytime soon when we have a chip with a sub-subdomain.
> >> That will need a new driver, but as it seems the mt8183 and the mt6765 have a
> >> more complex design I think it is worth it.
> >>
> >> That said, given that you are in v11 already I understand that your motivation
> >> to start over isn't the biggest. The problem is, any new driver will have new
> >> bindings and won't work with older DTS. So adding a lot of stuff on top of a not
> >> really nice driver isn't something I'm very keen on. On the other hand you
> >> already put a lot of work into this solution.
> >>
> >> My proposal, I'll try to bake up a new driver this week. If I fail to deliver,
> >> it's up to you to decide if you want to go on with the approach in this series
> >> or try to work on the new one.
> >
> >> Regards,
> >> Matthias
> >>
> >
> > Thanks for considering our request.
> >
> >>> +
> >>> + if (IS_ERR(clk[sub_clk_cnt])) {
> >>> + dev_err(&pdev->dev,
> >>> + "Subsys clk get fail %ld\n",
> >>> + PTR_ERR(clk[sub_clk_cnt]));
> >>> + return PTR_ERR(clk[sub_clk_cnt]);
> >>> + }
> >>> + sub_clk_cnt++;
> >>> + }
> >>> + }
> >>> +
> >>> + return sub_clk_cnt;
> >>> +}
> >>> +
> >>> static int init_basic_clks(struct platform_device *pdev, struct clk **clk,
> >>> const char * const *name)
> >>> {
> >>> @@ -466,6 +521,7 @@ static struct scp *init_scp(struct platform_device *pdev,
> >>> struct scp_domain *scpd = &scp->domains[i];
> >>> struct generic_pm_domain *genpd = &scpd->genpd;
> >>> const struct scp_domain_data *data = &scp_domain_data[i];
> >>> + int clk_cnt;
> >>
> >> clk_cnt sounds to me like clock count, but the variable actually is only used to
> >> check the return value of init_subsys_clks. Please rename it to ret or something
> >> like this.
> >>
> >
> > OK, I'll fix it.
> >
> >>>
> >>> pd_data->domains[i] = genpd;
> >>> scpd->scp = scp;
> >>> @@ -476,6 +532,18 @@ static struct scp *init_scp(struct platform_device *pdev,
> >>> if (ret)
> >>> return ERR_PTR(ret);
> >>>
> >>> + if (data->subsys_clk_prefix) {
> >>> + clk_cnt = init_subsys_clks(pdev,
> >>> + data->subsys_clk_prefix,
> >>> + scpd->subsys_clk);
> >>> + if (clk_cnt < 0) {
> >>> + dev_err(&pdev->dev,
> >>> + "%s: subsys clk unavailable\n",
> >>> + data->name);
> >>> + return ERR_PTR(clk_cnt);
> >>> + }
> >>> + }
> >>> +
> >>> genpd->name = data->name;
> >>> genpd->power_off = scpsys_power_off;
> >>> genpd->power_on = scpsys_power_on;
> >>>
> >
>
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v11 04/10] soc: mediatek: Add multiple step bus protection control
2020-02-13 2:15 ` Weiyi Lu
@ 2020-02-13 11:11 ` Matthias Brugger
0 siblings, 0 replies; 33+ messages in thread
From: Matthias Brugger @ 2020-02-13 11:11 UTC (permalink / raw)
To: Weiyi Lu
Cc: Nicolas Boichat, Rob Herring, Sascha Hauer, James Liao, Fan Chen,
linux-arm-kernel, linux-kernel, linux-mediatek, srv_heupstream
On 13/02/2020 03:15, Weiyi Lu wrote:
> On Wed, 2020-02-12 at 10:23 +0100, Matthias Brugger wrote:
>>
>> On 12/02/2020 03:55, Weiyi Lu wrote:
>>> On Tue, 2020-02-11 at 18:49 +0100, Matthias Brugger wrote:
>>>>
>>>> On 20/12/2019 04:45, Weiyi Lu wrote:
>>>>> Both MT8183 & MT6765 have more control steps of bus protection
>>>>> than previous project. And there add more bus protection registers
>>>>> reside at infracfg & smi-common. Also add new APIs for multiple
>>>>> step bus protection control with more customized arguments.
>>>>> And then use bp_table for bus protection of all compatibles,
>>>>> instead of mixing bus_prot_mask and bus_prot_reg_update.
>>>>>
>>>>> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
>>>>> ---
>>>>> drivers/soc/mediatek/Makefile | 2 +-
>>>>> drivers/soc/mediatek/mtk-scpsys-ext.c | 101 +++++++++++++++++++++++++++++
>>>>> drivers/soc/mediatek/mtk-scpsys.c | 117 +++++++++++++++++++++-------------
>>>>> drivers/soc/mediatek/scpsys-ext.h | 67 +++++++++++++++++++
>>>>> 4 files changed, 240 insertions(+), 47 deletions(-)
>>>>> create mode 100644 drivers/soc/mediatek/mtk-scpsys-ext.c
>>>>> create mode 100644 drivers/soc/mediatek/scpsys-ext.h
>>>>>
>>>>> diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
>>>>> index b017330..b442be9 100644
>>>>> --- a/drivers/soc/mediatek/Makefile
>>>>> +++ b/drivers/soc/mediatek/Makefile
>>>>> @@ -1,5 +1,5 @@
>>>>> # SPDX-License-Identifier: GPL-2.0-only
>>>>> obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o
>>>>> -obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
>>>>> +obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o mtk-scpsys-ext.o
>>>>
>>>> It seems that we would need another patch which get's rid of the mtk-infracfg
>>>> first and then add stuff like the possibility to have different steps.
>>>>
>>>
>>> Actually I have a PATCH 05/11 to remove the mtk-infracfg.
>>> In this patch, I have some changes, like calling
>>> mtk_scpsys_ext_set_bus_protection(...) instead of
>>> mtk_infracfg_set_bus_protection(...) in scpsys_bus_protect_enable(...)
>>> and replacing bus_prot_mask by bp_table.
>>> I thought I should introduce the new method first and remove useless one
>>> later. What do you think?
>>
>> Yes, but first patch would be a step to get rid of mtk-infracfg and a second
>> patch add bp_table and the like.
>>
>
> OK, I'll split into such sequence.
>
>>>
>>>>> obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
>>>>> obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
>>>>> diff --git a/drivers/soc/mediatek/mtk-scpsys-ext.c b/drivers/soc/mediatek/mtk-scpsys-ext.c
>>>>> new file mode 100644
>>>>> index 0000000..df402ac
>>>>> --- /dev/null
>>>>> +++ b/drivers/soc/mediatek/mtk-scpsys-ext.c
>>>>
>>>> I'm not quite sure why we should put this into a new file. I suppose the
>>>> rational behind it is the fact that we access other blocks through regmap.
>>>>
>>>
>>> Yes, those operation are accross infracfg and smi-common so we put these
>>> into new files.
>>
>> Are you exepct other drivers to use this functions? If not I will have to think
>> again, but I don't see any reason to put it into a new file.
>>
>
> I thought no other driver would use these functions unless there will
> have drivers want to take over the bus protection process by themselves.
>
> Do you prefer just putting these functions into mtk-scpsys.c?
>
Yes I'd prefer that.
Regards,
Matthias
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v11 06/10] soc: mediatek: Add subsys clock control for bus protection
2020-02-13 2:46 ` Weiyi Lu
@ 2020-02-13 12:56 ` Matthias Brugger
2020-02-14 6:33 ` Weiyi Lu
2020-02-14 6:42 ` Weiyi Lu
0 siblings, 2 replies; 33+ messages in thread
From: Matthias Brugger @ 2020-02-13 12:56 UTC (permalink / raw)
To: Weiyi Lu
Cc: Rob Herring, Nicolas Boichat, srv_heupstream, James Liao,
linux-kernel, Fan Chen, linux-mediatek, Sascha Hauer,
linux-arm-kernel
On 13/02/2020 03:46, Weiyi Lu wrote:
> On Wed, 2020-02-12 at 12:02 +0100, Matthias Brugger wrote:
>>
>> On 12/02/2020 03:55, Weiyi Lu wrote:
>>> On Tue, 2020-02-11 at 18:54 +0100, Matthias Brugger wrote:
>>>>
>>>> On 20/12/2019 04:46, Weiyi Lu wrote:
>>>>> Add subsys CG control flow before/after the bus protect control
>>>>> due to bus protection need SMI bus relative CGs enabled to feedback
>>>>> its ack.
>>>>>
>>>>
>>>> Sorry, I don't understand the commit message. Can you please rephrase and
>>>> explain better what this change is for.
>>>>
>>>
>>> OK! I'll reword it.
>>>
>>>>> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
>>>>> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
>>>>> ---
>>>>> drivers/soc/mediatek/mtk-scpsys.c | 72 +++++++++++++++++++++++++++++++++++++--
>>>>> 1 file changed, 70 insertions(+), 2 deletions(-)
>>>>>
>>>>> diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
>>>>> index 763ca58..32be4b3 100644
>>>>> --- a/drivers/soc/mediatek/mtk-scpsys.c
>>>>> +++ b/drivers/soc/mediatek/mtk-scpsys.c
>>>>> @@ -79,6 +79,7 @@
>>>>> #define PWR_STATUS_WB BIT(27) /* MT7622 */
>>>>>
>>>>> #define MAX_CLKS 3
>>>>> +#define MAX_SUBSYS_CLKS 10
>>>>>
>>>>> /**
>>>>> * struct scp_domain_data - scp domain data for power on/off flow
>>>>> @@ -88,6 +89,8 @@
>>>>> * @sram_pdn_bits: The mask for sram power control bits.
>>>>> * @sram_pdn_ack_bits: The mask for sram power control acked bits.
>>>>> * @basic_clk_name: The basic clocks required by this power domain.
>>>>> + * @subsys_clk_prefix: The prefix name of the clocks need to be enabled
>>>>> + * before releasing bus protection.
>>>>> * @caps: The flag for active wake-up action.
>>>>> * @bp_table: The mask table for multiple step bus protection.
>>>>> */
>>>>> @@ -98,6 +101,7 @@ struct scp_domain_data {
>>>>> u32 sram_pdn_bits;
>>>>> u32 sram_pdn_ack_bits;
>>>>> const char *basic_clk_name[MAX_CLKS];
>>>>> + const char *subsys_clk_prefix;
>>>>> u8 caps;
>>>>> struct bus_prot bp_table[MAX_STEPS];
>>>>> };
>>>>> @@ -108,6 +112,7 @@ struct scp_domain {
>>>>> struct generic_pm_domain genpd;
>>>>> struct scp *scp;
>>>>> struct clk *clk[MAX_CLKS];
>>>>> + struct clk *subsys_clk[MAX_SUBSYS_CLKS];
>>>>> const struct scp_domain_data *data;
>>>>> struct regulator *supply;
>>>>> };
>>>>> @@ -301,16 +306,22 @@ static int scpsys_power_on(struct generic_pm_domain *genpd)
>>>>> val |= PWR_RST_B_BIT;
>>>>> writel(val, ctl_addr);
>>>>>
>>>>> - ret = scpsys_sram_enable(scpd, ctl_addr);
>>>>> + ret = scpsys_clk_enable(scpd->subsys_clk, MAX_SUBSYS_CLKS);
>>>>
>>>> Why can't we enable the subsystem clocks together with the rest just after
>>>> enabeling the regulator?
>>>>
>>>
>>> Subsys CG could only be enabled when its own power domain is already
>>> turned ON, and vice versa.
>>> In the dt-binding doc we mentioned there would have two groups of
>>> clocks.
>>> e.g.,
>>> BASIC clocks need to be enabled before enabling the corresponding power
>>> domain.
>>> SUBSYS clocks need to be enabled before releasing the bus protection.
>>>
>>
>> Do I understand correctly that we could enable/disable all clocks in the same
>> place as long as we make sure that the the basic clocks are turned on before we
>> turn on the subsys clocks, correct?
>>
>
> simply, yes
>
>> So why do we need to implement this logic in the power-controller driver?
>> Shouldn't that be part of the common clock driver?
>>
>
> we implement the subsys clock logic here just due to we already
> implement the bus protection flow in the power-controller driver.
I think in this driver is the correct place to implement bus protection flow.
> And If we don't enable the subsys clocks, bus protection cannot work.
> Hence, even the subsys power is on but the HW modules under this subsys
> power cannot access the bus though.
Ok, I understand that. But I understand that this should be fixed in the clock
driver. It seems the clock driver does not reflect the correct clock tree.
For example:
clocks CLK_MM_SMI_COMMON, CLK_MM_SMI_LARB0, CLK_MM_SMI_LARB1, CLK_MM_GALS_COMM0,
CLK_MM_GALS_COMM1, CLK_MM_GALS_CCU2MM, CLK_MM_GALS_IPU12MM, CLK_MM_GALS_IMG2MM,
CLK_MM_GALS_CAM2MM, CLK_MM_GALS_IPU2MM need the CLK_TOP_MUX_MM to be enabled
first. So I suppose CLK_TOP_MUX_MM is the parent clock of the other CLK_MM_*
clocks. If the clock tree is correctly described in the clock driver, then the
common clock framework will take care to enable CLK_TOP_MUX_MM when you try to
enable an CLK_MM_* clocks.
Why does that not work on mt8183? My impression after a quick look into the
clock driver is, that this should work.
Regards,
Matthias
>
>> Regards,
>> Matthias
>>
>>>>> if (ret < 0)
>>>>> goto err_pwr_ack;
>>>>>
>>>>> + ret = scpsys_sram_enable(scpd, ctl_addr);
>>>>> + if (ret < 0)
>>>>> + goto err_sram;
>>>>> +
>>>>> ret = scpsys_bus_protect_disable(scpd);
>>>>> if (ret < 0)
>>>>> - goto err_pwr_ack;
>>>>> + goto err_sram;
>>>>>
>>>>> return 0;
>>>>>
>>>>> +err_sram:
>>>>> + scpsys_clk_disable(scpd->subsys_clk, MAX_SUBSYS_CLKS);
>>>>> err_pwr_ack:
>>>>> scpsys_clk_disable(scpd->clk, MAX_CLKS);
>>>>> err_clk:
>>>>> @@ -337,6 +348,8 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
>>>>> if (ret < 0)
>>>>> goto out;
>>>>>
>>>>> + scpsys_clk_disable(scpd->subsys_clk, MAX_SUBSYS_CLKS);
>>>>> +
>>>>
>>>> Same here, why can't we disable the clocks in the scpsys_clk_disable call?
>>>>
>>>>> /* subsys power off */
>>>>> val = readl(ctl_addr);
>>>>> val |= PWR_ISO_BIT;
>>>>> @@ -374,6 +387,48 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
>>>>> return ret;
>>>>> }
>>>>>
>>>>> +static int init_subsys_clks(struct platform_device *pdev,
>>>>> + const char *prefix, struct clk **clk)
>>>>> +{
>>>>> + struct device_node *node = pdev->dev.of_node;
>>>>> + u32 prefix_len, sub_clk_cnt = 0;
>>>>> + struct property *prop;
>>>>> + const char *clk_name;
>>>>> +
>>>>> + if (!node) {
>>>>> + dev_err(&pdev->dev, "Cannot find scpsys node: %ld\n",
>>>>> + PTR_ERR(node));
>>>>> + return PTR_ERR(node);
>>>>> + }
>>>>> +
>>>>> + prefix_len = strlen(prefix);
>>>>> +
>>>>> + of_property_for_each_string(node, "clock-names", prop, clk_name) {
>>>>> + if (!strncmp(clk_name, prefix, prefix_len) &&
>>>>> + (clk_name[prefix_len] == '-')) {
>>>>> + if (sub_clk_cnt >= MAX_SUBSYS_CLKS) {
>>>>> + dev_err(&pdev->dev,
>>>>> + "subsys clk out of range %d\n",
>>>>> + sub_clk_cnt);
>>>>> + return -ENOMEM;
>>>>
>>>> EINVAL maybe, ENOMEM seems wrong here.
>>>>
>>>
>>> OK, I'll fix with correct error.
>>>
>>>>> + }
>>>>> +
>>>>> + clk[sub_clk_cnt] = devm_clk_get(&pdev->dev,
>>>>> + clk_name);
>>>>
>>>> Here we get hit by the bad design of this driver in the first place. As we need
>>>> the subsystem-name (eg mm-0, mm-1) to group clocks to one scp_domain.
>>>> I think we should better try to model the domains and subdomains in DTS and add
>>>> their clocks to it. This way we can also get rid of the scp_subdomain which can
>>>> hit it's limit anytime soon when we have a chip with a sub-subdomain.
>>>> That will need a new driver, but as it seems the mt8183 and the mt6765 have a
>>>> more complex design I think it is worth it.
>>>>
>>>> That said, given that you are in v11 already I understand that your motivation
>>>> to start over isn't the biggest. The problem is, any new driver will have new
>>>> bindings and won't work with older DTS. So adding a lot of stuff on top of a not
>>>> really nice driver isn't something I'm very keen on. On the other hand you
>>>> already put a lot of work into this solution.
>>>>
>>>> My proposal, I'll try to bake up a new driver this week. If I fail to deliver,
>>>> it's up to you to decide if you want to go on with the approach in this series
>>>> or try to work on the new one.
>>>
>>>> Regards,
>>>> Matthias
>>>>
>>>
>>> Thanks for considering our request.
>>>
>>>>> +
>>>>> + if (IS_ERR(clk[sub_clk_cnt])) {
>>>>> + dev_err(&pdev->dev,
>>>>> + "Subsys clk get fail %ld\n",
>>>>> + PTR_ERR(clk[sub_clk_cnt]));
>>>>> + return PTR_ERR(clk[sub_clk_cnt]);
>>>>> + }
>>>>> + sub_clk_cnt++;
>>>>> + }
>>>>> + }
>>>>> +
>>>>> + return sub_clk_cnt;
>>>>> +}
>>>>> +
>>>>> static int init_basic_clks(struct platform_device *pdev, struct clk **clk,
>>>>> const char * const *name)
>>>>> {
>>>>> @@ -466,6 +521,7 @@ static struct scp *init_scp(struct platform_device *pdev,
>>>>> struct scp_domain *scpd = &scp->domains[i];
>>>>> struct generic_pm_domain *genpd = &scpd->genpd;
>>>>> const struct scp_domain_data *data = &scp_domain_data[i];
>>>>> + int clk_cnt;
>>>>
>>>> clk_cnt sounds to me like clock count, but the variable actually is only used to
>>>> check the return value of init_subsys_clks. Please rename it to ret or something
>>>> like this.
>>>>
>>>
>>> OK, I'll fix it.
>>>
>>>>>
>>>>> pd_data->domains[i] = genpd;
>>>>> scpd->scp = scp;
>>>>> @@ -476,6 +532,18 @@ static struct scp *init_scp(struct platform_device *pdev,
>>>>> if (ret)
>>>>> return ERR_PTR(ret);
>>>>>
>>>>> + if (data->subsys_clk_prefix) {
>>>>> + clk_cnt = init_subsys_clks(pdev,
>>>>> + data->subsys_clk_prefix,
>>>>> + scpd->subsys_clk);
>>>>> + if (clk_cnt < 0) {
>>>>> + dev_err(&pdev->dev,
>>>>> + "%s: subsys clk unavailable\n",
>>>>> + data->name);
>>>>> + return ERR_PTR(clk_cnt);
>>>>> + }
>>>>> + }
>>>>> +
>>>>> genpd->name = data->name;
>>>>> genpd->power_off = scpsys_power_off;
>>>>> genpd->power_on = scpsys_power_on;
>>>>>
>>>
>>
>> _______________________________________________
>> Linux-mediatek mailing list
>> Linux-mediatek@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-mediatek
>
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v11 06/10] soc: mediatek: Add subsys clock control for bus protection
2020-02-13 12:56 ` Matthias Brugger
@ 2020-02-14 6:33 ` Weiyi Lu
2020-02-14 6:42 ` Weiyi Lu
1 sibling, 0 replies; 33+ messages in thread
From: Weiyi Lu @ 2020-02-14 6:33 UTC (permalink / raw)
To: Matthias Brugger
Cc: Rob Herring, Nicolas Boichat, srv_heupstream, James Liao,
linux-kernel, Fan Chen, linux-mediatek, Sascha Hauer,
linux-arm-kernel
On Thu, 2020-02-13 at 13:56 +0100, Matthias Brugger wrote:
>
> On 13/02/2020 03:46, Weiyi Lu wrote:
> > On Wed, 2020-02-12 at 12:02 +0100, Matthias Brugger wrote:
> >>
> >> On 12/02/2020 03:55, Weiyi Lu wrote:
> >>> On Tue, 2020-02-11 at 18:54 +0100, Matthias Brugger wrote:
> >>>>
> >>>> On 20/12/2019 04:46, Weiyi Lu wrote:
> >>>>> Add subsys CG control flow before/after the bus protect control
> >>>>> due to bus protection need SMI bus relative CGs enabled to feedback
> >>>>> its ack.
> >>>>>
> >>>>
> >>>> Sorry, I don't understand the commit message. Can you please rephrase and
> >>>> explain better what this change is for.
> >>>>
> >>>
> >>> OK! I'll reword it.
> >>>
> >>>>> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> >>>>> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
> >>>>> ---
> >>>>> drivers/soc/mediatek/mtk-scpsys.c | 72 +++++++++++++++++++++++++++++++++++++--
> >>>>> 1 file changed, 70 insertions(+), 2 deletions(-)
> >>>>>
> >>>>> diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
> >>>>> index 763ca58..32be4b3 100644
> >>>>> --- a/drivers/soc/mediatek/mtk-scpsys.c
> >>>>> +++ b/drivers/soc/mediatek/mtk-scpsys.c
> >>>>> @@ -79,6 +79,7 @@
> >>>>> #define PWR_STATUS_WB BIT(27) /* MT7622 */
> >>>>>
> >>>>> #define MAX_CLKS 3
> >>>>> +#define MAX_SUBSYS_CLKS 10
> >>>>>
> >>>>> /**
> >>>>> * struct scp_domain_data - scp domain data for power on/off flow
> >>>>> @@ -88,6 +89,8 @@
> >>>>> * @sram_pdn_bits: The mask for sram power control bits.
> >>>>> * @sram_pdn_ack_bits: The mask for sram power control acked bits.
> >>>>> * @basic_clk_name: The basic clocks required by this power domain.
> >>>>> + * @subsys_clk_prefix: The prefix name of the clocks need to be enabled
> >>>>> + * before releasing bus protection.
> >>>>> * @caps: The flag for active wake-up action.
> >>>>> * @bp_table: The mask table for multiple step bus protection.
> >>>>> */
> >>>>> @@ -98,6 +101,7 @@ struct scp_domain_data {
> >>>>> u32 sram_pdn_bits;
> >>>>> u32 sram_pdn_ack_bits;
> >>>>> const char *basic_clk_name[MAX_CLKS];
> >>>>> + const char *subsys_clk_prefix;
> >>>>> u8 caps;
> >>>>> struct bus_prot bp_table[MAX_STEPS];
> >>>>> };
> >>>>> @@ -108,6 +112,7 @@ struct scp_domain {
> >>>>> struct generic_pm_domain genpd;
> >>>>> struct scp *scp;
> >>>>> struct clk *clk[MAX_CLKS];
> >>>>> + struct clk *subsys_clk[MAX_SUBSYS_CLKS];
> >>>>> const struct scp_domain_data *data;
> >>>>> struct regulator *supply;
> >>>>> };
> >>>>> @@ -301,16 +306,22 @@ static int scpsys_power_on(struct generic_pm_domain *genpd)
> >>>>> val |= PWR_RST_B_BIT;
> >>>>> writel(val, ctl_addr);
> >>>>>
> >>>>> - ret = scpsys_sram_enable(scpd, ctl_addr);
> >>>>> + ret = scpsys_clk_enable(scpd->subsys_clk, MAX_SUBSYS_CLKS);
> >>>>
> >>>> Why can't we enable the subsystem clocks together with the rest just after
> >>>> enabeling the regulator?
> >>>>
> >>>
> >>> Subsys CG could only be enabled when its own power domain is already
> >>> turned ON, and vice versa.
> >>> In the dt-binding doc we mentioned there would have two groups of
> >>> clocks.
> >>> e.g.,
> >>> BASIC clocks need to be enabled before enabling the corresponding power
> >>> domain.
> >>> SUBSYS clocks need to be enabled before releasing the bus protection.
> >>>
> >>
> >> Do I understand correctly that we could enable/disable all clocks in the same
> >> place as long as we make sure that the the basic clocks are turned on before we
> >> turn on the subsys clocks, correct?
> >>
> >
> > simply, yes
> >
> >> So why do we need to implement this logic in the power-controller driver?
> >> Shouldn't that be part of the common clock driver?
> >>
> >
> > we implement the subsys clock logic here just due to we already
> > implement the bus protection flow in the power-controller driver.
>
> I think in this driver is the correct place to implement bus protection flow.
>
> > And If we don't enable the subsys clocks, bus protection cannot work.
> > Hence, even the subsys power is on but the HW modules under this subsys
> > power cannot access the bus though.
>
> Ok, I understand that. But I understand that this should be fixed in the clock
> driver. It seems the clock driver does not reflect the correct clock tree.
> For example:
> clocks CLK_MM_SMI_COMMON, CLK_MM_SMI_LARB0, CLK_MM_SMI_LARB1, CLK_MM_GALS_COMM0,
> CLK_MM_GALS_COMM1, CLK_MM_GALS_CCU2MM, CLK_MM_GALS_IPU12MM, CLK_MM_GALS_IMG2MM,
> CLK_MM_GALS_CAM2MM, CLK_MM_GALS_IPU2MM need the CLK_TOP_MUX_MM to be enabled
> first. So I suppose CLK_TOP_MUX_MM is the parent clock of the other CLK_MM_*
> clocks. If the clock tree is correctly described in the clock driver, then the
> common clock framework will take care to enable CLK_TOP_MUX_MM when you try to
> enable an CLK_MM_* clocks.
>
> Why does that not work on mt8183? My impression after a quick look into the
> clock driver is, that this should work.
>
In fact, subsys clock registers could be controlled only when its power
domain is turned on.
So in the series[1] below, we are trying to associate the mfg subsys
clock with mfg power domain.
[1] https://patchwork.kernel.org/cover/11126157/
In other words, a complete flow when we enable a subsys clock for a
subsys H/W engine would be like following steps,
1. enable basic clocks that power domain depends on
2. enable power domain
3. enable subsys clocks that needed during bus protection process
4. release the bus protection
5. enable the target subsys engine clocks
For the mmsys, I guess we might be able to apply such change but there
is a little problem need to be solved first.
1. power controller wants to get the subsys clocks in register function
while driver probes, but it fails.
2. clock controller associates with the power domain while driver probes
and it fails too.
In the end, both power and clock controller cannot register
successfully.
But maybe just register the mmsys clocks earlier in module
initialization stage, but to associate with mm power domain during probe
would be a simple solution.
Back to your first question in this discussion, why do we need to
implement this logic in the power-controller driver?
I was thinking these subsys clock control flow should be coupled with
bus protection control.
What do you think?
> Regards,
> Matthias
>
> >
> >> Regards,
> >> Matthias
> >>
> >>>>> if (ret < 0)
> >>>>> goto err_pwr_ack;
> >>>>>
> >>>>> + ret = scpsys_sram_enable(scpd, ctl_addr);
> >>>>> + if (ret < 0)
> >>>>> + goto err_sram;
> >>>>> +
> >>>>> ret = scpsys_bus_protect_disable(scpd);
> >>>>> if (ret < 0)
> >>>>> - goto err_pwr_ack;
> >>>>> + goto err_sram;
> >>>>>
> >>>>> return 0;
> >>>>>
> >>>>> +err_sram:
> >>>>> + scpsys_clk_disable(scpd->subsys_clk, MAX_SUBSYS_CLKS);
> >>>>> err_pwr_ack:
> >>>>> scpsys_clk_disable(scpd->clk, MAX_CLKS);
> >>>>> err_clk:
> >>>>> @@ -337,6 +348,8 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
> >>>>> if (ret < 0)
> >>>>> goto out;
> >>>>>
> >>>>> + scpsys_clk_disable(scpd->subsys_clk, MAX_SUBSYS_CLKS);
> >>>>> +
> >>>>
> >>>> Same here, why can't we disable the clocks in the scpsys_clk_disable call?
> >>>>
> >>>>> /* subsys power off */
> >>>>> val = readl(ctl_addr);
> >>>>> val |= PWR_ISO_BIT;
> >>>>> @@ -374,6 +387,48 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
> >>>>> return ret;
> >>>>> }
> >>>>>
> >>>>> +static int init_subsys_clks(struct platform_device *pdev,
> >>>>> + const char *prefix, struct clk **clk)
> >>>>> +{
> >>>>> + struct device_node *node = pdev->dev.of_node;
> >>>>> + u32 prefix_len, sub_clk_cnt = 0;
> >>>>> + struct property *prop;
> >>>>> + const char *clk_name;
> >>>>> +
> >>>>> + if (!node) {
> >>>>> + dev_err(&pdev->dev, "Cannot find scpsys node: %ld\n",
> >>>>> + PTR_ERR(node));
> >>>>> + return PTR_ERR(node);
> >>>>> + }
> >>>>> +
> >>>>> + prefix_len = strlen(prefix);
> >>>>> +
> >>>>> + of_property_for_each_string(node, "clock-names", prop, clk_name) {
> >>>>> + if (!strncmp(clk_name, prefix, prefix_len) &&
> >>>>> + (clk_name[prefix_len] == '-')) {
> >>>>> + if (sub_clk_cnt >= MAX_SUBSYS_CLKS) {
> >>>>> + dev_err(&pdev->dev,
> >>>>> + "subsys clk out of range %d\n",
> >>>>> + sub_clk_cnt);
> >>>>> + return -ENOMEM;
> >>>>
> >>>> EINVAL maybe, ENOMEM seems wrong here.
> >>>>
> >>>
> >>> OK, I'll fix with correct error.
> >>>
> >>>>> + }
> >>>>> +
> >>>>> + clk[sub_clk_cnt] = devm_clk_get(&pdev->dev,
> >>>>> + clk_name);
> >>>>
> >>>> Here we get hit by the bad design of this driver in the first place. As we need
> >>>> the subsystem-name (eg mm-0, mm-1) to group clocks to one scp_domain.
> >>>> I think we should better try to model the domains and subdomains in DTS and add
> >>>> their clocks to it. This way we can also get rid of the scp_subdomain which can
> >>>> hit it's limit anytime soon when we have a chip with a sub-subdomain.
> >>>> That will need a new driver, but as it seems the mt8183 and the mt6765 have a
> >>>> more complex design I think it is worth it.
> >>>>
> >>>> That said, given that you are in v11 already I understand that your motivation
> >>>> to start over isn't the biggest. The problem is, any new driver will have new
> >>>> bindings and won't work with older DTS. So adding a lot of stuff on top of a not
> >>>> really nice driver isn't something I'm very keen on. On the other hand you
> >>>> already put a lot of work into this solution.
> >>>>
> >>>> My proposal, I'll try to bake up a new driver this week. If I fail to deliver,
> >>>> it's up to you to decide if you want to go on with the approach in this series
> >>>> or try to work on the new one.
> >>>
> >>>> Regards,
> >>>> Matthias
> >>>>
> >>>
> >>> Thanks for considering our request.
> >>>
> >>>>> +
> >>>>> + if (IS_ERR(clk[sub_clk_cnt])) {
> >>>>> + dev_err(&pdev->dev,
> >>>>> + "Subsys clk get fail %ld\n",
> >>>>> + PTR_ERR(clk[sub_clk_cnt]));
> >>>>> + return PTR_ERR(clk[sub_clk_cnt]);
> >>>>> + }
> >>>>> + sub_clk_cnt++;
> >>>>> + }
> >>>>> + }
> >>>>> +
> >>>>> + return sub_clk_cnt;
> >>>>> +}
> >>>>> +
> >>>>> static int init_basic_clks(struct platform_device *pdev, struct clk **clk,
> >>>>> const char * const *name)
> >>>>> {
> >>>>> @@ -466,6 +521,7 @@ static struct scp *init_scp(struct platform_device *pdev,
> >>>>> struct scp_domain *scpd = &scp->domains[i];
> >>>>> struct generic_pm_domain *genpd = &scpd->genpd;
> >>>>> const struct scp_domain_data *data = &scp_domain_data[i];
> >>>>> + int clk_cnt;
> >>>>
> >>>> clk_cnt sounds to me like clock count, but the variable actually is only used to
> >>>> check the return value of init_subsys_clks. Please rename it to ret or something
> >>>> like this.
> >>>>
> >>>
> >>> OK, I'll fix it.
> >>>
> >>>>>
> >>>>> pd_data->domains[i] = genpd;
> >>>>> scpd->scp = scp;
> >>>>> @@ -476,6 +532,18 @@ static struct scp *init_scp(struct platform_device *pdev,
> >>>>> if (ret)
> >>>>> return ERR_PTR(ret);
> >>>>>
> >>>>> + if (data->subsys_clk_prefix) {
> >>>>> + clk_cnt = init_subsys_clks(pdev,
> >>>>> + data->subsys_clk_prefix,
> >>>>> + scpd->subsys_clk);
> >>>>> + if (clk_cnt < 0) {
> >>>>> + dev_err(&pdev->dev,
> >>>>> + "%s: subsys clk unavailable\n",
> >>>>> + data->name);
> >>>>> + return ERR_PTR(clk_cnt);
> >>>>> + }
> >>>>> + }
> >>>>> +
> >>>>> genpd->name = data->name;
> >>>>> genpd->power_off = scpsys_power_off;
> >>>>> genpd->power_on = scpsys_power_on;
> >>>>>
> >>>
> >>
> >> _______________________________________________
> >> Linux-mediatek mailing list
> >> Linux-mediatek@lists.infradead.org
> >> http://lists.infradead.org/mailman/listinfo/linux-mediatek
> >
>
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v11 06/10] soc: mediatek: Add subsys clock control for bus protection
2020-02-13 12:56 ` Matthias Brugger
2020-02-14 6:33 ` Weiyi Lu
@ 2020-02-14 6:42 ` Weiyi Lu
1 sibling, 0 replies; 33+ messages in thread
From: Weiyi Lu @ 2020-02-14 6:42 UTC (permalink / raw)
To: Matthias Brugger
Cc: Rob Herring, Nicolas Boichat, srv_heupstream, James Liao,
linux-kernel, Fan Chen, linux-mediatek, Sascha Hauer,
linux-arm-kernel
On Thu, 2020-02-13 at 13:56 +0100, Matthias Brugger wrote:
>
> On 13/02/2020 03:46, Weiyi Lu wrote:
> > On Wed, 2020-02-12 at 12:02 +0100, Matthias Brugger wrote:
> >>
> >> On 12/02/2020 03:55, Weiyi Lu wrote:
> >>> On Tue, 2020-02-11 at 18:54 +0100, Matthias Brugger wrote:
> >>>>
> >>>> On 20/12/2019 04:46, Weiyi Lu wrote:
> >>>>> Add subsys CG control flow before/after the bus protect control
> >>>>> due to bus protection need SMI bus relative CGs enabled to feedback
> >>>>> its ack.
> >>>>>
> >>>>
> >>>> Sorry, I don't understand the commit message. Can you please rephrase and
> >>>> explain better what this change is for.
> >>>>
> >>>
> >>> OK! I'll reword it.
> >>>
> >>>>> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> >>>>> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
> >>>>> ---
> >>>>> drivers/soc/mediatek/mtk-scpsys.c | 72 +++++++++++++++++++++++++++++++++++++--
> >>>>> 1 file changed, 70 insertions(+), 2 deletions(-)
> >>>>>
> >>>>> diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
> >>>>> index 763ca58..32be4b3 100644
> >>>>> --- a/drivers/soc/mediatek/mtk-scpsys.c
> >>>>> +++ b/drivers/soc/mediatek/mtk-scpsys.c
> >>>>> @@ -79,6 +79,7 @@
> >>>>> #define PWR_STATUS_WB BIT(27) /* MT7622 */
> >>>>>
> >>>>> #define MAX_CLKS 3
> >>>>> +#define MAX_SUBSYS_CLKS 10
> >>>>>
> >>>>> /**
> >>>>> * struct scp_domain_data - scp domain data for power on/off flow
> >>>>> @@ -88,6 +89,8 @@
> >>>>> * @sram_pdn_bits: The mask for sram power control bits.
> >>>>> * @sram_pdn_ack_bits: The mask for sram power control acked bits.
> >>>>> * @basic_clk_name: The basic clocks required by this power domain.
> >>>>> + * @subsys_clk_prefix: The prefix name of the clocks need to be enabled
> >>>>> + * before releasing bus protection.
> >>>>> * @caps: The flag for active wake-up action.
> >>>>> * @bp_table: The mask table for multiple step bus protection.
> >>>>> */
> >>>>> @@ -98,6 +101,7 @@ struct scp_domain_data {
> >>>>> u32 sram_pdn_bits;
> >>>>> u32 sram_pdn_ack_bits;
> >>>>> const char *basic_clk_name[MAX_CLKS];
> >>>>> + const char *subsys_clk_prefix;
> >>>>> u8 caps;
> >>>>> struct bus_prot bp_table[MAX_STEPS];
> >>>>> };
> >>>>> @@ -108,6 +112,7 @@ struct scp_domain {
> >>>>> struct generic_pm_domain genpd;
> >>>>> struct scp *scp;
> >>>>> struct clk *clk[MAX_CLKS];
> >>>>> + struct clk *subsys_clk[MAX_SUBSYS_CLKS];
> >>>>> const struct scp_domain_data *data;
> >>>>> struct regulator *supply;
> >>>>> };
> >>>>> @@ -301,16 +306,22 @@ static int scpsys_power_on(struct generic_pm_domain *genpd)
> >>>>> val |= PWR_RST_B_BIT;
> >>>>> writel(val, ctl_addr);
> >>>>>
> >>>>> - ret = scpsys_sram_enable(scpd, ctl_addr);
> >>>>> + ret = scpsys_clk_enable(scpd->subsys_clk, MAX_SUBSYS_CLKS);
> >>>>
> >>>> Why can't we enable the subsystem clocks together with the rest just after
> >>>> enabeling the regulator?
> >>>>
> >>>
> >>> Subsys CG could only be enabled when its own power domain is already
> >>> turned ON, and vice versa.
> >>> In the dt-binding doc we mentioned there would have two groups of
> >>> clocks.
> >>> e.g.,
> >>> BASIC clocks need to be enabled before enabling the corresponding power
> >>> domain.
> >>> SUBSYS clocks need to be enabled before releasing the bus protection.
> >>>
> >>
> >> Do I understand correctly that we could enable/disable all clocks in the same
> >> place as long as we make sure that the the basic clocks are turned on before we
> >> turn on the subsys clocks, correct?
> >>
> >
> > simply, yes
> >
> >> So why do we need to implement this logic in the power-controller driver?
> >> Shouldn't that be part of the common clock driver?
> >>
> >
> > we implement the subsys clock logic here just due to we already
> > implement the bus protection flow in the power-controller driver.
>
> I think in this driver is the correct place to implement bus protection flow.
>
> > And If we don't enable the subsys clocks, bus protection cannot work.
> > Hence, even the subsys power is on but the HW modules under this subsys
> > power cannot access the bus though.
>
> Ok, I understand that. But I understand that this should be fixed in the clock
> driver. It seems the clock driver does not reflect the correct clock tree.
> For example:
> clocks CLK_MM_SMI_COMMON, CLK_MM_SMI_LARB0, CLK_MM_SMI_LARB1, CLK_MM_GALS_COMM0,
> CLK_MM_GALS_COMM1, CLK_MM_GALS_CCU2MM, CLK_MM_GALS_IPU12MM, CLK_MM_GALS_IMG2MM,
> CLK_MM_GALS_CAM2MM, CLK_MM_GALS_IPU2MM need the CLK_TOP_MUX_MM to be enabled
> first. So I suppose CLK_TOP_MUX_MM is the parent clock of the other CLK_MM_*
> clocks. If the clock tree is correctly described in the clock driver, then the
> common clock framework will take care to enable CLK_TOP_MUX_MM when you try to
> enable an CLK_MM_* clocks.
>
> Why does that not work on mt8183? My impression after a quick look into the
> clock driver is, that this should work.
>
(resend due to the mail server return error...)
In fact, subsys clock registers could be controlled only when its power
domain is turned on.
So in the series[1] below, we are trying to associate the mfg subsys
clock with mfg power domain.
[1] https://patchwork.kernel.org/cover/11126157/
In other words, a complete flow when we enable a subsys clock for a
subsys H/W engine would be like following steps,
1. enable basic clocks that power domain depends on
2. enable power domain
3. enable subsys clocks that needed during bus protection process
4. release the bus protection
5. enable the target subsys engine clocks
For the mmsys, I guess we might be able to apply such change but there
is a little problem need to be solved first.
1. power controller wants to get the subsys clocks in register function
while driver probes, but it fails.
2. clock controller associates with the power domain while driver probes
and it fails too.
In the end, both power and clock controller cannot register
successfully.
But maybe just register the mmsys clocks earlier in module
initialization stage, but to associate with mm power domain during probe
would be a simple solution.
Back to your first question in this discussion, why do we need to
implement this logic in the power-controller driver?
I was thinking these subsys clock control flow should be coupled with
bus protection control.
What do you think?
> Regards,
> Matthias
>
> >
> >> Regards,
> >> Matthias
> >>
> >>>>> if (ret < 0)
> >>>>> goto err_pwr_ack;
> >>>>>
> >>>>> + ret = scpsys_sram_enable(scpd, ctl_addr);
> >>>>> + if (ret < 0)
> >>>>> + goto err_sram;
> >>>>> +
> >>>>> ret = scpsys_bus_protect_disable(scpd);
> >>>>> if (ret < 0)
> >>>>> - goto err_pwr_ack;
> >>>>> + goto err_sram;
> >>>>>
> >>>>> return 0;
> >>>>>
> >>>>> +err_sram:
> >>>>> + scpsys_clk_disable(scpd->subsys_clk, MAX_SUBSYS_CLKS);
> >>>>> err_pwr_ack:
> >>>>> scpsys_clk_disable(scpd->clk, MAX_CLKS);
> >>>>> err_clk:
> >>>>> @@ -337,6 +348,8 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
> >>>>> if (ret < 0)
> >>>>> goto out;
> >>>>>
> >>>>> + scpsys_clk_disable(scpd->subsys_clk, MAX_SUBSYS_CLKS);
> >>>>> +
> >>>>
> >>>> Same here, why can't we disable the clocks in the scpsys_clk_disable call?
> >>>>
> >>>>> /* subsys power off */
> >>>>> val = readl(ctl_addr);
> >>>>> val |= PWR_ISO_BIT;
> >>>>> @@ -374,6 +387,48 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
> >>>>> return ret;
> >>>>> }
> >>>>>
> >>>>> +static int init_subsys_clks(struct platform_device *pdev,
> >>>>> + const char *prefix, struct clk **clk)
> >>>>> +{
> >>>>> + struct device_node *node = pdev->dev.of_node;
> >>>>> + u32 prefix_len, sub_clk_cnt = 0;
> >>>>> + struct property *prop;
> >>>>> + const char *clk_name;
> >>>>> +
> >>>>> + if (!node) {
> >>>>> + dev_err(&pdev->dev, "Cannot find scpsys node: %ld\n",
> >>>>> + PTR_ERR(node));
> >>>>> + return PTR_ERR(node);
> >>>>> + }
> >>>>> +
> >>>>> + prefix_len = strlen(prefix);
> >>>>> +
> >>>>> + of_property_for_each_string(node, "clock-names", prop, clk_name) {
> >>>>> + if (!strncmp(clk_name, prefix, prefix_len) &&
> >>>>> + (clk_name[prefix_len] == '-')) {
> >>>>> + if (sub_clk_cnt >= MAX_SUBSYS_CLKS) {
> >>>>> + dev_err(&pdev->dev,
> >>>>> + "subsys clk out of range %d\n",
> >>>>> + sub_clk_cnt);
> >>>>> + return -ENOMEM;
> >>>>
> >>>> EINVAL maybe, ENOMEM seems wrong here.
> >>>>
> >>>
> >>> OK, I'll fix with correct error.
> >>>
> >>>>> + }
> >>>>> +
> >>>>> + clk[sub_clk_cnt] = devm_clk_get(&pdev->dev,
> >>>>> + clk_name);
> >>>>
> >>>> Here we get hit by the bad design of this driver in the first place. As we need
> >>>> the subsystem-name (eg mm-0, mm-1) to group clocks to one scp_domain.
> >>>> I think we should better try to model the domains and subdomains in DTS and add
> >>>> their clocks to it. This way we can also get rid of the scp_subdomain which can
> >>>> hit it's limit anytime soon when we have a chip with a sub-subdomain.
> >>>> That will need a new driver, but as it seems the mt8183 and the mt6765 have a
> >>>> more complex design I think it is worth it.
> >>>>
> >>>> That said, given that you are in v11 already I understand that your motivation
> >>>> to start over isn't the biggest. The problem is, any new driver will have new
> >>>> bindings and won't work with older DTS. So adding a lot of stuff on top of a not
> >>>> really nice driver isn't something I'm very keen on. On the other hand you
> >>>> already put a lot of work into this solution.
> >>>>
> >>>> My proposal, I'll try to bake up a new driver this week. If I fail to deliver,
> >>>> it's up to you to decide if you want to go on with the approach in this series
> >>>> or try to work on the new one.
> >>>
> >>>> Regards,
> >>>> Matthias
> >>>>
> >>>
> >>> Thanks for considering our request.
> >>>
> >>>>> +
> >>>>> + if (IS_ERR(clk[sub_clk_cnt])) {
> >>>>> + dev_err(&pdev->dev,
> >>>>> + "Subsys clk get fail %ld\n",
> >>>>> + PTR_ERR(clk[sub_clk_cnt]));
> >>>>> + return PTR_ERR(clk[sub_clk_cnt]);
> >>>>> + }
> >>>>> + sub_clk_cnt++;
> >>>>> + }
> >>>>> + }
> >>>>> +
> >>>>> + return sub_clk_cnt;
> >>>>> +}
> >>>>> +
> >>>>> static int init_basic_clks(struct platform_device *pdev, struct clk **clk,
> >>>>> const char * const *name)
> >>>>> {
> >>>>> @@ -466,6 +521,7 @@ static struct scp *init_scp(struct platform_device *pdev,
> >>>>> struct scp_domain *scpd = &scp->domains[i];
> >>>>> struct generic_pm_domain *genpd = &scpd->genpd;
> >>>>> const struct scp_domain_data *data = &scp_domain_data[i];
> >>>>> + int clk_cnt;
> >>>>
> >>>> clk_cnt sounds to me like clock count, but the variable actually is only used to
> >>>> check the return value of init_subsys_clks. Please rename it to ret or something
> >>>> like this.
> >>>>
> >>>
> >>> OK, I'll fix it.
> >>>
> >>>>>
> >>>>> pd_data->domains[i] = genpd;
> >>>>> scpd->scp = scp;
> >>>>> @@ -476,6 +532,18 @@ static struct scp *init_scp(struct platform_device *pdev,
> >>>>> if (ret)
> >>>>> return ERR_PTR(ret);
> >>>>>
> >>>>> + if (data->subsys_clk_prefix) {
> >>>>> + clk_cnt = init_subsys_clks(pdev,
> >>>>> + data->subsys_clk_prefix,
> >>>>> + scpd->subsys_clk);
> >>>>> + if (clk_cnt < 0) {
> >>>>> + dev_err(&pdev->dev,
> >>>>> + "%s: subsys clk unavailable\n",
> >>>>> + data->name);
> >>>>> + return ERR_PTR(clk_cnt);
> >>>>> + }
> >>>>> + }
> >>>>> +
> >>>>> genpd->name = data->name;
> >>>>> genpd->power_off = scpsys_power_off;
> >>>>> genpd->power_on = scpsys_power_on;
> >>>>>
> >>>
> >>
> >> _______________________________________________
> >> Linux-mediatek mailing list
> >> Linux-mediatek@lists.infradead.org
> >> http://lists.infradead.org/mailman/listinfo/linux-mediatek
> >
>
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 33+ messages in thread
end of thread, other threads:[~2020-02-14 6:43 UTC | newest]
Thread overview: 33+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-12-20 3:45 [PATCH v11 00/10] Mediatek MT8183 scpsys support Weiyi Lu
2019-12-20 3:45 ` [PATCH v11 01/10] dt-bindings: mediatek: Add property to mt8183 smi-common Weiyi Lu
2020-01-15 5:45 ` Weiyi Lu
2019-12-20 3:45 ` [PATCH v11 02/10] dt-bindings: soc: Add MT8183 power dt-bindings Weiyi Lu
2019-12-20 3:45 ` [PATCH v11 03/10] soc: mediatek: Add basic_clk_name to scp_power_data Weiyi Lu
2019-12-20 4:05 ` Nicolas Boichat
2019-12-20 3:45 ` [PATCH v11 04/10] soc: mediatek: Add multiple step bus protection control Weiyi Lu
2019-12-20 4:09 ` Nicolas Boichat
2020-02-11 17:49 ` Matthias Brugger
2020-02-12 2:55 ` Weiyi Lu
2020-02-12 9:23 ` Matthias Brugger
2020-02-13 2:15 ` Weiyi Lu
2020-02-13 11:11 ` Matthias Brugger
2019-12-20 3:45 ` [PATCH v11 05/10] soc: mediatek: Remove infracfg misc driver support Weiyi Lu
2019-12-20 4:11 ` Nicolas Boichat
2019-12-20 5:00 ` Weiyi Lu
2019-12-20 5:09 ` Nicolas Boichat
2019-12-20 3:46 ` [PATCH v11 06/10] soc: mediatek: Add subsys clock control for bus protection Weiyi Lu
2020-02-11 17:54 ` Matthias Brugger
2020-02-12 2:55 ` Weiyi Lu
2020-02-12 11:02 ` Matthias Brugger
2020-02-13 2:46 ` Weiyi Lu
2020-02-13 12:56 ` Matthias Brugger
2020-02-14 6:33 ` Weiyi Lu
2020-02-14 6:42 ` Weiyi Lu
2019-12-20 3:46 ` [PATCH v11 07/10] soc: mediatek: Add extra sram control Weiyi Lu
2020-02-11 17:04 ` Matthias Brugger
2020-02-12 2:56 ` Weiyi Lu
2019-12-20 3:46 ` [PATCH v11 08/10] soc: mediatek: Add MT8183 scpsys support Weiyi Lu
2019-12-20 5:11 ` Nicolas Boichat
2019-12-20 3:46 ` [PATCH v11 09/10] arm64: dts: Add power controller device node of MT8183 Weiyi Lu
2019-12-20 3:46 ` [PATCH v11 10/10] arm64: dts: Add power-domains properity to mfgcfg Weiyi Lu
2019-12-27 1:43 ` [PATCH v11 00/10] Mediatek MT8183 scpsys support Weiyi Lu
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