Re: [PATCH v6 2/3] dt-bindings: edac: nuvoton: add NPCM memory controller

From: Paul Menzel <pmenzel@molgen.mpg.de>
To: Medad CChien <medadyoung@gmail.com>
Cc: rric@kernel.org, james.morse@arm.com, tony.luck@intel.com,
	mchehab@kernel.org, bp@alien8.de, robh+dt@kernel.org,
	benjaminfair@google.com, yuenn@google.com, venture@google.com,
	KWLIU@nuvoton.com, YSCHU@nuvoton.com, JJLIU0@nuvoton.com,
	KFTING@nuvoton.com, avifishman70@gmail.com, tmaimon77@gmail.com,
	tali.perry1@gmail.com, ctcchien@nuvoton.com,
	devicetree@vger.kernel.org, openbmc@lists.ozlabs.org,
	linux-kernel@vger.kernel.org, linux-edac@vger.kernel.org
Subject: Re: [PATCH v6 2/3] dt-bindings: edac: nuvoton: add NPCM memory controller
Date: Sat, 9 Apr 2022 08:12:03 +0200	[thread overview]
Message-ID: <9cf20395-369a-2738-608d-dd5f1aabe48b@molgen.mpg.de> (raw)
In-Reply-To: <20220322030152.19018-3-ctcchien@nuvoton.com>

Dear Medad,

Thank you for your patch.

Am 22.03.22 um 04:01 schrieb Medad CChien:
> Added device tree binding documentation for Nuvoton BMC
> NPCM memory controller.

Please use present tense, and spell *devicetree* without a space. The 
line below even fits in 75 characters:

Document devicetree bindings for the Nuvoton BMC NPCM memory controller.

> Signed-off-by: Medad CChien <ctcchien@nuvoton.com>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
> ---
>   .../edac/nuvoton,npcm-memory-controller.yaml  | 62 +++++++++++++++++++
>   1 file changed, 62 insertions(+)
>   create mode 100644 Documentation/devicetree/bindings/edac/nuvoton,npcm-memory-controller.yaml
> 
> diff --git a/Documentation/devicetree/bindings/edac/nuvoton,npcm-memory-controller.yaml b/Documentation/devicetree/bindings/edac/nuvoton,npcm-memory-controller.yaml
> new file mode 100644
> index 000000000000..97469294f4ba
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/edac/nuvoton,npcm-memory-controller.yaml
> @@ -0,0 +1,62 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/edac/nuvoton,npcm-memory-controller.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Nuvoton NPCM Memory Controller
> +
> +maintainers:
> +  - Medad CChien <ctcchien@nuvoton.com>
> +
> +description: |
> +  The Nuvoton BMC SoC supports DDR4 memory with and without ECC (error
> +  correction check).
> +
> +  The memory controller supports single bit error correction, double bit
> +  error detection (in-line ECC in which a section (1/8th) of the
> +  memory device used to store data is used for ECC storage).

*memory* fits on the line above?

> +
> +  Note, the bootloader must configure ECC mode for the memory controller.
> +
> +properties:
> +  compatible:
> +    enum:
> +      - nuvoton,npcm845-memory-controller
> +      - nuvoton,npcm750-memory-controller

Sort the entries?

Kind regards,

Paul

> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    minItems: 1
> +    items:
> +      - description: uncorrectable error interrupt
> +      - description: correctable error interrupt
> +
> +  interrupt-names:
> +    minItems: 1
> +    items:
> +      - const: ue
> +      - const: ce
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    ahb {
> +        #address-cells = <2>;
> +        #size-cells = <2>;
> +        mc: memory-controller@f0824000 {
> +            compatible = "nuvoton,npcm750-memory-controller";
> +            reg = <0x0 0xf0824000 0x0 0x1000>;
> +            interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
> +        };
> +    };
> +