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Date:   Tue, 19 Apr 2022 15:06:54 +0300
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Subject: Re: [PATCH 0/2] Update register & interrupt info in am65x DSS
Content-Language: en-US
To:     Aradhya Bhatia <a-bhatia1@ti.com>, Jyri Sarha <jyri.sarha@iki.fi>,
        Vignesh Raghavendra <vigneshr@ti.com>,
        Nishanth Menon <nm@ti.com>
Cc:     DRI Development <dri-devel@lists.freedesktop.org>,
        Devicetree <devicetree@vger.kernel.org>,
        Linux ARM Kernel <linux-arm-kernel@lists.infradead.org>,
        Linux Kernel <linux-kernel@vger.kernel.org>,
        Nikhil Devshatwar <nikhil.nd@ti.com>
References: <20220419070302.16502-1-a-bhatia1@ti.com>
From:   Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
In-Reply-To: <20220419070302.16502-1-a-bhatia1@ti.com>
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On 19/04/2022 10:03, Aradhya Bhatia wrote:
> The Display SubSystem IP on the ti's am65x soc has an additional
> register space "common1" and services a maximum of 2 interrupts.
> 
> The first patch in the series adds the required updates to the yaml
> file. The second patch then reflects the yaml updates in the DSS DT
> node of am65x soc.
> 
> Aradhya Bhatia (2):
>    dt-bindings: display: ti,am65x-dss: Add missing register & interrupt
>    arm64: dts: ti: k3-am65: Add missing register & interrupt in DSS node
> 
>   .../devicetree/bindings/display/ti/ti,am65x-dss.yaml   | 10 +++++++---
>   arch/arm64/boot/dts/ti/k3-am65-main.dtsi               |  6 ++++--
>   2 files changed, 11 insertions(+), 5 deletions(-)
> 

Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>

How are you planning to use the common1 area?

  Tomi