From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S942531AbcJ0PAc (ORCPT ); Thu, 27 Oct 2016 11:00:32 -0400 Received: from smtp.ctxuk.citrix.com ([185.25.65.24]:50710 "EHLO SMTP.EU.CITRIX.COM" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932442AbcJ0PAb (ORCPT ); Thu, 27 Oct 2016 11:00:31 -0400 X-IronPort-AV: E=Sophos;i="5.31,553,1473120000"; d="scan'208";a="33843920" Subject: Re: [Xen-devel] [PATCH 8/8] xen/pvh: Enable CPU hotplug To: Boris Ostrovsky , , References: <1476468318-24422-1-git-send-email-boris.ostrovsky@oracle.com> <1476468318-24422-9-git-send-email-boris.ostrovsky@oracle.com> <846901a2-06c1-931f-9933-bda4696e2e40@oracle.com> CC: , , , Jan Beulich From: Andrew Cooper Message-ID: <9e8a05ce-851f-ed9e-c5af-ad9cc84876a1@citrix.com> Date: Thu, 27 Oct 2016 16:00:26 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Icedove/45.4.0 MIME-Version: 1.0 In-Reply-To: <846901a2-06c1-931f-9933-bda4696e2e40@oracle.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: AMSPEX02CAS01.citrite.net (10.69.22.112) To AMSPEX02CL02.citrite.net (10.69.22.126) X-DLP: AMS1 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 27/10/16 15:25, Boris Ostrovsky wrote: > > > On 10/14/2016 03:01 PM, Boris Ostrovsky wrote: >> On 10/14/2016 02:41 PM, Andrew Cooper wrote: >>> On 14/10/16 19:05, Boris Ostrovsky wrote: >>>> PVH guests don't receive ACPI hotplug interrupts and therefore >>>> need to monitor xenstore for CPU hotplug event. >>> Why not? If they don't, they should. As we are providing ACPI anyway, >>> we should provide all bits of it. >> >> We don't have IOAPIC, which is how these interrupts are typically >> delivered. I suppose we might be able to specify it as something else. >> >> I'll look into this. > > > (+Jan) > > Yes, we can do this. The main issue is how to deal with event > registers (i.e FADT.x_pm1a_evt_blk) and AML's PRST region (which > specifies online CPU map). > > Currently these are accessed via IO space and are handled by qemu. > > There are a couple of ways to deal with this that I can see. > > 1. We can implement ioreq handling in the hypervisor, there are only a > few addresses that need handling. > > 2. We can implement those registers in memory space and have libxl > update them them on a hotplug command. This appears to be possible > because these registers mostly just consume writes without side > effects so they can be simple memory locations. The one exception is > updating status bits (they are cleared by writing 1s) but I think we > can do this from the AML. > > Other than that the only other thing is setting up an event channel > between the toolstack and the guest (either via xenstore or perhaps by > having a reserved port for SCI). > > I have a prototype with (2) (except for the bit clearing part) but I > want to hear comments on this approach before I write proper patches. Xen already deals with 1 for HVM guests. We should do the same for PVH guests as well. -1 to anything involving looping a PVH dom0 back around to some entity running inside dom0. ~Andrew ~Andrew