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([2601:586:5000:570:28d9:4790:bc16:cc93]) by smtp.gmail.com with ESMTPSA id t18-20020a05622a181200b003a527d29a41sm4311476qtc.75.2022.11.02.09.24.48 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 02 Nov 2022 09:24:48 -0700 (PDT) Message-ID: <9eaaf256-8de2-ddc9-ac95-aed9b0670f5e@linaro.org> Date: Wed, 2 Nov 2022 12:24:47 -0400 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.1 Subject: Re: [PATCH v3 3/4] arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs Content-Language: en-US To: Melody Olvera , Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20221026200429.162212-1-quic_molvera@quicinc.com> <20221026200429.162212-4-quic_molvera@quicinc.com> From: Krzysztof Kozlowski In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 31/10/2022 17:49, Melody Olvera wrote: > > > On 10/27/2022 8:21 AM, Krzysztof Kozlowski wrote: >> On 26/10/2022 16:04, Melody Olvera wrote: >>> Add the base DTSI files for QDU1000 and QRU1000 SoCs, including base >>> descriptions of CPUs, GCC, RPMHCC, QUP, TLMM, and interrupt-controller >>> to boot to shell with console on these SoCs. >>> >>> Signed-off-by: Melody Olvera >>> --- >>> arch/arm64/boot/dts/qcom/qdu1000.dtsi | 1406 +++++++++++++++++++++++++ >> Please use scripts/get_maintainers.pl to get a list of necessary people >> and lists to CC. It might happen, that command when run on an older >> kernel, gives you outdated entries. Therefore please be sure you base >> your patches on recent Linux kernel. > Sure thing; we talked about this on a different patch. >> >>> arch/arm64/boot/dts/qcom/qru1000.dtsi | 27 + >>> 2 files changed, 1433 insertions(+) >>> create mode 100644 arch/arm64/boot/dts/qcom/qdu1000.dtsi >>> create mode 100644 arch/arm64/boot/dts/qcom/qru1000.dtsi >>> >>> diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi >>> new file mode 100644 >>> index 000000000000..76474106e931 >>> --- /dev/null >>> +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi >>> @@ -0,0 +1,1406 @@ >>> +// SPDX-License-Identifier: BSD-3-Clause >>> +/* >>> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. >>> + */ >> (...) >> >>> + >>> + soc: soc@0 { >>> + #address-cells = <2>; >>> + #size-cells = <2>; >>> + ranges = <0 0 0 0 0x10 0>; >>> + dma-ranges = <0 0 0 0 0x10 0>; >>> + compatible = "simple-bus"; >>> + >>> + gcc: clock-controller@80000 { >>> + compatible = "qcom,gcc-qdu1000", "syscon"; >>> + reg = <0x0 0x80000 0x0 0x1f4200>; >>> + #clock-cells = <1>; >>> + #reset-cells = <1>; >>> + #power-domain-cells = <1>; >>> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; >>> + clock-names = "bi_tcxo", "sleep_clk"; >>> + }; >>> + >>> + gpi_dma0: dma-controller@900000 { >>> + compatible = "qcom,sm6350-gpi-dma"; >> You should add here a specific compatible as well. Same in other places. >> All places. I had impression we talked about this few times, so I don't >> know what is missing on your side. >> >> This must be: >> "qcom,qdu1000-gpi-dma", "qcom,sm6350-gpi-dma" > Got it. I talked to Stephan and he said either your suggestion or just using > preexisting compatibles would be ok. I thought it might be cleaner to not > have the qdu compats, but I'm fine either way. >> >>> + #dma-cells = <3>; >>> + reg = <0x0 0x900000 0x0 0x60000>; >>> + interrupts = , >>> + , >>> + , >>> + , >>> + , >>> + , >>> + , >>> + , >>> + , >>> + , >>> + , >>> + ; >>> + dma-channels = <12>; >>> + dma-channel-mask = <0x3f>; >>> + iommus = <&apps_smmu 0xf6 0x0>; >>> + }; >>> + >> (...) >> >> >>> + >>> + tlmm: pinctrl@f000000 { >>> + compatible = "qcom,qdu1000-tlmm"; >>> + reg = <0x0 0xf000000 0x0 0x1000000>; >>> + interrupts = ; >>> + gpio-controller; >>> + #gpio-cells = <2>; >>> + interrupt-controller; >>> + #interrupt-cells = <2>; >>> + gpio-ranges = <&tlmm 0 0 151>; >>> + wakeup-parent = <&pdc>; >>> + >>> + qup_uart0_default: qup-uart0-default-state { >>> + pins = "gpio6", "gpio7", "gpio8", "gpio9"; >>> + function = "qup00"; >>> + }; >>> + >>> + qup_i2c1_data_clk: qup-i2c1-data-clk-state { >>> + pins = "gpio10", "gpio11"; >>> + function = "qup01"; >>> + drive-strength = <2>; >> Can we have some generic agreement where to put drive-strengths and bias? >> >> See also: >> https://lore.kernel.org/linux-devicetree/20221026200357.391635-2-krzysztof.kozlowski@linaro.org/ >> >> https://lore.kernel.org/lkml/CAD=FV=VUL4GmjaibAMhKNdpEso_Hg_R=XeMaqah1LSj_9-Ce4Q@mail.gmail.com/ > Not sure how much two-sense I have for the conversation at large, but generally I agree with Doug's > point in the first paragraph. Pulls for this soc are consistent across boards so I don't think it makes > sense to move them to the board files here. I vote that these stay here. >> I would be great if Konrad and Bjorn shared their opinion on this... but wait, you did not Cc all maintainers... Eh. Best regards, Krzysztof