* [PATCH 0/6] Add support for remoteproc modem-pil on SDM845 SoCs
@ 2018-03-02 9:23 13% sibis
2018-03-02 9:23 15% ` [PATCH 1/6] reset: qcom: AOSS (Always on subsystem) reset controller sibis
` (5 more replies)
0 siblings, 6 replies; 200+ results
From: sibis @ 2018-03-02 9:23 UTC (permalink / raw)
To: bjorn.andersson
Cc: linux-remoteproc, linux-kernel, devicetree, sibis, georgi.djakov,
jassisinghbrar, p.zabel, ohad, mark.rutland, robh+dt, kyan,
sricharan, akdwived, linux-arm-msm
This patch series add support for remoteproc Q6v5 modem-pil on Qualcomm
SDM845 SoC. The first patch adds AOSS (Always on subsystem) reset driver
to provide for mss reset line. The third patch adds the APCS offset for
SDM845. The last couple of patches add the resets sequence for Q6 on
SDM845 and adds helper functions for arbitrary reset assert/deassert
sequences.
sibis (6):
reset: qcom: AOSS (Always on subsystem) reset controller
dt-bindings: mailbox: Add APCS global binding for SDM845 SoCs
mailbox: Add support for Qualcomm SDM845 SoCs
dt-bindings: remoteproc: Add Q6v5 Modem PIL binding for SDM845
remoteproc: qcom: Add support for mss remoteproc on SDM845
remoteproc: qcom: Reorder active clks enable and reset
.../bindings/mailbox/qcom,apcs-kpss-global.txt | 3 +-
.../devicetree/bindings/remoteproc/qcom,q6v5.txt | 5 +-
.../devicetree/bindings/reset/qcom,aoss-reset.txt | 54 +++++++
drivers/mailbox/qcom-apcs-ipc-mailbox.c | 1 +
drivers/remoteproc/qcom_q6v5_pil.c | 149 +++++++++++++++++--
drivers/reset/Kconfig | 10 ++
drivers/reset/Makefile | 1 +
drivers/reset/reset-qcom-aoss.c | 161 +++++++++++++++++++++
include/dt-bindings/reset/qcom,aoss-sdm845.h | 17 +++
9 files changed, 386 insertions(+), 15 deletions(-)
create mode 100644 Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
create mode 100644 drivers/reset/reset-qcom-aoss.c
create mode 100644 include/dt-bindings/reset/qcom,aoss-sdm845.h
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [relevance 13%]
* [PATCH 1/6] reset: qcom: AOSS (Always on subsystem) reset controller
2018-03-02 9:23 13% [PATCH 0/6] Add support for remoteproc modem-pil on SDM845 SoCs sibis
@ 2018-03-02 9:23 15% ` sibis
2018-03-02 10:30 0% ` Philipp Zabel
2018-03-02 9:23 21% ` [PATCH 2/6] dt-bindings: mailbox: Add APCS global binding for SDM845 SoCs sibis
` (4 subsequent siblings)
5 siblings, 1 reply; 200+ results
From: sibis @ 2018-03-02 9:23 UTC (permalink / raw)
To: bjorn.andersson
Cc: linux-remoteproc, linux-kernel, devicetree, sibis, georgi.djakov,
jassisinghbrar, p.zabel, ohad, mark.rutland, robh+dt, kyan,
sricharan, akdwived, linux-arm-msm
Add reset controller driver for Qualcomm SDM845 SoC to
control reset signals provided by AOSS for Modem, Venus
ADSP, GPU, Camera, Wireless, Display subsystem
Signed-off-by: sibis <sibis@codeaurora.org>
---
.../devicetree/bindings/reset/qcom,aoss-reset.txt | 54 +++++++
drivers/reset/Kconfig | 10 ++
drivers/reset/Makefile | 1 +
drivers/reset/reset-qcom-aoss.c | 161 +++++++++++++++++++++
include/dt-bindings/reset/qcom,aoss-sdm845.h | 17 +++
5 files changed, 243 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
create mode 100644 drivers/reset/reset-qcom-aoss.c
create mode 100644 include/dt-bindings/reset/qcom,aoss-sdm845.h
diff --git a/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
new file mode 100644
index 0000000..5318e14
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
@@ -0,0 +1,54 @@
+Qualcomm AOSS Reset Controller
+======================================
+
+This binding describes a reset-controller found on AOSS (Always on SubSysem)
+for Qualcomm SDM845 SoCs.
+
+Required properties:
+- compatible:
+ Usage: required
+ Value type: <string>
+ Definition: must be:
+ "qcom,aoss-reset-sdm845", "syscon"
+
+- reg:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: must specify the base address and size of the
+ syscon device.
+
+
+- #reset-cells:
+ Usage: required
+ Value type: <uint>
+ Definition: must be 1; cell entry represents the reset index.
+
+example:
+
+aoss_reset: qcom,reset-controller@b2e0100 {
+ compatible = "qcom,aoss-reset-sdm845", "syscon";
+ reg = <0xc2b0000 0x20004>;
+ #reset-cells = <1>;
+};
+
+
+Specifying reset lines connected to IP modules
+==============================================
+
+Device nodes that need access to reset lines should
+specify them as a reset phandle in their corresponding node as
+specified in reset.txt.
+
+Example:
+
+ modem-pil@4080000 {
+ ...
+
+ resets = <&aoss_reset AOSS_CC_MSS_RESTART>;
+ reset-names = "mss_restart";
+
+ ...
+ };
+
+For list of all valid reset indicies see
+<dt-bindings/reset/qcom,aoss-sdm845.h>
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 7fc7769..4b1da86 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -81,6 +81,16 @@ config RESET_PISTACHIO
help
This enables the reset driver for ImgTec Pistachio SoCs.
+config RESET_QCOM_AOSS
+ bool "Qcom AOSS Reset Driver"
+ depends on ARCH_QCOM || COMPILE_TEST
+ select MFD_SYSCON
+ help
+ This enables the AOSS (Always On SubSystem) reset driver
+ for Qcom SoCs. Say Y if you want to control reset signals
+ provided by AOSS for Modem, Venus, ADSP, GPU, Camera,
+ Wireless, Display subsystem. Otherwise, say N.
+
config RESET_SIMPLE
bool "Simple Reset Controller Driver" if COMPILE_TEST
default ARCH_SOCFPGA || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 132c24f..c30044a 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
obj-$(CONFIG_RESET_MESON) += reset-meson.o
obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o
+obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o
obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
diff --git a/drivers/reset/reset-qcom-aoss.c b/drivers/reset/reset-qcom-aoss.c
new file mode 100644
index 0000000..eb8c69b
--- /dev/null
+++ b/drivers/reset/reset-qcom-aoss.c
@@ -0,0 +1,161 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+#include <linux/regmap.h>
+#include <linux/of_device.h>
+#include <dt-bindings/reset/qcom,aoss-sdm845.h>
+
+struct qcom_aoss_reset_map {
+ unsigned int reg;
+ u8 bit;
+};
+
+struct qcom_aoss_desc {
+ const struct regmap_config *config;
+ const struct qcom_aoss_reset_map *resets;
+ int delay;
+ size_t num_resets;
+};
+
+struct qcom_aoss_reset_data {
+ struct reset_controller_dev rcdev;
+ struct regmap *regmap;
+ const struct qcom_aoss_desc *desc;
+};
+
+static const struct regmap_config aoss_sdm845_regmap_config = {
+ .name = "aoss-reset",
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x20000,
+ .fast_io = true,
+};
+
+static const struct qcom_aoss_reset_map aoss_sdm845_resets[] = {
+ [AOSS_CC_MSS_RESTART] = { 0x0, 0 },
+ [AOSS_CC_CAMSS_RESTART] = { 0x1000, 0 },
+ [AOSS_CC_VENUS_RESTART] = { 0x2000, 0 },
+ [AOSS_CC_GPU_RESTART] = { 0x3000, 0 },
+ [AOSS_CC_DISPSS_RESTART] = { 0x4000, 0 },
+ [AOSS_CC_WCSS_RESTART] = { 0x10000, 0 },
+ [AOSS_CC_LPASS_RESTART] = { 0x20000, 0 },
+};
+
+static const struct qcom_aoss_desc aoss_sdm845_desc = {
+ .config = &aoss_sdm845_regmap_config,
+ .resets = aoss_sdm845_resets,
+ /* Wait 6 32kHz sleep cycles for reset */
+ .delay = 200,
+ .num_resets = ARRAY_SIZE(aoss_sdm845_resets),
+};
+
+static struct qcom_aoss_reset_data *to_qcom_aoss_reset_data(
+ struct reset_controller_dev *rcdev)
+{
+ return container_of(rcdev, struct qcom_aoss_reset_data, rcdev);
+}
+
+static int qcom_aoss_control_assert(struct reset_controller_dev *rcdev,
+ unsigned long idx)
+{
+ struct qcom_aoss_reset_data *data = to_qcom_aoss_reset_data(rcdev);
+ const struct qcom_aoss_reset_map *map = &data->desc->resets[idx];
+
+ if (idx >= rcdev->nr_resets)
+ return -EINVAL;
+
+ return regmap_update_bits(data->regmap, map->reg,
+ BIT(map->bit), BIT(map->bit));
+}
+
+static int qcom_aoss_control_deassert(struct reset_controller_dev *rcdev,
+ unsigned long idx)
+{
+ struct qcom_aoss_reset_data *data = to_qcom_aoss_reset_data(rcdev);
+ const struct qcom_aoss_reset_map *map = &data->desc->resets[idx];
+
+ if (idx >= rcdev->nr_resets)
+ return -EINVAL;
+
+ return regmap_update_bits(data->regmap, map->reg, BIT(map->bit), 0);
+}
+
+static int qcom_aoss_control_reset(struct reset_controller_dev *rcdev,
+ unsigned long idx)
+{
+ struct qcom_aoss_reset_data *data = to_qcom_aoss_reset_data(rcdev);
+ int ret;
+
+ ret = rcdev->ops->assert(rcdev, idx);
+ if (ret)
+ return ret;
+
+ udelay(data->desc->delay);
+
+ ret = rcdev->ops->deassert(rcdev, idx);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static const struct reset_control_ops qcom_aoss_reset_ops = {
+ .reset = qcom_aoss_control_reset,
+ .assert = qcom_aoss_control_assert,
+ .deassert = qcom_aoss_control_deassert,
+};
+
+static int qcom_aoss_reset_probe(struct platform_device *pdev)
+{
+ struct qcom_aoss_reset_data *data;
+ struct device *dev = &pdev->dev;
+ const struct qcom_aoss_desc *desc;
+
+ desc = of_device_get_match_data(&pdev->dev);
+ if (!desc)
+ return -EINVAL;
+
+ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ data->desc = desc;
+ data->regmap = syscon_node_to_regmap(dev->of_node);
+ if (IS_ERR(data->regmap)) {
+ dev_err(dev, "Unable to get aoss-reset regmap");
+ return PTR_ERR(data->regmap);
+ }
+ regmap_attach_dev(dev, data->regmap, desc->config);
+
+ data->rcdev.owner = THIS_MODULE;
+ data->rcdev.ops = &qcom_aoss_reset_ops;
+ data->rcdev.nr_resets = desc->num_resets;
+ data->rcdev.of_node = pdev->dev.of_node;
+
+ return devm_reset_controller_register(&pdev->dev, &data->rcdev);
+}
+
+static const struct of_device_id qcom_aoss_reset_of_match[] = {
+ { .compatible = "qcom,aoss-reset-sdm845", .data = &aoss_sdm845_desc},
+ {}
+};
+
+static struct platform_driver qcom_aoss_reset_driver = {
+ .probe = qcom_aoss_reset_probe,
+ .driver = {
+ .name = "qcom_aoss_reset",
+ .of_match_table = qcom_aoss_reset_of_match,
+ },
+};
+
+builtin_platform_driver(qcom_aoss_reset_driver);
+
+MODULE_DESCRIPTION("Qualcomm AOSS Reset Driver");
+MODULE_LICENSE("GPL v2");
diff --git a/include/dt-bindings/reset/qcom,aoss-sdm845.h b/include/dt-bindings/reset/qcom,aoss-sdm845.h
new file mode 100644
index 0000000..e9b38fc
--- /dev/null
+++ b/include/dt-bindings/reset/qcom,aoss-sdm845.h
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_RESET_AOSS_SDM_845_H
+#define _DT_BINDINGS_RESET_AOSS_SDM_845_H
+
+#define AOSS_CC_MSS_RESTART 0
+#define AOSS_CC_CAMSS_RESTART 1
+#define AOSS_CC_VENUS_RESTART 2
+#define AOSS_CC_GPU_RESTART 3
+#define AOSS_CC_DISPSS_RESTART 4
+#define AOSS_CC_WCSS_RESTART 5
+#define AOSS_CC_LPASS_RESTART 6
+
+#endif
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 15%]
* [PATCH 2/6] dt-bindings: mailbox: Add APCS global binding for SDM845 SoCs
2018-03-02 9:23 13% [PATCH 0/6] Add support for remoteproc modem-pil on SDM845 SoCs sibis
2018-03-02 9:23 15% ` [PATCH 1/6] reset: qcom: AOSS (Always on subsystem) reset controller sibis
@ 2018-03-02 9:23 21% ` sibis
2018-03-02 9:23 21% ` [PATCH 3/6] mailbox: Add support for Qualcomm " sibis
` (3 subsequent siblings)
5 siblings, 0 replies; 200+ results
From: sibis @ 2018-03-02 9:23 UTC (permalink / raw)
To: bjorn.andersson
Cc: linux-remoteproc, linux-kernel, devicetree, sibis, georgi.djakov,
jassisinghbrar, p.zabel, ohad, mark.rutland, robh+dt, kyan,
sricharan, akdwived, linux-arm-msm
Include SDM845 APCS binding to the list of possible bindings
Signed-off-by: sibis <sibis@codeaurora.org>
---
Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt
index 16964f0..a60d2b2 100644
--- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt
+++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt
@@ -9,7 +9,8 @@ platforms.
Value type: <string>
Definition: must be one of:
"qcom,msm8916-apcs-kpss-global",
- "qcom,msm8996-apcs-hmss-global"
+ "qcom,msm8996-apcs-hmss-global",
+ "qcom,sdm845-apcs-hmss-global"
- reg:
Usage: required
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 21%]
* [PATCH 3/6] mailbox: Add support for Qualcomm SDM845 SoCs
2018-03-02 9:23 13% [PATCH 0/6] Add support for remoteproc modem-pil on SDM845 SoCs sibis
2018-03-02 9:23 15% ` [PATCH 1/6] reset: qcom: AOSS (Always on subsystem) reset controller sibis
2018-03-02 9:23 21% ` [PATCH 2/6] dt-bindings: mailbox: Add APCS global binding for SDM845 SoCs sibis
@ 2018-03-02 9:23 21% ` sibis
2018-03-02 9:23 21% ` [PATCH 4/6] dt-bindings: remoteproc: Add Q6v5 Modem PIL binding for SDM845 sibis
` (2 subsequent siblings)
5 siblings, 0 replies; 200+ results
From: sibis @ 2018-03-02 9:23 UTC (permalink / raw)
To: bjorn.andersson
Cc: linux-remoteproc, linux-kernel, devicetree, sibis, georgi.djakov,
jassisinghbrar, p.zabel, ohad, mark.rutland, robh+dt, kyan,
sricharan, akdwived, linux-arm-msm
Add the corresponding APCS offset for SDM845 SoC
Signed-off-by: sibis <sibis@codeaurora.org>
---
drivers/mailbox/qcom-apcs-ipc-mailbox.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
index 57bde0d..62d704d 100644
--- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c
+++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
@@ -125,6 +125,7 @@ static int qcom_apcs_ipc_remove(struct platform_device *pdev)
static const struct of_device_id qcom_apcs_ipc_of_match[] = {
{ .compatible = "qcom,msm8916-apcs-kpss-global", .data = (void *)8 },
{ .compatible = "qcom,msm8996-apcs-hmss-global", .data = (void *)16 },
+ { .compatible = "qcom,sdm845-apcs-hmss-global", .data = (void *)12 },
{}
};
MODULE_DEVICE_TABLE(of, qcom_apcs_ipc_of_match);
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 21%]
* [PATCH 4/6] dt-bindings: remoteproc: Add Q6v5 Modem PIL binding for SDM845
2018-03-02 9:23 13% [PATCH 0/6] Add support for remoteproc modem-pil on SDM845 SoCs sibis
` (2 preceding siblings ...)
2018-03-02 9:23 21% ` [PATCH 3/6] mailbox: Add support for Qualcomm " sibis
@ 2018-03-02 9:23 21% ` sibis
2018-03-02 9:23 16% ` [PATCH 5/6] remoteproc: qcom: Add support for mss remoteproc on SDM845 sibis
2018-03-02 9:23 20% ` [PATCH 6/6] remoteproc: qcom: Reorder active clks enable and reset sibis
5 siblings, 0 replies; 200+ results
From: sibis @ 2018-03-02 9:23 UTC (permalink / raw)
To: bjorn.andersson
Cc: linux-remoteproc, linux-kernel, devicetree, sibis, georgi.djakov,
jassisinghbrar, p.zabel, ohad, mark.rutland, robh+dt, kyan,
sricharan, akdwived, linux-arm-msm
Add new compatible string for Qualcomm SDM845 SoCs
Signed-off-by: sibis <sibis@codeaurora.org>
---
Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
index 00d3d58..11907db 100644
--- a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
+++ b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
@@ -9,8 +9,9 @@ on the Qualcomm Hexagon core.
Definition: must be one of:
"qcom,q6v5-pil",
"qcom,msm8916-mss-pil",
- "qcom,msm8974-mss-pil"
- "qcom,msm8996-mss-pil"
+ "qcom,msm8974-mss-pil",
+ "qcom,msm8996-mss-pil",
+ "qcom,sdm845-mss-pil"
- reg:
Usage: required
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 21%]
* [PATCH 5/6] remoteproc: qcom: Add support for mss remoteproc on SDM845
2018-03-02 9:23 13% [PATCH 0/6] Add support for remoteproc modem-pil on SDM845 SoCs sibis
` (3 preceding siblings ...)
2018-03-02 9:23 21% ` [PATCH 4/6] dt-bindings: remoteproc: Add Q6v5 Modem PIL binding for SDM845 sibis
@ 2018-03-02 9:23 16% ` sibis
2018-03-02 9:23 20% ` [PATCH 6/6] remoteproc: qcom: Reorder active clks enable and reset sibis
5 siblings, 0 replies; 200+ results
From: sibis @ 2018-03-02 9:23 UTC (permalink / raw)
To: bjorn.andersson
Cc: linux-remoteproc, linux-kernel, devicetree, sibis, georgi.djakov,
jassisinghbrar, p.zabel, ohad, mark.rutland, robh+dt, kyan,
sricharan, akdwived, linux-arm-msm
>From SDM845, the Q6SS reset sequence on software side has been
simplified with the introduction of boot FSM which assists in
bringing the Q6 out of reset
Add GLINK subdevice to allow definition of GLINK edge as a
child of modem-pil
Reset assert/deassert sequence vary across SoCs adding reset
start/stop helper functions to handle SoC specific reset sequences
Signed-off-by: sibis <sibis@codeaurora.org>
---
drivers/remoteproc/qcom_q6v5_pil.c | 134 +++++++++++++++++++++++++++++++++++--
1 file changed, 129 insertions(+), 5 deletions(-)
diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
index b4e5e72..f4997e0 100644
--- a/drivers/remoteproc/qcom_q6v5_pil.c
+++ b/drivers/remoteproc/qcom_q6v5_pil.c
@@ -57,6 +57,8 @@
#define RMB_PMI_META_DATA_REG 0x10
#define RMB_PMI_CODE_START_REG 0x14
#define RMB_PMI_CODE_LENGTH_REG 0x18
+#define RMB_MBA_MSS_STATUS 0x40
+#define RMB_MBA_ALT_RESET 0x44
#define RMB_CMD_META_DATA_READY 0x1
#define RMB_CMD_LOAD_READY 0x2
@@ -104,6 +106,13 @@
#define QDSP6SS_XO_CBCR 0x0038
#define QDSP6SS_ACC_OVERRIDE_VAL 0x20
+/* QDSP6v65 parameters */
+#define QDSP6SS_SLEEP 0x3C
+#define QDSP6SS_BOOT_CORE_START 0x400
+#define QDSP6SS_BOOT_CMD 0x404
+#define SLEEP_CHECK_MAX_LOOPS 200
+#define BOOT_FSM_TIMEOUT 10000
+
struct reg_info {
struct regulator *reg;
int uV;
@@ -126,6 +135,8 @@ struct rproc_hexagon_res {
bool need_mem_protection;
};
+struct q6v5_reset_ops;
+
struct q6v5 {
struct device *dev;
struct rproc *rproc;
@@ -166,6 +177,8 @@ struct q6v5 {
void *mpss_region;
size_t mpss_size;
+ const struct q6v5_reset_ops *ops;
+ struct qcom_rproc_glink glink_subdev;
struct qcom_rproc_subdev smd_subdev;
struct qcom_rproc_ssr ssr_subdev;
bool need_mem_protection;
@@ -174,10 +187,16 @@ struct q6v5 {
int version;
};
+struct q6v5_reset_ops {
+ int (*reset_start)(struct q6v5 *qproc);
+ int (*reset_stop)(struct q6v5 *qproc);
+};
+
enum {
MSS_MSM8916,
MSS_MSM8974,
MSS_MSM8996,
+ MSS_SDM845,
};
static int q6v5_regulator_init(struct device *dev, struct reg_info *regs,
@@ -332,6 +351,52 @@ static int q6v5_load(struct rproc *rproc, const struct firmware *fw)
return 0;
}
+static void alt_reset_restart(struct q6v5 *qproc, u32 restart)
+{
+ writel(restart, qproc->rmb_base + RMB_MBA_ALT_RESET);
+}
+
+static int q6v5_msm_reset_stop(struct q6v5 *qproc)
+{
+ return reset_control_assert(qproc->mss_restart);
+}
+
+static int q6v5_msm_reset_start(struct q6v5 *qproc)
+{
+ return reset_control_deassert(qproc->mss_restart);
+}
+
+static int q6v5_sdm_reset_stop(struct q6v5 *qproc)
+{
+ return reset_control_reset(qproc->mss_restart);
+}
+
+static int q6v5_sdm_reset_start(struct q6v5 *qproc)
+{
+ int ret;
+
+ alt_reset_restart(qproc, 1);
+ /* Ensure alt reset is written before restart reg */
+ udelay(100);
+
+ ret = reset_control_reset(qproc->mss_restart);
+
+ udelay(100);
+ alt_reset_restart(qproc, 0);
+
+ return ret;
+}
+
+static const struct q6v5_reset_ops q6v5_msm_ops = {
+ .reset_stop = q6v5_msm_reset_stop,
+ .reset_start = q6v5_msm_reset_start,
+};
+
+static const struct q6v5_reset_ops q6v5_sdm_ops = {
+ .reset_stop = q6v5_sdm_reset_stop,
+ .reset_start = q6v5_sdm_reset_start,
+};
+
static int q6v5_rmb_pbl_wait(struct q6v5 *qproc, int ms)
{
unsigned long timeout;
@@ -384,8 +449,37 @@ static int q6v5proc_reset(struct q6v5 *qproc)
int ret;
int i;
+ if (qproc->version == MSS_SDM845) {
- if (qproc->version == MSS_MSM8996) {
+ val = readl(qproc->reg_base + QDSP6SS_SLEEP);
+ val |= 0x1;
+ writel(val, qproc->reg_base + QDSP6SS_SLEEP);
+
+ ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_SLEEP,
+ val, !(val & BIT(31)), 1,
+ SLEEP_CHECK_MAX_LOOPS);
+ if (ret) {
+ dev_err(qproc->dev, "QDSP6SS Sleep clock timed out\n");
+ return -ETIMEDOUT;
+ }
+
+ /* De-assert QDSP6 stop core */
+ writel(1, qproc->reg_base + QDSP6SS_BOOT_CORE_START);
+ /* Trigger boot FSM */
+ writel(1, qproc->reg_base + QDSP6SS_BOOT_CMD);
+
+ ret = readl_poll_timeout(qproc->rmb_base + RMB_MBA_MSS_STATUS,
+ val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT);
+ if (ret) {
+ dev_err(qproc->dev, "Boot FSM failed to complete.\n");
+ /* Reset the modem so that boot FSM is in reset state */
+ qproc->ops->reset_start(qproc);
+ return ret;
+ }
+
+ goto pbl_wait;
+
+ } else if (qproc->version == MSS_MSM8996) {
/* Override the ACC value if required */
writel(QDSP6SS_ACC_OVERRIDE_VAL,
qproc->reg_base + QDSP6SS_STRAP_ACC);
@@ -493,6 +587,7 @@ static int q6v5proc_reset(struct q6v5 *qproc)
val &= ~Q6SS_STOP_CORE;
writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
+pbl_wait:
/* Wait for PBL status */
ret = q6v5_rmb_pbl_wait(qproc, 1000);
if (ret == -ETIMEDOUT) {
@@ -746,7 +841,7 @@ static int q6v5_start(struct rproc *rproc)
dev_err(qproc->dev, "failed to enable supplies\n");
goto disable_proxy_clk;
}
- ret = reset_control_deassert(qproc->mss_restart);
+ ret = qproc->ops->reset_start(qproc);
if (ret) {
dev_err(qproc->dev, "failed to deassert mss restart\n");
goto disable_vdd;
@@ -841,7 +936,7 @@ static int q6v5_start(struct rproc *rproc)
qproc->active_clk_count);
assert_reset:
- reset_control_assert(qproc->mss_restart);
+ qproc->ops->reset_stop(qproc);
disable_vdd:
q6v5_regulator_disable(qproc, qproc->active_regs,
qproc->active_reg_count);
@@ -891,7 +986,7 @@ static int q6v5_stop(struct rproc *rproc)
qproc->mpss_phys, qproc->mpss_size);
WARN_ON(ret);
- reset_control_assert(qproc->mss_restart);
+ qproc->ops->reset_stop(qproc);
q6v5_clk_disable(qproc->dev, qproc->active_clks,
qproc->active_clk_count);
q6v5_regulator_disable(qproc, qproc->active_regs,
@@ -1140,6 +1235,12 @@ static int q6v5_probe(struct platform_device *pdev)
qproc->dev = &pdev->dev;
qproc->rproc = rproc;
platform_set_drvdata(pdev, qproc);
+ qproc->version = desc->version;
+
+ if (qproc->version == MSS_SDM845)
+ qproc->ops = &q6v5_sdm_ops;
+ else
+ qproc->ops = &q6v5_msm_ops;
init_completion(&qproc->start_done);
init_completion(&qproc->stop_done);
@@ -1188,7 +1289,6 @@ static int q6v5_probe(struct platform_device *pdev)
if (ret)
goto free_rproc;
- qproc->version = desc->version;
qproc->need_mem_protection = desc->need_mem_protection;
ret = q6v5_request_irq(qproc, pdev, "wdog", q6v5_wdog_interrupt);
if (ret < 0)
@@ -1213,6 +1313,7 @@ static int q6v5_probe(struct platform_device *pdev)
}
qproc->mpss_perm = BIT(QCOM_SCM_VMID_HLOS);
qproc->mba_perm = BIT(QCOM_SCM_VMID_HLOS);
+ qcom_add_glink_subdev(rproc, &qproc->glink_subdev);
qcom_add_smd_subdev(rproc, &qproc->smd_subdev);
qcom_add_ssr_subdev(rproc, &qproc->ssr_subdev, "mpss");
@@ -1234,6 +1335,7 @@ static int q6v5_remove(struct platform_device *pdev)
rproc_del(qproc->rproc);
+ qcom_remove_glink_subdev(qproc->rproc, &qproc->glink_subdev);
qcom_remove_smd_subdev(qproc->rproc, &qproc->smd_subdev);
qcom_remove_ssr_subdev(qproc->rproc, &qproc->ssr_subdev);
rproc_free(qproc->rproc);
@@ -1241,6 +1343,27 @@ static int q6v5_remove(struct platform_device *pdev)
return 0;
}
+static const struct rproc_hexagon_res sdm845_mss = {
+ .hexagon_mba_image = "mba.mbn",
+ .proxy_clk_names = (char*[]){
+ "xo",
+ "axis2",
+ "prng",
+ NULL
+ },
+ .active_clk_names = (char*[]){
+ "iface",
+ "bus",
+ "mem",
+ "gpll0_mss",
+ "snoc_axi",
+ "mnoc_axi",
+ NULL
+ },
+ .need_mem_protection = true,
+ .version = MSS_SDM845,
+};
+
static const struct rproc_hexagon_res msm8996_mss = {
.hexagon_mba_image = "mba.mbn",
.proxy_clk_names = (char*[]){
@@ -1334,6 +1457,7 @@ static int q6v5_remove(struct platform_device *pdev)
{ .compatible = "qcom,msm8916-mss-pil", .data = &msm8916_mss},
{ .compatible = "qcom,msm8974-mss-pil", .data = &msm8974_mss},
{ .compatible = "qcom,msm8996-mss-pil", .data = &msm8996_mss},
+ { .compatible = "qcom,sdm845-mss-pil", .data = &sdm845_mss},
{ },
};
MODULE_DEVICE_TABLE(of, q6v5_of_match);
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 16%]
* [PATCH 6/6] remoteproc: qcom: Reorder active clks enable and reset
2018-03-02 9:23 13% [PATCH 0/6] Add support for remoteproc modem-pil on SDM845 SoCs sibis
` (4 preceding siblings ...)
2018-03-02 9:23 16% ` [PATCH 5/6] remoteproc: qcom: Add support for mss remoteproc on SDM845 sibis
@ 2018-03-02 9:23 20% ` sibis
5 siblings, 0 replies; 200+ results
From: sibis @ 2018-03-02 9:23 UTC (permalink / raw)
To: bjorn.andersson
Cc: linux-remoteproc, linux-kernel, devicetree, sibis, georgi.djakov,
jassisinghbrar, p.zabel, ohad, mark.rutland, robh+dt, kyan,
sricharan, akdwived, linux-arm-msm
Active clks need to be enabled before Asserting/Deasserting
the reset lines in SDM845
Signed-off-by: sibis <sibis@codeaurora.org>
---
drivers/remoteproc/qcom_q6v5_pil.c | 19 ++++++++++---------
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
index f4997e0..cf45fe6 100644
--- a/drivers/remoteproc/qcom_q6v5_pil.c
+++ b/drivers/remoteproc/qcom_q6v5_pil.c
@@ -841,17 +841,18 @@ static int q6v5_start(struct rproc *rproc)
dev_err(qproc->dev, "failed to enable supplies\n");
goto disable_proxy_clk;
}
- ret = qproc->ops->reset_start(qproc);
- if (ret) {
- dev_err(qproc->dev, "failed to deassert mss restart\n");
- goto disable_vdd;
- }
ret = q6v5_clk_enable(qproc->dev, qproc->active_clks,
qproc->active_clk_count);
if (ret) {
dev_err(qproc->dev, "failed to enable clocks\n");
- goto assert_reset;
+ goto disable_vdd;
+ }
+
+ ret = qproc->ops->reset_start(qproc);
+ if (ret) {
+ dev_err(qproc->dev, "failed to deassert mss restart\n");
+ goto disable_active_clks;
}
/* Assign MBA image access in DDR to q6 */
@@ -862,7 +863,7 @@ static int q6v5_start(struct rproc *rproc)
dev_err(qproc->dev,
"assigning Q6 access to mba memory failed: %d\n",
xfermemop_ret);
- goto disable_active_clks;
+ goto assert_reset;
}
writel(qproc->mba_phys, qproc->rmb_base + RMB_MBA_IMAGE_REG);
@@ -931,12 +932,12 @@ static int q6v5_start(struct rproc *rproc)
"Failed to reclaim mba buffer, system may become unstable\n");
}
+assert_reset:
+ qproc->ops->reset_stop(qproc);
disable_active_clks:
q6v5_clk_disable(qproc->dev, qproc->active_clks,
qproc->active_clk_count);
-assert_reset:
- qproc->ops->reset_stop(qproc);
disable_vdd:
q6v5_regulator_disable(qproc, qproc->active_regs,
qproc->active_reg_count);
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 20%]
* Re: [PATCH 1/6] reset: qcom: AOSS (Always on subsystem) reset controller
2018-03-02 9:23 15% ` [PATCH 1/6] reset: qcom: AOSS (Always on subsystem) reset controller sibis
@ 2018-03-02 10:30 0% ` Philipp Zabel
2018-03-05 6:47 6% ` Sibi S
0 siblings, 1 reply; 200+ results
From: Philipp Zabel @ 2018-03-02 10:30 UTC (permalink / raw)
To: sibis, bjorn.andersson
Cc: linux-remoteproc, linux-kernel, devicetree, georgi.djakov,
jassisinghbrar, ohad, mark.rutland, robh+dt, kyan, sricharan,
akdwived, linux-arm-msm
Hi sibis,
thank you for the patch. I have a few questions and comments below.
On Fri, 2018-03-02 at 14:53 +0530, sibis wrote:
> Add reset controller driver for Qualcomm SDM845 SoC to
> control reset signals provided by AOSS for Modem, Venus
> ADSP, GPU, Camera, Wireless, Display subsystem
>
> Signed-off-by: sibis <sibis@codeaurora.org>
> ---
> .../devicetree/bindings/reset/qcom,aoss-reset.txt | 54 +++++++
> drivers/reset/Kconfig | 10 ++
> drivers/reset/Makefile | 1 +
> drivers/reset/reset-qcom-aoss.c | 161 +++++++++++++++++++++
> include/dt-bindings/reset/qcom,aoss-sdm845.h | 17 +++
> 5 files changed, 243 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
> create mode 100644 drivers/reset/reset-qcom-aoss.c
> create mode 100644 include/dt-bindings/reset/qcom,aoss-sdm845.h
>
> diff --git a/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
> new file mode 100644
> index 0000000..5318e14
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
> @@ -0,0 +1,54 @@
> +Qualcomm AOSS Reset Controller
> +======================================
> +
> +This binding describes a reset-controller found on AOSS (Always on SubSysem)
> +for Qualcomm SDM845 SoCs.
> +
> +Required properties:
> +- compatible:
> + Usage: required
> + Value type: <string>
> + Definition: must be:
> + "qcom,aoss-reset-sdm845", "syscon"
> +
> +- reg:
> + Usage: required
> + Value type: <prop-encoded-array>
> + Definition: must specify the base address and size of the
> + syscon device.
> +
> +
> +- #reset-cells:
> + Usage: required
> + Value type: <uint>
> + Definition: must be 1; cell entry represents the reset index.
> +
> +example:
> +
> +aoss_reset: qcom,reset-controller@b2e0100 {
> + compatible = "qcom,aoss-reset-sdm845", "syscon";
> + reg = <0xc2b0000 0x20004>;
> + #reset-cells = <1>;
> +};
> +
> +
> +Specifying reset lines connected to IP modules
> +==============================================
> +
> +Device nodes that need access to reset lines should
> +specify them as a reset phandle in their corresponding node as
> +specified in reset.txt.
> +
> +Example:
> +
> + modem-pil@4080000 {
> + ...
> +
> + resets = <&aoss_reset AOSS_CC_MSS_RESTART>;
> + reset-names = "mss_restart";
> +
> + ...
> + };
> +
> +For list of all valid reset indicies see
> +<dt-bindings/reset/qcom,aoss-sdm845.h>
> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
> index 7fc7769..4b1da86 100644
> --- a/drivers/reset/Kconfig
> +++ b/drivers/reset/Kconfig
> @@ -81,6 +81,16 @@ config RESET_PISTACHIO
> help
> This enables the reset driver for ImgTec Pistachio SoCs.
>
> +config RESET_QCOM_AOSS
> + bool "Qcom AOSS Reset Driver"
> + depends on ARCH_QCOM || COMPILE_TEST
Do all ARCH_QCOM have AOSS? If so, should this be enabled by default?
> + select MFD_SYSCON
> + help
> + This enables the AOSS (Always On SubSystem) reset driver
> + for Qcom SoCs. Say Y if you want to control reset signals
Is Qcom and Qualcomm interchangeable?
> + provided by AOSS for Modem, Venus, ADSP, GPU, Camera,
> + Wireless, Display subsystem. Otherwise, say N.
> +
> config RESET_SIMPLE
> bool "Simple Reset Controller Driver" if COMPILE_TEST
> default ARCH_SOCFPGA || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX
> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
> index 132c24f..c30044a 100644
> --- a/drivers/reset/Makefile
> +++ b/drivers/reset/Makefile
> @@ -14,6 +14,7 @@ obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
> obj-$(CONFIG_RESET_MESON) += reset-meson.o
> obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
> obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o
> +obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o
> obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
> obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
> obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
> diff --git a/drivers/reset/reset-qcom-aoss.c b/drivers/reset/reset-qcom-aoss.c
> new file mode 100644
> index 0000000..eb8c69b
> --- /dev/null
> +++ b/drivers/reset/reset-qcom-aoss.c
> @@ -0,0 +1,161 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2018 The Linux Foundation. All rights reserved.
> + */
> +
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/reset-controller.h>
> +#include <linux/regmap.h>
> +#include <linux/of_device.h>
> +#include <dt-bindings/reset/qcom,aoss-sdm845.h>
> +
> +struct qcom_aoss_reset_map {
> + unsigned int reg;
> + u8 bit;
> +};
> +
> +struct qcom_aoss_desc {
> + const struct regmap_config *config;
> + const struct qcom_aoss_reset_map *resets;
> + int delay;
> + size_t num_resets;
> +};
> +
> +struct qcom_aoss_reset_data {
> + struct reset_controller_dev rcdev;
> + struct regmap *regmap;
> + const struct qcom_aoss_desc *desc;
> +};
> +
> +static const struct regmap_config aoss_sdm845_regmap_config = {
> + .name = "aoss-reset",
> + .reg_bits = 32,
> + .reg_stride = 4,
> + .val_bits = 32,
> + .max_register = 0x20000,
> + .fast_io = true,
> +};
> +
> +static const struct qcom_aoss_reset_map aoss_sdm845_resets[] = {
> + [AOSS_CC_MSS_RESTART] = { 0x0, 0 },
> + [AOSS_CC_CAMSS_RESTART] = { 0x1000, 0 },
> + [AOSS_CC_VENUS_RESTART] = { 0x2000, 0 },
> + [AOSS_CC_GPU_RESTART] = { 0x3000, 0 },
> + [AOSS_CC_DISPSS_RESTART] = { 0x4000, 0 },
> + [AOSS_CC_WCSS_RESTART] = { 0x10000, 0 },
> + [AOSS_CC_LPASS_RESTART] = { 0x20000, 0 },
> +};
> +
> +static const struct qcom_aoss_desc aoss_sdm845_desc = {
> + .config = &aoss_sdm845_regmap_config,
> + .resets = aoss_sdm845_resets,
> + /* Wait 6 32kHz sleep cycles for reset */
> + .delay = 200,
> + .num_resets = ARRAY_SIZE(aoss_sdm845_resets),
> +};
> +
> +static struct qcom_aoss_reset_data *to_qcom_aoss_reset_data(
> + struct reset_controller_dev *rcdev)
> +{
> + return container_of(rcdev, struct qcom_aoss_reset_data, rcdev);
> +}
> +
> +static int qcom_aoss_control_assert(struct reset_controller_dev *rcdev,
> + unsigned long idx)
> +{
> + struct qcom_aoss_reset_data *data = to_qcom_aoss_reset_data(rcdev);
> + const struct qcom_aoss_reset_map *map = &data->desc->resets[idx];
> +
> + if (idx >= rcdev->nr_resets)
> + return -EINVAL;
This check is not necessary. For all drivers that don't set of_xlate,
the default of_reset_simple_xlate already makes sure no reset_control
is ever returned with rstc->id >= rcdev->nr_resets.
> + return regmap_update_bits(data->regmap, map->reg,
> + BIT(map->bit), BIT(map->bit));
> +}
> +
> +static int qcom_aoss_control_deassert(struct reset_controller_dev *rcdev,
> + unsigned long idx)
> +{
> + struct qcom_aoss_reset_data *data = to_qcom_aoss_reset_data(rcdev);
> + const struct qcom_aoss_reset_map *map = &data->desc->resets[idx];
> +
> + if (idx >= rcdev->nr_resets)
> + return -EINVAL;
Same here.
> + return regmap_update_bits(data->regmap, map->reg, BIT(map->bit), 0);
> +}
> +
> +static int qcom_aoss_control_reset(struct reset_controller_dev *rcdev,
> + unsigned long idx)
> +{
> + struct qcom_aoss_reset_data *data = to_qcom_aoss_reset_data(rcdev);
> + int ret;
> +
> + ret = rcdev->ops->assert(rcdev, idx);
Don't use the ops function pointers here, just call
qcom_aoss_control_assert directly.
> + if (ret)
> + return ret;
> +
> + udelay(data->desc->delay);
> +
> + ret = rcdev->ops->deassert(rcdev, idx);
> + if (ret)
> + return ret;
> +
> + return 0;
This can be simplified to just
return qcom_aoss_control_deassert(rcdev, idx);
> +}
> +
> +static const struct reset_control_ops qcom_aoss_reset_ops = {
> + .reset = qcom_aoss_control_reset,
> + .assert = qcom_aoss_control_assert,
> + .deassert = qcom_aoss_control_deassert,
> +};
> +
> +static int qcom_aoss_reset_probe(struct platform_device *pdev)
> +{
> + struct qcom_aoss_reset_data *data;
> + struct device *dev = &pdev->dev;
> + const struct qcom_aoss_desc *desc;
> +
> + desc = of_device_get_match_data(&pdev->dev);
You could use dev here instead of pdev->dev.
> + if (!desc)
> + return -EINVAL;
> +
> + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
> + if (!data)
> + return -ENOMEM;
> +
> + data->desc = desc;
> + data->regmap = syscon_node_to_regmap(dev->of_node);
> + if (IS_ERR(data->regmap)) {
> + dev_err(dev, "Unable to get aoss-reset regmap");
> + return PTR_ERR(data->regmap);
> + }
> + regmap_attach_dev(dev, data->regmap, desc->config);
> +
> + data->rcdev.owner = THIS_MODULE;
> + data->rcdev.ops = &qcom_aoss_reset_ops;
> + data->rcdev.nr_resets = desc->num_resets;
> + data->rcdev.of_node = pdev->dev.of_node;
And here.
> + return devm_reset_controller_register(&pdev->dev, &data->rcdev);
And here.
> +}
> +
> +static const struct of_device_id qcom_aoss_reset_of_match[] = {
> + { .compatible = "qcom,aoss-reset-sdm845", .data = &aoss_sdm845_desc},
Consider adding a space between &aoss_sdm845_desc and } ...
> + {}
> +};
> +
> +static struct platform_driver qcom_aoss_reset_driver = {
> + .probe = qcom_aoss_reset_probe,
> + .driver = {
> + .name = "qcom_aoss_reset",
... and removing the superfluous space here.
> + .of_match_table = qcom_aoss_reset_of_match,
> + },
> +};
> +
> +builtin_platform_driver(qcom_aoss_reset_driver);
> +
> +MODULE_DESCRIPTION("Qualcomm AOSS Reset Driver");
> +MODULE_LICENSE("GPL v2");
> diff --git a/include/dt-bindings/reset/qcom,aoss-sdm845.h b/include/dt-bindings/reset/qcom,aoss-sdm845.h
> new file mode 100644
> index 0000000..e9b38fc
> --- /dev/null
> +++ b/include/dt-bindings/reset/qcom,aoss-sdm845.h
> @@ -0,0 +1,17 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2018 The Linux Foundation. All rights reserved.
> + */
> +
> +#ifndef _DT_BINDINGS_RESET_AOSS_SDM_845_H
> +#define _DT_BINDINGS_RESET_AOSS_SDM_845_H
> +
> +#define AOSS_CC_MSS_RESTART 0
> +#define AOSS_CC_CAMSS_RESTART 1
> +#define AOSS_CC_VENUS_RESTART 2
> +#define AOSS_CC_GPU_RESTART 3
> +#define AOSS_CC_DISPSS_RESTART 4
> +#define AOSS_CC_WCSS_RESTART 5
> +#define AOSS_CC_LPASS_RESTART 6
> +
> +#endif
regards
Philipp
^ permalink raw reply [relevance 0%]
* Re: [PATCH 1/6] reset: qcom: AOSS (Always on subsystem) reset controller
2018-03-02 10:30 0% ` Philipp Zabel
@ 2018-03-05 6:47 6% ` Sibi S
0 siblings, 0 replies; 200+ results
From: Sibi S @ 2018-03-05 6:47 UTC (permalink / raw)
To: Philipp Zabel, bjorn.andersson
Cc: linux-remoteproc, linux-kernel, devicetree, georgi.djakov,
jassisinghbrar, ohad, mark.rutland, robh+dt, kyan, sricharan,
akdwived, linux-arm-msm
Hi Philipp,
Thanks for the review. I will post out the v2 of the patch series.
On 03/02/2018 04:00 PM, Philipp Zabel wrote:
> Hi sibis,
>
> thank you for the patch. I have a few questions and comments below.
>
> On Fri, 2018-03-02 at 14:53 +0530, sibis wrote:
>> Add reset controller driver for Qualcomm SDM845 SoC to
>> control reset signals provided by AOSS for Modem, Venus
>> ADSP, GPU, Camera, Wireless, Display subsystem
>>
>> Signed-off-by: sibis <sibis@codeaurora.org>
>> ---
>> .../devicetree/bindings/reset/qcom,aoss-reset.txt | 54 +++++++
>> drivers/reset/Kconfig | 10 ++
>> drivers/reset/Makefile | 1 +
>> drivers/reset/reset-qcom-aoss.c | 161 +++++++++++++++++++++
>> include/dt-bindings/reset/qcom,aoss-sdm845.h | 17 +++
>> 5 files changed, 243 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
>> create mode 100644 drivers/reset/reset-qcom-aoss.c
>> create mode 100644 include/dt-bindings/reset/qcom,aoss-sdm845.h
>>
>> diff --git a/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
>> new file mode 100644
>> index 0000000..5318e14
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
>> @@ -0,0 +1,54 @@
>> +Qualcomm AOSS Reset Controller
>> +======================================
>> +
>> +This binding describes a reset-controller found on AOSS (Always on SubSysem)
>> +for Qualcomm SDM845 SoCs.
>> +
>> +Required properties:
>> +- compatible:
>> + Usage: required
>> + Value type: <string>
>> + Definition: must be:
>> + "qcom,aoss-reset-sdm845", "syscon"
>> +
>> +- reg:
>> + Usage: required
>> + Value type: <prop-encoded-array>
>> + Definition: must specify the base address and size of the
>> + syscon device.
>> +
>> +
>> +- #reset-cells:
>> + Usage: required
>> + Value type: <uint>
>> + Definition: must be 1; cell entry represents the reset index.
>> +
>> +example:
>> +
>> +aoss_reset: qcom,reset-controller@b2e0100 {
>> + compatible = "qcom,aoss-reset-sdm845", "syscon";
>> + reg = <0xc2b0000 0x20004>;
>> + #reset-cells = <1>;
>> +};
>> +
>> +
>> +Specifying reset lines connected to IP modules
>> +==============================================
>> +
>> +Device nodes that need access to reset lines should
>> +specify them as a reset phandle in their corresponding node as
>> +specified in reset.txt.
>> +
>> +Example:
>> +
>> + modem-pil@4080000 {
>> + ...
>> +
>> + resets = <&aoss_reset AOSS_CC_MSS_RESTART>;
>> + reset-names = "mss_restart";
>> +
>> + ...
>> + };
>> +
>> +For list of all valid reset indicies see
>> +<dt-bindings/reset/qcom,aoss-sdm845.h>
>> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
>> index 7fc7769..4b1da86 100644
>> --- a/drivers/reset/Kconfig
>> +++ b/drivers/reset/Kconfig
>> @@ -81,6 +81,16 @@ config RESET_PISTACHIO
>> help
>> This enables the reset driver for ImgTec Pistachio SoCs.
>>
>> +config RESET_QCOM_AOSS
>> + bool "Qcom AOSS Reset Driver"
>> + depends on ARCH_QCOM || COMPILE_TEST
>
> Do all ARCH_QCOM have AOSS? If so, should this be enabled by default?
>
AOSS reset is currently supported on SDM845 SoCs and not on any of other
the previously upstreamed Qualcomm SoCs. I will change description to
convey the same. I needs to explicitly enabled for SDM845 SoCs.
>> + select MFD_SYSCON
>> + help
>> + This enables the AOSS (Always On SubSystem) reset driver
>> + for Qcom SoCs. Say Y if you want to control reset signals
>
> Is Qcom and Qualcomm interchangeable?
>
Though it is used interchangeably, it will make more sense if I
change it to Qualcomm here.
>> + provided by AOSS for Modem, Venus, ADSP, GPU, Camera,
>> + Wireless, Display subsystem. Otherwise, say N.
>> +
>> config RESET_SIMPLE
>> bool "Simple Reset Controller Driver" if COMPILE_TEST
>> default ARCH_SOCFPGA || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX
>> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
>> index 132c24f..c30044a 100644
>> --- a/drivers/reset/Makefile
>> +++ b/drivers/reset/Makefile
>> @@ -14,6 +14,7 @@ obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
>> obj-$(CONFIG_RESET_MESON) += reset-meson.o
>> obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
>> obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o
>> +obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o
>> obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
>> obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
>> obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
>> diff --git a/drivers/reset/reset-qcom-aoss.c b/drivers/reset/reset-qcom-aoss.c
>> new file mode 100644
>> index 0000000..eb8c69b
>> --- /dev/null
>> +++ b/drivers/reset/reset-qcom-aoss.c
>> @@ -0,0 +1,161 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (C) 2018 The Linux Foundation. All rights reserved.
>> + */
>> +
>> +#include <linux/mfd/syscon.h>
>> +#include <linux/module.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/reset-controller.h>
>> +#include <linux/regmap.h>
>> +#include <linux/of_device.h>
>> +#include <dt-bindings/reset/qcom,aoss-sdm845.h>
>> +
>> +struct qcom_aoss_reset_map {
>> + unsigned int reg;
>> + u8 bit;
>> +};
>> +
>> +struct qcom_aoss_desc {
>> + const struct regmap_config *config;
>> + const struct qcom_aoss_reset_map *resets;
>> + int delay;
>> + size_t num_resets;
>> +};
>> +
>> +struct qcom_aoss_reset_data {
>> + struct reset_controller_dev rcdev;
>> + struct regmap *regmap;
>> + const struct qcom_aoss_desc *desc;
>> +};
>> +
>> +static const struct regmap_config aoss_sdm845_regmap_config = {
>> + .name = "aoss-reset",
>> + .reg_bits = 32,
>> + .reg_stride = 4,
>> + .val_bits = 32,
>> + .max_register = 0x20000,
>> + .fast_io = true,
>> +};
>> +
>> +static const struct qcom_aoss_reset_map aoss_sdm845_resets[] = {
>> + [AOSS_CC_MSS_RESTART] = { 0x0, 0 },
>> + [AOSS_CC_CAMSS_RESTART] = { 0x1000, 0 },
>> + [AOSS_CC_VENUS_RESTART] = { 0x2000, 0 },
>> + [AOSS_CC_GPU_RESTART] = { 0x3000, 0 },
>> + [AOSS_CC_DISPSS_RESTART] = { 0x4000, 0 },
>> + [AOSS_CC_WCSS_RESTART] = { 0x10000, 0 },
>> + [AOSS_CC_LPASS_RESTART] = { 0x20000, 0 },
>> +};
>> +
>> +static const struct qcom_aoss_desc aoss_sdm845_desc = {
>> + .config = &aoss_sdm845_regmap_config,
>> + .resets = aoss_sdm845_resets,
>> + /* Wait 6 32kHz sleep cycles for reset */
>> + .delay = 200,
>> + .num_resets = ARRAY_SIZE(aoss_sdm845_resets),
>> +};
>> +
>> +static struct qcom_aoss_reset_data *to_qcom_aoss_reset_data(
>> + struct reset_controller_dev *rcdev)
>> +{
>> + return container_of(rcdev, struct qcom_aoss_reset_data, rcdev);
>> +}
>> +
>> +static int qcom_aoss_control_assert(struct reset_controller_dev *rcdev,
>> + unsigned long idx)
>> +{
>> + struct qcom_aoss_reset_data *data = to_qcom_aoss_reset_data(rcdev);
>> + const struct qcom_aoss_reset_map *map = &data->desc->resets[idx];
>> +
>> + if (idx >= rcdev->nr_resets)
>> + return -EINVAL;
>
> This check is not necessary. For all drivers that don't set of_xlate,
> the default of_reset_simple_xlate already makes sure no reset_control
> is ever returned with rstc->id >= rcdev->nr_resets.
>
Will remove it
>> + return regmap_update_bits(data->regmap, map->reg,
>> + BIT(map->bit), BIT(map->bit));
>> +}
>> +
>> +static int qcom_aoss_control_deassert(struct reset_controller_dev *rcdev,
>> + unsigned long idx)
>> +{
>> + struct qcom_aoss_reset_data *data = to_qcom_aoss_reset_data(rcdev);
>> + const struct qcom_aoss_reset_map *map = &data->desc->resets[idx];
>> +
>> + if (idx >= rcdev->nr_resets)
>> + return -EINVAL;
>
> Same here.
>
ditto
>> + return regmap_update_bits(data->regmap, map->reg, BIT(map->bit), 0);
>> +}
>> +
>> +static int qcom_aoss_control_reset(struct reset_controller_dev *rcdev,
>> + unsigned long idx)
>> +{
>> + struct qcom_aoss_reset_data *data = to_qcom_aoss_reset_data(rcdev);
>> + int ret;
>> +
>> + ret = rcdev->ops->assert(rcdev, idx);
>
> Don't use the ops function pointers here, just call
> qcom_aoss_control_assert directly.
sure will repace it.
>
>> + if (ret)
>> + return ret;
>> +
>> + udelay(data->desc->delay);
>> +
>> + ret = rcdev->ops->deassert(rcdev, idx);
>> + if (ret)
>> + return ret;
>> +
>> + return 0;
>
> This can be simplified to just
>
> return qcom_aoss_control_deassert(rcdev, idx);
>
ditto
>> +}
>> +
>> +static const struct reset_control_ops qcom_aoss_reset_ops = {
>> + .reset = qcom_aoss_control_reset,
>> + .assert = qcom_aoss_control_assert,
>> + .deassert = qcom_aoss_control_deassert,
>> +};
>> +
>> +static int qcom_aoss_reset_probe(struct platform_device *pdev)
>> +{
>> + struct qcom_aoss_reset_data *data;
>> + struct device *dev = &pdev->dev;
>> + const struct qcom_aoss_desc *desc;
>> +
>> + desc = of_device_get_match_data(&pdev->dev);
>
> You could use dev here instead of pdev->dev.
>
Yeah I will replace all instances of pdev->dev with dev
>> + if (!desc)
>> + return -EINVAL;
>> +
>> + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
>> + if (!data)
>> + return -ENOMEM;
>> +
>> + data->desc = desc;
>> + data->regmap = syscon_node_to_regmap(dev->of_node);
>> + if (IS_ERR(data->regmap)) {
>> + dev_err(dev, "Unable to get aoss-reset regmap");
>> + return PTR_ERR(data->regmap);
>> + }
>> + regmap_attach_dev(dev, data->regmap, desc->config);
>> +
>> + data->rcdev.owner = THIS_MODULE;
>> + data->rcdev.ops = &qcom_aoss_reset_ops;
>> + data->rcdev.nr_resets = desc->num_resets;
>> + data->rcdev.of_node = pdev->dev.of_node;
>
> And here.
>
>> + return devm_reset_controller_register(&pdev->dev, &data->rcdev);
>
> And here.
>
>> +}
>> +
>> +static const struct of_device_id qcom_aoss_reset_of_match[] = {
>> + { .compatible = "qcom,aoss-reset-sdm845", .data = &aoss_sdm845_desc},
>
> Consider adding a space between &aoss_sdm845_desc and } ...
>
sure will do
>> + {}
>> +};
>> +
>> +static struct platform_driver qcom_aoss_reset_driver = {
>> + .probe = qcom_aoss_reset_probe,
>> + .driver = {
>> + .name = "qcom_aoss_reset",
>
> ... and removing the superfluous space here.
Will remove the superfluous spacing
>
>> + .of_match_table = qcom_aoss_reset_of_match,
>> + },
>> +};
>> +
>> +builtin_platform_driver(qcom_aoss_reset_driver);
>> +
>> +MODULE_DESCRIPTION("Qualcomm AOSS Reset Driver");
>> +MODULE_LICENSE("GPL v2");
>> diff --git a/include/dt-bindings/reset/qcom,aoss-sdm845.h b/include/dt-bindings/reset/qcom,aoss-sdm845.h
>> new file mode 100644
>> index 0000000..e9b38fc
>> --- /dev/null
>> +++ b/include/dt-bindings/reset/qcom,aoss-sdm845.h
>> @@ -0,0 +1,17 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (C) 2018 The Linux Foundation. All rights reserved.
>> + */
>> +
>> +#ifndef _DT_BINDINGS_RESET_AOSS_SDM_845_H
>> +#define _DT_BINDINGS_RESET_AOSS_SDM_845_H
>> +
>> +#define AOSS_CC_MSS_RESTART 0
>> +#define AOSS_CC_CAMSS_RESTART 1
>> +#define AOSS_CC_VENUS_RESTART 2
>> +#define AOSS_CC_GPU_RESTART 3
>> +#define AOSS_CC_DISPSS_RESTART 4
>> +#define AOSS_CC_WCSS_RESTART 5
>> +#define AOSS_CC_LPASS_RESTART 6
>> +
>> +#endif
>
> regards
> Philipp
>
--
Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc, is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [relevance 6%]
* [PATCH 0/6] Add support for remoteproc modem-pil on SDM845 SoCs
@ 2018-03-05 9:53 13% sibis
2018-03-05 9:53 15% ` [PATCH 1/6] reset: qcom: AOSS (Always on subsystem) reset controller sibis
` (5 more replies)
0 siblings, 6 replies; 200+ results
From: sibis @ 2018-03-05 9:53 UTC (permalink / raw)
To: bjorn.andersson
Cc: linux-remoteproc, linux-kernel, devicetree, sibis, georgi.djakov,
jassisinghbrar, p.zabel, ohad, mark.rutland, robh+dt, kyan,
sricharan, akdwived, linux-arm-msm
This patch series add support for remoteproc Q6v5 modem-pil on Qualcomm
SDM845 SoC. The first patch adds AOSS (Always on subsystem) reset driver
to provide for mss reset line. The third patch adds the APCS offset for
SDM845. The last couple of patches add the resets sequence for Q6 on
SDM845 and adds helper functions for arbitrary reset assert/deassert
sequences
V2:
Addressed reset-qcom-aoss review suggestions and reworked
re-ordering of the active clk and reset sequence in
qcom_q6v5_pil
sibis (6):
reset: qcom: AOSS (Always on subsystem) reset controller
dt-bindings: mailbox: Add APCS global binding for SDM845 SoCs
mailbox: Add support for Qualcomm SDM845 SoCs
dt-bindings: remoteproc: Add Q6v5 Modem PIL binding for SDM845
remoteproc: qcom: Add support for mss remoteproc on SDM845
remoteproc: qcom: Always assert and deassert reset signals in SDM845
.../bindings/mailbox/qcom,apcs-kpss-global.txt | 3 +-
.../devicetree/bindings/remoteproc/qcom,q6v5.txt | 5 +-
.../devicetree/bindings/reset/qcom,aoss-reset.txt | 54 +++++++
drivers/mailbox/qcom-apcs-ipc-mailbox.c | 1 +
drivers/remoteproc/qcom_q6v5_pil.c | 163 ++++++++++++++++++++-
drivers/reset/Kconfig | 10 ++
drivers/reset/Makefile | 1 +
drivers/reset/reset-qcom-aoss.c | 151 +++++++++++++++++++
include/dt-bindings/reset/qcom,aoss-sdm845.h | 17 +++
9 files changed, 396 insertions(+), 9 deletions(-)
create mode 100644 Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
create mode 100644 drivers/reset/reset-qcom-aoss.c
create mode 100644 include/dt-bindings/reset/qcom,aoss-sdm845.h
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [relevance 13%]
* [PATCH 1/6] reset: qcom: AOSS (Always on subsystem) reset controller
2018-03-05 9:53 13% [PATCH 0/6] Add support for remoteproc modem-pil on SDM845 SoCs sibis
@ 2018-03-05 9:53 15% ` sibis
2018-03-07 21:35 0% ` Rob Herring
2018-03-05 9:53 21% ` [PATCH 2/6] dt-bindings: mailbox: Add APCS global binding for SDM845 SoCs sibis
` (4 subsequent siblings)
5 siblings, 1 reply; 200+ results
From: sibis @ 2018-03-05 9:53 UTC (permalink / raw)
To: bjorn.andersson
Cc: linux-remoteproc, linux-kernel, devicetree, sibis, georgi.djakov,
jassisinghbrar, p.zabel, ohad, mark.rutland, robh+dt, kyan,
sricharan, akdwived, linux-arm-msm
Add reset controller driver for Qualcomm SDM845 SoC to
control reset signals provided by AOSS for Modem, Venus
ADSP, GPU, Camera, Wireless, Display subsystem
Signed-off-by: sibis <sibis@codeaurora.org>
---
.../devicetree/bindings/reset/qcom,aoss-reset.txt | 54 ++++++++
drivers/reset/Kconfig | 10 ++
drivers/reset/Makefile | 1 +
drivers/reset/reset-qcom-aoss.c | 151 +++++++++++++++++++++
include/dt-bindings/reset/qcom,aoss-sdm845.h | 17 +++
5 files changed, 233 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
create mode 100644 drivers/reset/reset-qcom-aoss.c
create mode 100644 include/dt-bindings/reset/qcom,aoss-sdm845.h
diff --git a/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
new file mode 100644
index 0000000..5318e14
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
@@ -0,0 +1,54 @@
+Qualcomm AOSS Reset Controller
+======================================
+
+This binding describes a reset-controller found on AOSS (Always on SubSysem)
+for Qualcomm SDM845 SoCs.
+
+Required properties:
+- compatible:
+ Usage: required
+ Value type: <string>
+ Definition: must be:
+ "qcom,aoss-reset-sdm845", "syscon"
+
+- reg:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: must specify the base address and size of the
+ syscon device.
+
+
+- #reset-cells:
+ Usage: required
+ Value type: <uint>
+ Definition: must be 1; cell entry represents the reset index.
+
+example:
+
+aoss_reset: qcom,reset-controller@b2e0100 {
+ compatible = "qcom,aoss-reset-sdm845", "syscon";
+ reg = <0xc2b0000 0x20004>;
+ #reset-cells = <1>;
+};
+
+
+Specifying reset lines connected to IP modules
+==============================================
+
+Device nodes that need access to reset lines should
+specify them as a reset phandle in their corresponding node as
+specified in reset.txt.
+
+Example:
+
+ modem-pil@4080000 {
+ ...
+
+ resets = <&aoss_reset AOSS_CC_MSS_RESTART>;
+ reset-names = "mss_restart";
+
+ ...
+ };
+
+For list of all valid reset indicies see
+<dt-bindings/reset/qcom,aoss-sdm845.h>
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 7fc7769..1141733 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -81,6 +81,16 @@ config RESET_PISTACHIO
help
This enables the reset driver for ImgTec Pistachio SoCs.
+config RESET_QCOM_AOSS
+ bool "Qcom AOSS Reset Driver"
+ depends on ARCH_QCOM || COMPILE_TEST
+ select MFD_SYSCON
+ help
+ This enables the AOSS (Always On SubSystem) reset driver
+ for Qualcomm SDM845 SoCs. Say Y if you want to control
+ reset signals provided by AOSS for Modem, Venus, ADSP,
+ GPU, Camera, Wireless, Display subsystem. Otherwise, say N.
+
config RESET_SIMPLE
bool "Simple Reset Controller Driver" if COMPILE_TEST
default ARCH_SOCFPGA || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 132c24f..c30044a 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
obj-$(CONFIG_RESET_MESON) += reset-meson.o
obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o
+obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o
obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
diff --git a/drivers/reset/reset-qcom-aoss.c b/drivers/reset/reset-qcom-aoss.c
new file mode 100644
index 0000000..1f3e3e8
--- /dev/null
+++ b/drivers/reset/reset-qcom-aoss.c
@@ -0,0 +1,151 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+#include <linux/regmap.h>
+#include <linux/of_device.h>
+#include <dt-bindings/reset/qcom,aoss-sdm845.h>
+
+struct qcom_aoss_reset_map {
+ unsigned int reg;
+ u8 bit;
+};
+
+struct qcom_aoss_desc {
+ const struct regmap_config *config;
+ const struct qcom_aoss_reset_map *resets;
+ int delay;
+ size_t num_resets;
+};
+
+struct qcom_aoss_reset_data {
+ struct reset_controller_dev rcdev;
+ struct regmap *regmap;
+ const struct qcom_aoss_desc *desc;
+};
+
+static const struct regmap_config aoss_sdm845_regmap_config = {
+ .name = "aoss-reset",
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x20000,
+ .fast_io = true,
+};
+
+static const struct qcom_aoss_reset_map aoss_sdm845_resets[] = {
+ [AOSS_CC_MSS_RESTART] = { 0x0, 0 },
+ [AOSS_CC_CAMSS_RESTART] = { 0x1000, 0 },
+ [AOSS_CC_VENUS_RESTART] = { 0x2000, 0 },
+ [AOSS_CC_GPU_RESTART] = { 0x3000, 0 },
+ [AOSS_CC_DISPSS_RESTART] = { 0x4000, 0 },
+ [AOSS_CC_WCSS_RESTART] = { 0x10000, 0 },
+ [AOSS_CC_LPASS_RESTART] = { 0x20000, 0 },
+};
+
+static const struct qcom_aoss_desc aoss_sdm845_desc = {
+ .config = &aoss_sdm845_regmap_config,
+ .resets = aoss_sdm845_resets,
+ /* Wait 6 32kHz sleep cycles for reset */
+ .delay = 200,
+ .num_resets = ARRAY_SIZE(aoss_sdm845_resets),
+};
+
+static struct qcom_aoss_reset_data *to_qcom_aoss_reset_data(
+ struct reset_controller_dev *rcdev)
+{
+ return container_of(rcdev, struct qcom_aoss_reset_data, rcdev);
+}
+
+static int qcom_aoss_control_assert(struct reset_controller_dev *rcdev,
+ unsigned long idx)
+{
+ struct qcom_aoss_reset_data *data = to_qcom_aoss_reset_data(rcdev);
+ const struct qcom_aoss_reset_map *map = &data->desc->resets[idx];
+
+ return regmap_update_bits(data->regmap, map->reg,
+ BIT(map->bit), BIT(map->bit));
+}
+
+static int qcom_aoss_control_deassert(struct reset_controller_dev *rcdev,
+ unsigned long idx)
+{
+ struct qcom_aoss_reset_data *data = to_qcom_aoss_reset_data(rcdev);
+ const struct qcom_aoss_reset_map *map = &data->desc->resets[idx];
+
+ return regmap_update_bits(data->regmap, map->reg, BIT(map->bit), 0);
+}
+
+static int qcom_aoss_control_reset(struct reset_controller_dev *rcdev,
+ unsigned long idx)
+{
+ struct qcom_aoss_reset_data *data = to_qcom_aoss_reset_data(rcdev);
+ int ret;
+
+ ret = qcom_aoss_control_assert(rcdev, idx);
+ if (ret)
+ return ret;
+
+ udelay(data->desc->delay);
+
+ return qcom_aoss_control_deassert(rcdev, idx);
+}
+
+static const struct reset_control_ops qcom_aoss_reset_ops = {
+ .reset = qcom_aoss_control_reset,
+ .assert = qcom_aoss_control_assert,
+ .deassert = qcom_aoss_control_deassert,
+};
+
+static int qcom_aoss_reset_probe(struct platform_device *pdev)
+{
+ struct qcom_aoss_reset_data *data;
+ struct device *dev = &pdev->dev;
+ const struct qcom_aoss_desc *desc;
+
+ desc = of_device_get_match_data(dev);
+ if (!desc)
+ return -EINVAL;
+
+ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ data->desc = desc;
+ data->regmap = syscon_node_to_regmap(dev->of_node);
+ if (IS_ERR(data->regmap)) {
+ dev_err(dev, "Unable to get aoss-reset regmap");
+ return PTR_ERR(data->regmap);
+ }
+ regmap_attach_dev(dev, data->regmap, desc->config);
+
+ data->rcdev.owner = THIS_MODULE;
+ data->rcdev.ops = &qcom_aoss_reset_ops;
+ data->rcdev.nr_resets = desc->num_resets;
+ data->rcdev.of_node = dev->of_node;
+
+ return devm_reset_controller_register(dev, &data->rcdev);
+}
+
+static const struct of_device_id qcom_aoss_reset_of_match[] = {
+ { .compatible = "qcom,aoss-reset-sdm845", .data = &aoss_sdm845_desc },
+ {}
+};
+
+static struct platform_driver qcom_aoss_reset_driver = {
+ .probe = qcom_aoss_reset_probe,
+ .driver = {
+ .name = "qcom_aoss_reset",
+ .of_match_table = qcom_aoss_reset_of_match,
+ },
+};
+
+builtin_platform_driver(qcom_aoss_reset_driver);
+
+MODULE_DESCRIPTION("Qualcomm AOSS Reset Driver");
+MODULE_LICENSE("GPL v2");
diff --git a/include/dt-bindings/reset/qcom,aoss-sdm845.h b/include/dt-bindings/reset/qcom,aoss-sdm845.h
new file mode 100644
index 0000000..e9b38fc
--- /dev/null
+++ b/include/dt-bindings/reset/qcom,aoss-sdm845.h
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_RESET_AOSS_SDM_845_H
+#define _DT_BINDINGS_RESET_AOSS_SDM_845_H
+
+#define AOSS_CC_MSS_RESTART 0
+#define AOSS_CC_CAMSS_RESTART 1
+#define AOSS_CC_VENUS_RESTART 2
+#define AOSS_CC_GPU_RESTART 3
+#define AOSS_CC_DISPSS_RESTART 4
+#define AOSS_CC_WCSS_RESTART 5
+#define AOSS_CC_LPASS_RESTART 6
+
+#endif
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 15%]
* [PATCH 2/6] dt-bindings: mailbox: Add APCS global binding for SDM845 SoCs
2018-03-05 9:53 13% [PATCH 0/6] Add support for remoteproc modem-pil on SDM845 SoCs sibis
2018-03-05 9:53 15% ` [PATCH 1/6] reset: qcom: AOSS (Always on subsystem) reset controller sibis
@ 2018-03-05 9:53 21% ` sibis
2018-03-07 21:55 0% ` Rob Herring
2018-03-05 9:53 21% ` [PATCH 3/6] mailbox: Add support for Qualcomm " sibis
` (3 subsequent siblings)
5 siblings, 1 reply; 200+ results
From: sibis @ 2018-03-05 9:53 UTC (permalink / raw)
To: bjorn.andersson
Cc: linux-remoteproc, linux-kernel, devicetree, sibis, georgi.djakov,
jassisinghbrar, p.zabel, ohad, mark.rutland, robh+dt, kyan,
sricharan, akdwived, linux-arm-msm
Include SDM845 APCS binding to the list of possible bindings
Signed-off-by: sibis <sibis@codeaurora.org>
---
Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt
index 16964f0..a60d2b2 100644
--- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt
+++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt
@@ -9,7 +9,8 @@ platforms.
Value type: <string>
Definition: must be one of:
"qcom,msm8916-apcs-kpss-global",
- "qcom,msm8996-apcs-hmss-global"
+ "qcom,msm8996-apcs-hmss-global",
+ "qcom,sdm845-apcs-hmss-global"
- reg:
Usage: required
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 21%]
* [PATCH 3/6] mailbox: Add support for Qualcomm SDM845 SoCs
2018-03-05 9:53 13% [PATCH 0/6] Add support for remoteproc modem-pil on SDM845 SoCs sibis
2018-03-05 9:53 15% ` [PATCH 1/6] reset: qcom: AOSS (Always on subsystem) reset controller sibis
2018-03-05 9:53 21% ` [PATCH 2/6] dt-bindings: mailbox: Add APCS global binding for SDM845 SoCs sibis
@ 2018-03-05 9:53 21% ` sibis
2018-03-05 9:53 21% ` [PATCH 4/6] dt-bindings: remoteproc: Add Q6v5 Modem PIL binding for SDM845 sibis
` (2 subsequent siblings)
5 siblings, 0 replies; 200+ results
From: sibis @ 2018-03-05 9:53 UTC (permalink / raw)
To: bjorn.andersson
Cc: linux-remoteproc, linux-kernel, devicetree, sibis, georgi.djakov,
jassisinghbrar, p.zabel, ohad, mark.rutland, robh+dt, kyan,
sricharan, akdwived, linux-arm-msm
Add the corresponding APCS offset for SDM845 SoC
Signed-off-by: sibis <sibis@codeaurora.org>
---
drivers/mailbox/qcom-apcs-ipc-mailbox.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
index 57bde0d..62d704d 100644
--- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c
+++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
@@ -125,6 +125,7 @@ static int qcom_apcs_ipc_remove(struct platform_device *pdev)
static const struct of_device_id qcom_apcs_ipc_of_match[] = {
{ .compatible = "qcom,msm8916-apcs-kpss-global", .data = (void *)8 },
{ .compatible = "qcom,msm8996-apcs-hmss-global", .data = (void *)16 },
+ { .compatible = "qcom,sdm845-apcs-hmss-global", .data = (void *)12 },
{}
};
MODULE_DEVICE_TABLE(of, qcom_apcs_ipc_of_match);
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 21%]
* [PATCH 4/6] dt-bindings: remoteproc: Add Q6v5 Modem PIL binding for SDM845
2018-03-05 9:53 13% [PATCH 0/6] Add support for remoteproc modem-pil on SDM845 SoCs sibis
` (2 preceding siblings ...)
2018-03-05 9:53 21% ` [PATCH 3/6] mailbox: Add support for Qualcomm " sibis
@ 2018-03-05 9:53 21% ` sibis
2018-03-07 21:56 0% ` Rob Herring
2018-03-05 9:53 18% ` [PATCH 5/6] remoteproc: qcom: Add support for mss remoteproc on SDM845 sibis
2018-03-05 9:53 17% ` [PATCH 6/6] remoteproc: qcom: Always assert and deassert reset signals in SDM845 sibis
5 siblings, 1 reply; 200+ results
From: sibis @ 2018-03-05 9:53 UTC (permalink / raw)
To: bjorn.andersson
Cc: linux-remoteproc, linux-kernel, devicetree, sibis, georgi.djakov,
jassisinghbrar, p.zabel, ohad, mark.rutland, robh+dt, kyan,
sricharan, akdwived, linux-arm-msm
Add new compatible string for Qualcomm SDM845 SoCs
Signed-off-by: sibis <sibis@codeaurora.org>
---
Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
index 00d3d58..11907db 100644
--- a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
+++ b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
@@ -9,8 +9,9 @@ on the Qualcomm Hexagon core.
Definition: must be one of:
"qcom,q6v5-pil",
"qcom,msm8916-mss-pil",
- "qcom,msm8974-mss-pil"
- "qcom,msm8996-mss-pil"
+ "qcom,msm8974-mss-pil",
+ "qcom,msm8996-mss-pil",
+ "qcom,sdm845-mss-pil"
- reg:
Usage: required
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 21%]
* [PATCH 5/6] remoteproc: qcom: Add support for mss remoteproc on SDM845
2018-03-05 9:53 13% [PATCH 0/6] Add support for remoteproc modem-pil on SDM845 SoCs sibis
` (3 preceding siblings ...)
2018-03-05 9:53 21% ` [PATCH 4/6] dt-bindings: remoteproc: Add Q6v5 Modem PIL binding for SDM845 sibis
@ 2018-03-05 9:53 18% ` sibis
2018-03-05 9:53 17% ` [PATCH 6/6] remoteproc: qcom: Always assert and deassert reset signals in SDM845 sibis
5 siblings, 0 replies; 200+ results
From: sibis @ 2018-03-05 9:53 UTC (permalink / raw)
To: bjorn.andersson
Cc: linux-remoteproc, linux-kernel, devicetree, sibis, georgi.djakov,
jassisinghbrar, p.zabel, ohad, mark.rutland, robh+dt, kyan,
sricharan, akdwived, linux-arm-msm
>From SDM845, the Q6SS reset sequence on software side has been
simplified with the introduction of boot FSM which assists in
bringing the Q6 out of reset
Add GLINK subdevice to allow definition of GLINK edge as a
child of modem-pil
Signed-off-by: sibis <sibis@codeaurora.org>
---
drivers/remoteproc/qcom_q6v5_pil.c | 65 +++++++++++++++++++++++++++++++++++++-
1 file changed, 64 insertions(+), 1 deletion(-)
diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
index b4e5e72..92bf125 100644
--- a/drivers/remoteproc/qcom_q6v5_pil.c
+++ b/drivers/remoteproc/qcom_q6v5_pil.c
@@ -57,6 +57,8 @@
#define RMB_PMI_META_DATA_REG 0x10
#define RMB_PMI_CODE_START_REG 0x14
#define RMB_PMI_CODE_LENGTH_REG 0x18
+#define RMB_MBA_MSS_STATUS 0x40
+#define RMB_MBA_ALT_RESET 0x44
#define RMB_CMD_META_DATA_READY 0x1
#define RMB_CMD_LOAD_READY 0x2
@@ -104,6 +106,13 @@
#define QDSP6SS_XO_CBCR 0x0038
#define QDSP6SS_ACC_OVERRIDE_VAL 0x20
+/* QDSP6v65 parameters */
+#define QDSP6SS_SLEEP 0x3C
+#define QDSP6SS_BOOT_CORE_START 0x400
+#define QDSP6SS_BOOT_CMD 0x404
+#define SLEEP_CHECK_MAX_LOOPS 200
+#define BOOT_FSM_TIMEOUT 10000
+
struct reg_info {
struct regulator *reg;
int uV;
@@ -166,6 +175,7 @@ struct q6v5 {
void *mpss_region;
size_t mpss_size;
+ struct qcom_rproc_glink glink_subdev;
struct qcom_rproc_subdev smd_subdev;
struct qcom_rproc_ssr ssr_subdev;
bool need_mem_protection;
@@ -178,6 +188,7 @@ enum {
MSS_MSM8916,
MSS_MSM8974,
MSS_MSM8996,
+ MSS_SDM845,
};
static int q6v5_regulator_init(struct device *dev, struct reg_info *regs,
@@ -384,8 +395,35 @@ static int q6v5proc_reset(struct q6v5 *qproc)
int ret;
int i;
+ if (qproc->version == MSS_SDM845) {
- if (qproc->version == MSS_MSM8996) {
+ val = readl(qproc->reg_base + QDSP6SS_SLEEP);
+ val |= 0x1;
+ writel(val, qproc->reg_base + QDSP6SS_SLEEP);
+
+ ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_SLEEP,
+ val, !(val & BIT(31)), 1,
+ SLEEP_CHECK_MAX_LOOPS);
+ if (ret) {
+ dev_err(qproc->dev, "QDSP6SS Sleep clock timed out\n");
+ return -ETIMEDOUT;
+ }
+
+ /* De-assert QDSP6 stop core */
+ writel(1, qproc->reg_base + QDSP6SS_BOOT_CORE_START);
+ /* Trigger boot FSM */
+ writel(1, qproc->reg_base + QDSP6SS_BOOT_CMD);
+
+ ret = readl_poll_timeout(qproc->rmb_base + RMB_MBA_MSS_STATUS,
+ val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT);
+ if (ret) {
+ dev_err(qproc->dev, "Boot FSM failed to complete.\n");
+ return ret;
+ }
+
+ goto pbl_wait;
+
+ } else if (qproc->version == MSS_MSM8996) {
/* Override the ACC value if required */
writel(QDSP6SS_ACC_OVERRIDE_VAL,
qproc->reg_base + QDSP6SS_STRAP_ACC);
@@ -493,6 +531,7 @@ static int q6v5proc_reset(struct q6v5 *qproc)
val &= ~Q6SS_STOP_CORE;
writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
+pbl_wait:
/* Wait for PBL status */
ret = q6v5_rmb_pbl_wait(qproc, 1000);
if (ret == -ETIMEDOUT) {
@@ -1213,6 +1252,7 @@ static int q6v5_probe(struct platform_device *pdev)
}
qproc->mpss_perm = BIT(QCOM_SCM_VMID_HLOS);
qproc->mba_perm = BIT(QCOM_SCM_VMID_HLOS);
+ qcom_add_glink_subdev(rproc, &qproc->glink_subdev);
qcom_add_smd_subdev(rproc, &qproc->smd_subdev);
qcom_add_ssr_subdev(rproc, &qproc->ssr_subdev, "mpss");
@@ -1234,6 +1274,7 @@ static int q6v5_remove(struct platform_device *pdev)
rproc_del(qproc->rproc);
+ qcom_remove_glink_subdev(qproc->rproc, &qproc->glink_subdev);
qcom_remove_smd_subdev(qproc->rproc, &qproc->smd_subdev);
qcom_remove_ssr_subdev(qproc->rproc, &qproc->ssr_subdev);
rproc_free(qproc->rproc);
@@ -1241,6 +1282,27 @@ static int q6v5_remove(struct platform_device *pdev)
return 0;
}
+static const struct rproc_hexagon_res sdm845_mss = {
+ .hexagon_mba_image = "mba.mbn",
+ .proxy_clk_names = (char*[]){
+ "xo",
+ "axis2",
+ "prng",
+ NULL
+ },
+ .active_clk_names = (char*[]){
+ "iface",
+ "bus",
+ "mem",
+ "gpll0_mss",
+ "snoc_axi",
+ "mnoc_axi",
+ NULL
+ },
+ .need_mem_protection = true,
+ .version = MSS_SDM845,
+};
+
static const struct rproc_hexagon_res msm8996_mss = {
.hexagon_mba_image = "mba.mbn",
.proxy_clk_names = (char*[]){
@@ -1334,6 +1396,7 @@ static int q6v5_remove(struct platform_device *pdev)
{ .compatible = "qcom,msm8916-mss-pil", .data = &msm8916_mss},
{ .compatible = "qcom,msm8974-mss-pil", .data = &msm8974_mss},
{ .compatible = "qcom,msm8996-mss-pil", .data = &msm8996_mss},
+ { .compatible = "qcom,sdm845-mss-pil", .data = &sdm845_mss},
{ },
};
MODULE_DEVICE_TABLE(of, q6v5_of_match);
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 18%]
* [PATCH 6/6] remoteproc: qcom: Always assert and deassert reset signals in SDM845
2018-03-05 9:53 13% [PATCH 0/6] Add support for remoteproc modem-pil on SDM845 SoCs sibis
` (4 preceding siblings ...)
2018-03-05 9:53 18% ` [PATCH 5/6] remoteproc: qcom: Add support for mss remoteproc on SDM845 sibis
@ 2018-03-05 9:53 17% ` sibis
5 siblings, 0 replies; 200+ results
From: sibis @ 2018-03-05 9:53 UTC (permalink / raw)
To: bjorn.andersson
Cc: linux-remoteproc, linux-kernel, devicetree, sibis, georgi.djakov,
jassisinghbrar, p.zabel, ohad, mark.rutland, robh+dt, kyan,
sricharan, akdwived, linux-arm-msm
SDM845 brings a new reset signal ALT_RESET which is a part of the MSS
subsystem hence requires some of the active clks to be enabled before
assert/deassert
Reset the modem if the BOOT FSM does timeout
Reset assert/deassert sequence vary across SoCs adding reset, adding
start/stop helper functions to handle SoC specific reset sequences
Signed-off-by: sibis <sibis@codeaurora.org>
---
drivers/remoteproc/qcom_q6v5_pil.c | 100 ++++++++++++++++++++++++++++++++++---
1 file changed, 94 insertions(+), 6 deletions(-)
diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
index 92bf125..bd8c397 100644
--- a/drivers/remoteproc/qcom_q6v5_pil.c
+++ b/drivers/remoteproc/qcom_q6v5_pil.c
@@ -130,11 +130,14 @@ struct rproc_hexagon_res {
struct qcom_mss_reg_res *proxy_supply;
struct qcom_mss_reg_res *active_supply;
char **proxy_clk_names;
+ char **reset_clk_names;
char **active_clk_names;
int version;
bool need_mem_protection;
};
+struct q6v5_reset_ops;
+
struct q6v5 {
struct device *dev;
struct rproc *rproc;
@@ -153,8 +156,10 @@ struct q6v5 {
unsigned stop_bit;
struct clk *active_clks[8];
+ struct clk *reset_clks[4];
struct clk *proxy_clks[4];
int active_clk_count;
+ int reset_clk_count;
int proxy_clk_count;
struct reg_info active_regs[1];
@@ -175,6 +180,7 @@ struct q6v5 {
void *mpss_region;
size_t mpss_size;
+ const struct q6v5_reset_ops *ops;
struct qcom_rproc_glink glink_subdev;
struct qcom_rproc_subdev smd_subdev;
struct qcom_rproc_ssr ssr_subdev;
@@ -184,6 +190,11 @@ struct q6v5 {
int version;
};
+struct q6v5_reset_ops {
+ int (*reset_start)(struct q6v5 *qproc);
+ int (*reset_stop)(struct q6v5 *qproc);
+};
+
enum {
MSS_MSM8916,
MSS_MSM8974,
@@ -343,6 +354,52 @@ static int q6v5_load(struct rproc *rproc, const struct firmware *fw)
return 0;
}
+static void alt_reset_restart(struct q6v5 *qproc, u32 restart)
+{
+ writel(restart, qproc->rmb_base + RMB_MBA_ALT_RESET);
+}
+
+static int q6v5_msm_reset_stop(struct q6v5 *qproc)
+{
+ return reset_control_assert(qproc->mss_restart);
+}
+
+static int q6v5_msm_reset_start(struct q6v5 *qproc)
+{
+ return reset_control_deassert(qproc->mss_restart);
+}
+
+static int q6v5_sdm_reset_stop(struct q6v5 *qproc)
+{
+ return reset_control_reset(qproc->mss_restart);
+}
+
+static int q6v5_sdm_reset_start(struct q6v5 *qproc)
+{
+ int ret;
+
+ alt_reset_restart(qproc, 1);
+ /* Ensure alt reset is written before restart reg */
+ udelay(100);
+
+ ret = reset_control_reset(qproc->mss_restart);
+
+ udelay(100);
+ alt_reset_restart(qproc, 0);
+
+ return ret;
+}
+
+static const struct q6v5_reset_ops q6v5_msm_ops = {
+ .reset_stop = q6v5_msm_reset_stop,
+ .reset_start = q6v5_msm_reset_start,
+};
+
+static const struct q6v5_reset_ops q6v5_sdm_ops = {
+ .reset_stop = q6v5_sdm_reset_stop,
+ .reset_start = q6v5_sdm_reset_start,
+};
+
static int q6v5_rmb_pbl_wait(struct q6v5 *qproc, int ms)
{
unsigned long timeout;
@@ -418,6 +475,8 @@ static int q6v5proc_reset(struct q6v5 *qproc)
val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT);
if (ret) {
dev_err(qproc->dev, "Boot FSM failed to complete.\n");
+ /* Reset the modem so that boot FSM is in reset state */
+ qproc->ops->reset_start(qproc);
return ret;
}
@@ -785,10 +844,18 @@ static int q6v5_start(struct rproc *rproc)
dev_err(qproc->dev, "failed to enable supplies\n");
goto disable_proxy_clk;
}
- ret = reset_control_deassert(qproc->mss_restart);
+
+ ret = q6v5_clk_enable(qproc->dev, qproc->reset_clks,
+ qproc->reset_clk_count);
+ if (ret) {
+ dev_err(qproc->dev, "failed to enable reset clocks\n");
+ goto disable_vdd;
+ }
+
+ ret = qproc->ops->reset_start(qproc);
if (ret) {
dev_err(qproc->dev, "failed to deassert mss restart\n");
- goto disable_vdd;
+ goto disable_reset_clks;
}
ret = q6v5_clk_enable(qproc->dev, qproc->active_clks,
@@ -880,7 +947,10 @@ static int q6v5_start(struct rproc *rproc)
qproc->active_clk_count);
assert_reset:
- reset_control_assert(qproc->mss_restart);
+ qproc->ops->reset_stop(qproc);
+disable_reset_clks:
+ q6v5_clk_disable(qproc->dev, qproc->reset_clks,
+ qproc->reset_clk_count);
disable_vdd:
q6v5_regulator_disable(qproc, qproc->active_regs,
qproc->active_reg_count);
@@ -930,9 +1000,11 @@ static int q6v5_stop(struct rproc *rproc)
qproc->mpss_phys, qproc->mpss_size);
WARN_ON(ret);
- reset_control_assert(qproc->mss_restart);
+ qproc->ops->reset_stop(qproc);
q6v5_clk_disable(qproc->dev, qproc->active_clks,
qproc->active_clk_count);
+ q6v5_clk_disable(qproc->dev, qproc->reset_clks,
+ qproc->reset_clk_count);
q6v5_regulator_disable(qproc, qproc->active_regs,
qproc->active_reg_count);
@@ -1179,6 +1251,12 @@ static int q6v5_probe(struct platform_device *pdev)
qproc->dev = &pdev->dev;
qproc->rproc = rproc;
platform_set_drvdata(pdev, qproc);
+ qproc->version = desc->version;
+
+ if (qproc->version == MSS_SDM845)
+ qproc->ops = &q6v5_sdm_ops;
+ else
+ qproc->ops = &q6v5_msm_ops;
init_completion(&qproc->start_done);
init_completion(&qproc->stop_done);
@@ -1199,6 +1277,14 @@ static int q6v5_probe(struct platform_device *pdev)
}
qproc->proxy_clk_count = ret;
+ ret = q6v5_init_clocks(&pdev->dev, qproc->reset_clks,
+ desc->reset_clk_names);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "Failed to get reset clocks.\n");
+ goto free_rproc;
+ }
+ qproc->reset_clk_count = ret;
+
ret = q6v5_init_clocks(&pdev->dev, qproc->active_clks,
desc->active_clk_names);
if (ret < 0) {
@@ -1227,7 +1313,6 @@ static int q6v5_probe(struct platform_device *pdev)
if (ret)
goto free_rproc;
- qproc->version = desc->version;
qproc->need_mem_protection = desc->need_mem_protection;
ret = q6v5_request_irq(qproc, pdev, "wdog", q6v5_wdog_interrupt);
if (ret < 0)
@@ -1290,8 +1375,11 @@ static int q6v5_remove(struct platform_device *pdev)
"prng",
NULL
},
- .active_clk_names = (char*[]){
+ .reset_clk_names = (char*[]){
"iface",
+ NULL
+ },
+ .active_clk_names = (char*[]){
"bus",
"mem",
"gpll0_mss",
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 17%]
* Re: [PATCH 1/6] reset: qcom: AOSS (Always on subsystem) reset controller
2018-03-05 9:53 15% ` [PATCH 1/6] reset: qcom: AOSS (Always on subsystem) reset controller sibis
@ 2018-03-07 21:35 0% ` Rob Herring
2018-03-09 14:55 6% ` Sibi S
0 siblings, 1 reply; 200+ results
From: Rob Herring @ 2018-03-07 21:35 UTC (permalink / raw)
To: sibis
Cc: bjorn.andersson, linux-remoteproc, linux-kernel, devicetree,
georgi.djakov, jassisinghbrar, p.zabel, ohad, mark.rutland, kyan,
sricharan, akdwived, linux-arm-msm
On Mon, Mar 05, 2018 at 03:23:28PM +0530, sibis wrote:
> Add reset controller driver for Qualcomm SDM845 SoC to
> control reset signals provided by AOSS for Modem, Venus
> ADSP, GPU, Camera, Wireless, Display subsystem
>
> Signed-off-by: sibis <sibis@codeaurora.org>
Need a full name here.
> ---
> .../devicetree/bindings/reset/qcom,aoss-reset.txt | 54 ++++++++
Separate patch for bindings (with the header) please.
> drivers/reset/Kconfig | 10 ++
> drivers/reset/Makefile | 1 +
> drivers/reset/reset-qcom-aoss.c | 151 +++++++++++++++++++++
> include/dt-bindings/reset/qcom,aoss-sdm845.h | 17 +++
> 5 files changed, 233 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
> create mode 100644 drivers/reset/reset-qcom-aoss.c
> create mode 100644 include/dt-bindings/reset/qcom,aoss-sdm845.h
>
> diff --git a/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
> new file mode 100644
> index 0000000..5318e14
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
> @@ -0,0 +1,54 @@
> +Qualcomm AOSS Reset Controller
> +======================================
> +
> +This binding describes a reset-controller found on AOSS (Always on SubSysem)
> +for Qualcomm SDM845 SoCs.
> +
> +Required properties:
> +- compatible:
> + Usage: required
> + Value type: <string>
> + Definition: must be:
> + "qcom,aoss-reset-sdm845", "syscon"
Someone in QCom needs to go fix the order of all your downstream
compatibles or review your bindings before sending upstream. The
standard ordering is <vendor>,<soc>-<block>.
Why syscon? The description is this is just a reset controller.
> +
> +- reg:
> + Usage: required
> + Value type: <prop-encoded-array>
> + Definition: must specify the base address and size of the
> + syscon device.
> +
> +
> +- #reset-cells:
> + Usage: required
> + Value type: <uint>
> + Definition: must be 1; cell entry represents the reset index.
> +
> +example:
> +
> +aoss_reset: qcom,reset-controller@b2e0100 {
> + compatible = "qcom,aoss-reset-sdm845", "syscon";
> + reg = <0xc2b0000 0x20004>;
> + #reset-cells = <1>;
> +};
> +
> +
> +Specifying reset lines connected to IP modules
> +==============================================
> +
> +Device nodes that need access to reset lines should
> +specify them as a reset phandle in their corresponding node as
> +specified in reset.txt.
> +
> +Example:
> +
> + modem-pil@4080000 {
> + ...
> +
> + resets = <&aoss_reset AOSS_CC_MSS_RESTART>;
> + reset-names = "mss_restart";
> +
> + ...
> + };
> +
> +For list of all valid reset indicies see
> +<dt-bindings/reset/qcom,aoss-sdm845.h>
Put this before the example.
^ permalink raw reply [relevance 0%]
* Re: [PATCH 2/6] dt-bindings: mailbox: Add APCS global binding for SDM845 SoCs
2018-03-05 9:53 21% ` [PATCH 2/6] dt-bindings: mailbox: Add APCS global binding for SDM845 SoCs sibis
@ 2018-03-07 21:55 0% ` Rob Herring
0 siblings, 0 replies; 200+ results
From: Rob Herring @ 2018-03-07 21:55 UTC (permalink / raw)
To: sibis
Cc: bjorn.andersson, linux-remoteproc, linux-kernel, devicetree,
georgi.djakov, jassisinghbrar, p.zabel, ohad, mark.rutland, kyan,
sricharan, akdwived, linux-arm-msm
On Mon, Mar 05, 2018 at 03:23:29PM +0530, sibis wrote:
> Include SDM845 APCS binding to the list of possible bindings
>
> Signed-off-by: sibis <sibis@codeaurora.org>
Need a full name.
> ---
> Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt
> index 16964f0..a60d2b2 100644
> --- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt
> +++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt
> @@ -9,7 +9,8 @@ platforms.
> Value type: <string>
> Definition: must be one of:
> "qcom,msm8916-apcs-kpss-global",
> - "qcom,msm8996-apcs-hmss-global"
> + "qcom,msm8996-apcs-hmss-global",
> + "qcom,sdm845-apcs-hmss-global"
Drop the comma so we can have 1 line changes instead of 3 in the
future.
>
> - reg:
> Usage: required
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
^ permalink raw reply [relevance 0%]
* Re: [PATCH 4/6] dt-bindings: remoteproc: Add Q6v5 Modem PIL binding for SDM845
2018-03-05 9:53 21% ` [PATCH 4/6] dt-bindings: remoteproc: Add Q6v5 Modem PIL binding for SDM845 sibis
@ 2018-03-07 21:56 0% ` Rob Herring
0 siblings, 0 replies; 200+ results
From: Rob Herring @ 2018-03-07 21:56 UTC (permalink / raw)
To: sibis
Cc: bjorn.andersson, linux-remoteproc, linux-kernel, devicetree,
georgi.djakov, jassisinghbrar, p.zabel, ohad, mark.rutland, kyan,
sricharan, akdwived, linux-arm-msm
On Mon, Mar 05, 2018 at 03:23:31PM +0530, sibis wrote:
> Add new compatible string for Qualcomm SDM845 SoCs
>
> Signed-off-by: sibis <sibis@codeaurora.org>
Full name.
> ---
> Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
> index 00d3d58..11907db 100644
> --- a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
> +++ b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
> @@ -9,8 +9,9 @@ on the Qualcomm Hexagon core.
> Definition: must be one of:
> "qcom,q6v5-pil",
> "qcom,msm8916-mss-pil",
> - "qcom,msm8974-mss-pil"
> - "qcom,msm8996-mss-pil"
> + "qcom,msm8974-mss-pil",
> + "qcom,msm8996-mss-pil",
> + "qcom,sdm845-mss-pil"
Drop the comma.
>
> - reg:
> Usage: required
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
^ permalink raw reply [relevance 0%]
* Re: [PATCH 1/6] reset: qcom: AOSS (Always on subsystem) reset controller
2018-03-07 21:35 0% ` Rob Herring
@ 2018-03-09 14:55 6% ` Sibi S
0 siblings, 1 reply; 200+ results
From: Sibi S @ 2018-03-09 14:55 UTC (permalink / raw)
To: Rob Herring
Cc: bjorn.andersson, linux-remoteproc, linux-kernel, devicetree,
georgi.djakov, jassisinghbrar, p.zabel, ohad, mark.rutland, kyan,
sricharan, akdwived, linux-arm-msm
Hi Rob,
Thanks for the review, will add the changes in v3 of the patch series
On 03/08/2018 03:05 AM, Rob Herring wrote:
> On Mon, Mar 05, 2018 at 03:23:28PM +0530, sibis wrote:
>> Add reset controller driver for Qualcomm SDM845 SoC to
>> control reset signals provided by AOSS for Modem, Venus
>> ADSP, GPU, Camera, Wireless, Display subsystem
>>
>> Signed-off-by: sibis <sibis@codeaurora.org>
>
> Need a full name here.
>
Will correct it
>> ---
>> .../devicetree/bindings/reset/qcom,aoss-reset.txt | 54 ++++++++
>
> Separate patch for bindings (with the header) please.
>
Will make a separate patch
>> drivers/reset/Kconfig | 10 ++
>> drivers/reset/Makefile | 1 +
>> drivers/reset/reset-qcom-aoss.c | 151 +++++++++++++++++++++
>> include/dt-bindings/reset/qcom,aoss-sdm845.h | 17 +++
>> 5 files changed, 233 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
>> create mode 100644 drivers/reset/reset-qcom-aoss.c
>> create mode 100644 include/dt-bindings/reset/qcom,aoss-sdm845.h
>>
>> diff --git a/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
>> new file mode 100644
>> index 0000000..5318e14
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
>> @@ -0,0 +1,54 @@
>> +Qualcomm AOSS Reset Controller
>> +======================================
>> +
>> +This binding describes a reset-controller found on AOSS (Always on SubSysem)
>> +for Qualcomm SDM845 SoCs.
>> +
>> +Required properties:
>> +- compatible:
>> + Usage: required
>> + Value type: <string>
>> + Definition: must be:
>> + "qcom,aoss-reset-sdm845", "syscon"
>
> Someone in QCom needs to go fix the order of all your downstream
> compatibles or review your bindings before sending upstream. The
> standard ordering is <vendor>,<soc>-<block>.
>
Will correct it.
> Why syscon? The description is this is just a reset controller.
>
syscon was needed in the compatible list due to using
syscon_node_to_regmap in the reset driver but I guess
since it is just a reset controller the correct thing to do
be ioremap the reg space and do devm_regmap_init_mmio on it.
Will remove syscon.
>> +
>> +- reg:
>> + Usage: required
>> + Value type: <prop-encoded-array>
>> + Definition: must specify the base address and size of the
>> + syscon device.
>> +
>> +
>> +- #reset-cells:
>> + Usage: required
>> + Value type: <uint>
>> + Definition: must be 1; cell entry represents the reset index.
>> +
>> +example:
>> +
>> +aoss_reset: qcom,reset-controller@b2e0100 {
>> + compatible = "qcom,aoss-reset-sdm845", "syscon";
>> + reg = <0xc2b0000 0x20004>;
>> + #reset-cells = <1>;
>> +};
>> +
>> +
>> +Specifying reset lines connected to IP modules
>> +==============================================
>> +
>> +Device nodes that need access to reset lines should
>> +specify them as a reset phandle in their corresponding node as
>> +specified in reset.txt.
>> +
>> +Example:
>> +
>> + modem-pil@4080000 {
>> + ...
>> +
>> + resets = <&aoss_reset AOSS_CC_MSS_RESTART>;
>> + reset-names = "mss_restart";
>> +
>> + ...
>> + };
>> +
>> +For list of all valid reset indicies see
>> +<dt-bindings/reset/qcom,aoss-sdm845.h>
>
> Put this before the example.
>
ok
> --
> To unsubscribe from this list: send the line "unsubscribe linux-remoteproc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
--
Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc, is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [relevance 6%]
* Re: [PATCH 1/6] reset: qcom: AOSS (Always on subsystem) reset controller
@ 2018-03-12 7:01 6% ` Sibi S
0 siblings, 0 replies; 200+ results
From: Sibi S @ 2018-03-12 7:01 UTC (permalink / raw)
To: Trilok Soni, Rob Herring
Cc: bjorn.andersson, linux-remoteproc, linux-kernel, devicetree,
georgi.djakov, jassisinghbrar, p.zabel, ohad, mark.rutland, kyan,
sricharan, akdwived, linux-arm-msm
Hi Trilok,
Thanks for the review. I will include it in the v3 patch series.
On 03/10/2018 02:59 AM, Trilok Soni wrote:
> Sibi,
>
> One cosmetic comment below.
>
> On 3/9/2018 6:55 AM, Sibi S wrote:
>> +
>>>> +This binding describes a reset-controller found on AOSS (Always on
>>>> SubSysem)
>>>> +for Qualcomm SDM845 SoCs.
>
> S/SubSysem/Subsytem
>
Will correct it
> ---Trilok Soni
>
>
>
--
Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc, is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [relevance 6%]
* [PATCH v3 0/7] Add support for remoteproc modem-pil on SDM845 SoCs
@ 2018-03-14 9:21 11% Sibi S
2018-03-14 9:21 17% ` [PATCH v3 1/7] dt-bindings: reset: Add AOSS reset bindings for " Sibi S
` (6 more replies)
0 siblings, 7 replies; 200+ results
From: Sibi S @ 2018-03-14 9:21 UTC (permalink / raw)
To: bjorn.andersson, p.zabel, robh+dt
Cc: linux-remoteproc, linux-kernel, devicetree, sibis, georgi.djakov,
jassisinghbrar, ohad, mark.rutland, kyan, sricharan, akdwived,
linux-arm-msm, tsoni
This patch series add support for remoteproc Q6v5 modem-pil on Qualcomm
SDM845 SoC. The second patch adds AOSS (Always on subsystem) reset driver
to provide for mss reset line. The fourth patch adds the APCS offset for
SDM845. The last couple of patches add the resets sequence for Q6 on
SDM845 and adds helper functions for arbitrary reset assert/deassert
sequences.
V3:
Removed syscon dependency for the aoss reset driver
Split dt-bindings and the aoss reset driver into separate patches
Corrected few typos and replaced misconfigured author name
V2:
Addressed reset-qcom-aoss review suggestions and reworked
re-ordering of the active clk and reset sequence in
qcom_q6v5_pil
Sibi S (7):
dt-bindings: reset: Add AOSS reset bindings for SDM845 SoCs
reset: qcom: AOSS (always on subsystem) reset controller
dt-bindings: mailbox: Add APCS global binding for SDM845 SoCs
mailbox: Add support for Qualcomm SDM845 SoCs
dt-bindings: remoteproc: Add Q6v5 Modem PIL binding for SDM845
remoteproc: qcom: Add support for mss remoteproc on SDM845
remoteproc: qcom: Always assert and deassert reset signals in SDM845
.../bindings/mailbox/qcom,apcs-kpss-global.txt | 1 +
.../devicetree/bindings/remoteproc/qcom,q6v5.txt | 1 +
.../devicetree/bindings/reset/qcom,aoss-reset.txt | 54 +++++++
drivers/mailbox/qcom-apcs-ipc-mailbox.c | 1 +
drivers/remoteproc/qcom_q6v5_pil.c | 163 ++++++++++++++++++++-
drivers/reset/Kconfig | 10 ++
drivers/reset/Makefile | 1 +
drivers/reset/reset-qcom-aoss.c | 156 ++++++++++++++++++++
include/dt-bindings/reset/qcom,sdm845-aoss.h | 17 +++
9 files changed, 398 insertions(+), 6 deletions(-)
create mode 100644 Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
create mode 100644 drivers/reset/reset-qcom-aoss.c
create mode 100644 include/dt-bindings/reset/qcom,sdm845-aoss.h
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [relevance 11%]
* [PATCH v3 1/7] dt-bindings: reset: Add AOSS reset bindings for SDM845 SoCs
2018-03-14 9:21 11% [PATCH v3 0/7] Add support for remoteproc modem-pil on SDM845 SoCs Sibi S
@ 2018-03-14 9:21 17% ` Sibi S
2018-03-18 12:49 0% ` Rob Herring
2018-03-14 9:21 14% ` [PATCH v3 2/7] reset: qcom: AOSS (always on subsystem) reset controller Sibi S
` (5 subsequent siblings)
6 siblings, 2 replies; 200+ results
From: Sibi S @ 2018-03-14 9:21 UTC (permalink / raw)
To: bjorn.andersson, p.zabel, robh+dt
Cc: linux-remoteproc, linux-kernel, devicetree, sibis, georgi.djakov,
jassisinghbrar, ohad, mark.rutland, kyan, sricharan, akdwived,
linux-arm-msm, tsoni
Add SDM845 AOSS (always on subsystem) reset controller binding
Signed-off-by: Sibi S <sibis@codeaurora.org>
---
.../devicetree/bindings/reset/qcom,aoss-reset.txt | 54 ++++++++++++++++++++++
include/dt-bindings/reset/qcom,sdm845-aoss.h | 17 +++++++
2 files changed, 71 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
create mode 100644 include/dt-bindings/reset/qcom,sdm845-aoss.h
diff --git a/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
new file mode 100644
index 0000000..04dca76
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
@@ -0,0 +1,54 @@
+Qualcomm AOSS Reset Controller
+======================================
+
+This binding describes a reset-controller found on AOSS (always on subsystem)
+for Qualcomm SDM845 SoCs.
+
+Required properties:
+- compatible:
+ Usage: required
+ Value type: <string>
+ Definition: must be:
+ "qcom,sdm845-aoss-reset"
+
+- reg:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: must specify the base address and size of the register
+ space.
+
+
+- #reset-cells:
+ Usage: required
+ Value type: <uint>
+ Definition: must be 1; cell entry represents the reset index.
+
+example:
+
+aoss_reset: qcom,reset-controller@b2e0100 {
+ compatible = "qcom,sdm845-aoss-reset";
+ reg = <0xc2b0000 0x20004>;
+ #reset-cells = <1>;
+};
+
+
+Specifying reset lines connected to IP modules
+==============================================
+
+Device nodes that need access to reset lines should
+specify them as a reset phandle in their corresponding node as
+specified in reset.txt.
+
+For list of all valid reset indicies see
+<dt-bindings/reset/qcom,sdm845-aoss.h>
+
+Example:
+
+modem-pil@4080000 {
+ ...
+
+ resets = <&aoss_reset AOSS_CC_MSS_RESTART>;
+ reset-names = "mss_restart";
+
+ ...
+};
diff --git a/include/dt-bindings/reset/qcom,sdm845-aoss.h b/include/dt-bindings/reset/qcom,sdm845-aoss.h
new file mode 100644
index 0000000..e9b38fc
--- /dev/null
+++ b/include/dt-bindings/reset/qcom,sdm845-aoss.h
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_RESET_AOSS_SDM_845_H
+#define _DT_BINDINGS_RESET_AOSS_SDM_845_H
+
+#define AOSS_CC_MSS_RESTART 0
+#define AOSS_CC_CAMSS_RESTART 1
+#define AOSS_CC_VENUS_RESTART 2
+#define AOSS_CC_GPU_RESTART 3
+#define AOSS_CC_DISPSS_RESTART 4
+#define AOSS_CC_WCSS_RESTART 5
+#define AOSS_CC_LPASS_RESTART 6
+
+#endif
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 17%]
* [PATCH v3 2/7] reset: qcom: AOSS (always on subsystem) reset controller
2018-03-14 9:21 11% [PATCH v3 0/7] Add support for remoteproc modem-pil on SDM845 SoCs Sibi S
2018-03-14 9:21 17% ` [PATCH v3 1/7] dt-bindings: reset: Add AOSS reset bindings for " Sibi S
@ 2018-03-14 9:21 14% ` Sibi S
2018-03-14 10:48 0% ` Vivek Gautam
2018-03-14 9:21 19% ` [PATCH v3 3/7] dt-bindings: mailbox: Add APCS global binding for SDM845 SoCs Sibi S
` (4 subsequent siblings)
6 siblings, 2 replies; 200+ results
From: Sibi S @ 2018-03-14 9:21 UTC (permalink / raw)
To: bjorn.andersson, p.zabel, robh+dt
Cc: linux-remoteproc, linux-kernel, devicetree, sibis, georgi.djakov,
jassisinghbrar, ohad, mark.rutland, kyan, sricharan, akdwived,
linux-arm-msm, tsoni
Add reset controller driver for Qualcomm SDM845 SoC to
control reset signals provided by AOSS for Modem, Venus
ADSP, GPU, Camera, Wireless, Display subsystem
Signed-off-by: Sibi S <sibis@codeaurora.org>
---
drivers/reset/Kconfig | 10 +++
drivers/reset/Makefile | 1 +
drivers/reset/reset-qcom-aoss.c | 156 ++++++++++++++++++++++++++++++++++++++++
3 files changed, 167 insertions(+)
create mode 100644 drivers/reset/reset-qcom-aoss.c
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 7fc7769..d06bd1d 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -81,6 +81,16 @@ config RESET_PISTACHIO
help
This enables the reset driver for ImgTec Pistachio SoCs.
+config RESET_QCOM_AOSS
+ bool "Qcom AOSS Reset Driver"
+ depends on ARCH_QCOM || COMPILE_TEST
+ select MFD_SYSCON
+ help
+ This enables the AOSS (always on subsystem) reset driver
+ for Qualcomm SDM845 SoCs. Say Y if you want to control
+ reset signals provided by AOSS for Modem, Venus, ADSP,
+ GPU, Camera, Wireless, Display subsystem. Otherwise, say N.
+
config RESET_SIMPLE
bool "Simple Reset Controller Driver" if COMPILE_TEST
default ARCH_SOCFPGA || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 132c24f..c30044a 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
obj-$(CONFIG_RESET_MESON) += reset-meson.o
obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o
+obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o
obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
diff --git a/drivers/reset/reset-qcom-aoss.c b/drivers/reset/reset-qcom-aoss.c
new file mode 100644
index 0000000..e70fb37
--- /dev/null
+++ b/drivers/reset/reset-qcom-aoss.c
@@ -0,0 +1,156 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+#include <linux/regmap.h>
+#include <linux/of_device.h>
+#include <dt-bindings/reset/qcom,sdm845-aoss.h>
+
+struct qcom_aoss_reset_map {
+ unsigned int reg;
+ u8 bit;
+};
+
+struct qcom_aoss_desc {
+ const struct regmap_config *config;
+ const struct qcom_aoss_reset_map *resets;
+ int delay;
+ size_t num_resets;
+};
+
+struct qcom_aoss_reset_data {
+ struct reset_controller_dev rcdev;
+ struct regmap *regmap;
+ const struct qcom_aoss_desc *desc;
+};
+
+static const struct regmap_config sdm845_aoss_regmap_config = {
+ .name = "aoss-reset",
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x20000,
+ .fast_io = true,
+};
+
+static const struct qcom_aoss_reset_map sdm845_aoss_resets[] = {
+ [AOSS_CC_MSS_RESTART] = { 0x0, 0 },
+ [AOSS_CC_CAMSS_RESTART] = { 0x1000, 0 },
+ [AOSS_CC_VENUS_RESTART] = { 0x2000, 0 },
+ [AOSS_CC_GPU_RESTART] = { 0x3000, 0 },
+ [AOSS_CC_DISPSS_RESTART] = { 0x4000, 0 },
+ [AOSS_CC_WCSS_RESTART] = { 0x10000, 0 },
+ [AOSS_CC_LPASS_RESTART] = { 0x20000, 0 },
+};
+
+static const struct qcom_aoss_desc sdm845_aoss_desc = {
+ .config = &sdm845_aoss_regmap_config,
+ .resets = sdm845_aoss_resets,
+ /* Wait 6 32kHz sleep cycles for reset */
+ .delay = 200,
+ .num_resets = ARRAY_SIZE(sdm845_aoss_resets),
+};
+
+static struct qcom_aoss_reset_data *to_qcom_aoss_reset_data(
+ struct reset_controller_dev *rcdev)
+{
+ return container_of(rcdev, struct qcom_aoss_reset_data, rcdev);
+}
+
+static int qcom_aoss_control_assert(struct reset_controller_dev *rcdev,
+ unsigned long idx)
+{
+ struct qcom_aoss_reset_data *data = to_qcom_aoss_reset_data(rcdev);
+ const struct qcom_aoss_reset_map *map = &data->desc->resets[idx];
+
+ return regmap_update_bits(data->regmap, map->reg,
+ BIT(map->bit), BIT(map->bit));
+}
+
+static int qcom_aoss_control_deassert(struct reset_controller_dev *rcdev,
+ unsigned long idx)
+{
+ struct qcom_aoss_reset_data *data = to_qcom_aoss_reset_data(rcdev);
+ const struct qcom_aoss_reset_map *map = &data->desc->resets[idx];
+
+ return regmap_update_bits(data->regmap, map->reg, BIT(map->bit), 0);
+}
+
+static int qcom_aoss_control_reset(struct reset_controller_dev *rcdev,
+ unsigned long idx)
+{
+ struct qcom_aoss_reset_data *data = to_qcom_aoss_reset_data(rcdev);
+ int ret;
+
+ ret = qcom_aoss_control_assert(rcdev, idx);
+ if (ret)
+ return ret;
+
+ udelay(data->desc->delay);
+
+ return qcom_aoss_control_deassert(rcdev, idx);
+}
+
+static const struct reset_control_ops qcom_aoss_reset_ops = {
+ .reset = qcom_aoss_control_reset,
+ .assert = qcom_aoss_control_assert,
+ .deassert = qcom_aoss_control_deassert,
+};
+
+static int qcom_aoss_reset_probe(struct platform_device *pdev)
+{
+ struct qcom_aoss_reset_data *data;
+ struct device *dev = &pdev->dev;
+ const struct qcom_aoss_desc *desc;
+ void __iomem *base;
+ struct resource *res;
+
+ desc = of_device_get_match_data(dev);
+ if (!desc)
+ return -EINVAL;
+
+ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ data->desc = desc;
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ data->regmap = devm_regmap_init_mmio(dev, base, desc->config);
+ if (IS_ERR(data->regmap)) {
+ dev_err(dev, "Unable to get aoss-reset regmap");
+ return PTR_ERR(data->regmap);
+ }
+
+ data->rcdev.owner = THIS_MODULE;
+ data->rcdev.ops = &qcom_aoss_reset_ops;
+ data->rcdev.nr_resets = desc->num_resets;
+ data->rcdev.of_node = dev->of_node;
+
+ return devm_reset_controller_register(dev, &data->rcdev);
+}
+
+static const struct of_device_id qcom_aoss_reset_of_match[] = {
+ { .compatible = "qcom,sdm845-aoss-reset", .data = &sdm845_aoss_desc },
+ {}
+};
+
+static struct platform_driver qcom_aoss_reset_driver = {
+ .probe = qcom_aoss_reset_probe,
+ .driver = {
+ .name = "qcom_aoss_reset",
+ .of_match_table = qcom_aoss_reset_of_match,
+ },
+};
+
+builtin_platform_driver(qcom_aoss_reset_driver);
+
+MODULE_DESCRIPTION("Qualcomm AOSS Reset Driver");
+MODULE_LICENSE("GPL v2");
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 14%]
* [PATCH v3 3/7] dt-bindings: mailbox: Add APCS global binding for SDM845 SoCs
2018-03-14 9:21 11% [PATCH v3 0/7] Add support for remoteproc modem-pil on SDM845 SoCs Sibi S
2018-03-14 9:21 17% ` [PATCH v3 1/7] dt-bindings: reset: Add AOSS reset bindings for " Sibi S
2018-03-14 9:21 14% ` [PATCH v3 2/7] reset: qcom: AOSS (always on subsystem) reset controller Sibi S
@ 2018-03-14 9:21 19% ` Sibi S
2018-03-18 22:45 0% ` Bjorn Andersson
2018-03-14 9:21 19% ` [PATCH v3 4/7] mailbox: Add support for Qualcomm " Sibi S
` (3 subsequent siblings)
6 siblings, 1 reply; 200+ results
From: Sibi S @ 2018-03-14 9:21 UTC (permalink / raw)
To: bjorn.andersson, p.zabel, robh+dt
Cc: linux-remoteproc, linux-kernel, devicetree, sibis, georgi.djakov,
jassisinghbrar, ohad, mark.rutland, kyan, sricharan, akdwived,
linux-arm-msm, tsoni
Include SDM845 APCS binding to the list of possible bindings
Signed-off-by: Sibi S <sibis@codeaurora.org>
---
Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt
index 16964f0..6a7e5d8 100644
--- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt
+++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt
@@ -10,6 +10,7 @@ platforms.
Definition: must be one of:
"qcom,msm8916-apcs-kpss-global",
"qcom,msm8996-apcs-hmss-global"
+ "qcom,sdm845-apcs-hmss-global"
- reg:
Usage: required
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 19%]
* [PATCH v3 4/7] mailbox: Add support for Qualcomm SDM845 SoCs
2018-03-14 9:21 11% [PATCH v3 0/7] Add support for remoteproc modem-pil on SDM845 SoCs Sibi S
` (2 preceding siblings ...)
2018-03-14 9:21 19% ` [PATCH v3 3/7] dt-bindings: mailbox: Add APCS global binding for SDM845 SoCs Sibi S
@ 2018-03-14 9:21 19% ` Sibi S
2018-03-18 22:45 0% ` Bjorn Andersson
2018-04-19 17:22 0% ` Bjorn Andersson
2018-03-14 9:21 19% ` [PATCH v3 5/7] dt-bindings: remoteproc: Add Q6v5 Modem PIL binding for SDM845 Sibi S
` (2 subsequent siblings)
6 siblings, 2 replies; 200+ results
From: Sibi S @ 2018-03-14 9:21 UTC (permalink / raw)
To: bjorn.andersson, p.zabel, robh+dt
Cc: linux-remoteproc, linux-kernel, devicetree, sibis, georgi.djakov,
jassisinghbrar, ohad, mark.rutland, kyan, sricharan, akdwived,
linux-arm-msm, tsoni
Add the corresponding APCS offset for SDM845 SoC
Signed-off-by: Sibi S <sibis@codeaurora.org>
---
drivers/mailbox/qcom-apcs-ipc-mailbox.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
index 57bde0d..62d704d 100644
--- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c
+++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
@@ -125,6 +125,7 @@ static int qcom_apcs_ipc_remove(struct platform_device *pdev)
static const struct of_device_id qcom_apcs_ipc_of_match[] = {
{ .compatible = "qcom,msm8916-apcs-kpss-global", .data = (void *)8 },
{ .compatible = "qcom,msm8996-apcs-hmss-global", .data = (void *)16 },
+ { .compatible = "qcom,sdm845-apcs-hmss-global", .data = (void *)12 },
{}
};
MODULE_DEVICE_TABLE(of, qcom_apcs_ipc_of_match);
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 19%]
* [PATCH v3 5/7] dt-bindings: remoteproc: Add Q6v5 Modem PIL binding for SDM845
2018-03-14 9:21 11% [PATCH v3 0/7] Add support for remoteproc modem-pil on SDM845 SoCs Sibi S
` (3 preceding siblings ...)
2018-03-14 9:21 19% ` [PATCH v3 4/7] mailbox: Add support for Qualcomm " Sibi S
@ 2018-03-14 9:21 19% ` Sibi S
2018-03-18 22:46 0% ` Bjorn Andersson
2018-03-14 9:21 16% ` [PATCH v3 6/7] remoteproc: qcom: Add support for mss remoteproc on SDM845 Sibi S
2018-03-14 9:21 14% ` [PATCH v3 7/7] remoteproc: qcom: Always assert and deassert reset signals in SDM845 Sibi S
6 siblings, 1 reply; 200+ results
From: Sibi S @ 2018-03-14 9:21 UTC (permalink / raw)
To: bjorn.andersson, p.zabel, robh+dt
Cc: linux-remoteproc, linux-kernel, devicetree, sibis, georgi.djakov,
jassisinghbrar, ohad, mark.rutland, kyan, sricharan, akdwived,
linux-arm-msm, tsoni
Add new compatible string for Qualcomm SDM845 SoCs
Signed-off-by: Sibi S <sibis@codeaurora.org>
---
Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
index 00d3d58..d901824 100644
--- a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
+++ b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
@@ -11,6 +11,7 @@ on the Qualcomm Hexagon core.
"qcom,msm8916-mss-pil",
"qcom,msm8974-mss-pil"
"qcom,msm8996-mss-pil"
+ "qcom,sdm845-mss-pil"
- reg:
Usage: required
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 19%]
* [PATCH v3 6/7] remoteproc: qcom: Add support for mss remoteproc on SDM845
2018-03-14 9:21 11% [PATCH v3 0/7] Add support for remoteproc modem-pil on SDM845 SoCs Sibi S
` (4 preceding siblings ...)
2018-03-14 9:21 19% ` [PATCH v3 5/7] dt-bindings: remoteproc: Add Q6v5 Modem PIL binding for SDM845 Sibi S
@ 2018-03-14 9:21 16% ` Sibi S
2018-03-14 9:21 14% ` [PATCH v3 7/7] remoteproc: qcom: Always assert and deassert reset signals in SDM845 Sibi S
6 siblings, 0 replies; 200+ results
From: Sibi S @ 2018-03-14 9:21 UTC (permalink / raw)
To: bjorn.andersson, p.zabel, robh+dt
Cc: linux-remoteproc, linux-kernel, devicetree, sibis, georgi.djakov,
jassisinghbrar, ohad, mark.rutland, kyan, sricharan, akdwived,
linux-arm-msm, tsoni
>From SDM845, the Q6SS reset sequence on software side has been
simplified with the introduction of boot FSM which assists in
bringing the Q6 out of reset
Add GLINK subdevice to allow definition of GLINK edge as a
child of modem-pil
Signed-off-by: Sibi S <sibis@codeaurora.org>
---
drivers/remoteproc/qcom_q6v5_pil.c | 65 +++++++++++++++++++++++++++++++++++++-
1 file changed, 64 insertions(+), 1 deletion(-)
diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
index b4e5e72..92bf125 100644
--- a/drivers/remoteproc/qcom_q6v5_pil.c
+++ b/drivers/remoteproc/qcom_q6v5_pil.c
@@ -57,6 +57,8 @@
#define RMB_PMI_META_DATA_REG 0x10
#define RMB_PMI_CODE_START_REG 0x14
#define RMB_PMI_CODE_LENGTH_REG 0x18
+#define RMB_MBA_MSS_STATUS 0x40
+#define RMB_MBA_ALT_RESET 0x44
#define RMB_CMD_META_DATA_READY 0x1
#define RMB_CMD_LOAD_READY 0x2
@@ -104,6 +106,13 @@
#define QDSP6SS_XO_CBCR 0x0038
#define QDSP6SS_ACC_OVERRIDE_VAL 0x20
+/* QDSP6v65 parameters */
+#define QDSP6SS_SLEEP 0x3C
+#define QDSP6SS_BOOT_CORE_START 0x400
+#define QDSP6SS_BOOT_CMD 0x404
+#define SLEEP_CHECK_MAX_LOOPS 200
+#define BOOT_FSM_TIMEOUT 10000
+
struct reg_info {
struct regulator *reg;
int uV;
@@ -166,6 +175,7 @@ struct q6v5 {
void *mpss_region;
size_t mpss_size;
+ struct qcom_rproc_glink glink_subdev;
struct qcom_rproc_subdev smd_subdev;
struct qcom_rproc_ssr ssr_subdev;
bool need_mem_protection;
@@ -178,6 +188,7 @@ enum {
MSS_MSM8916,
MSS_MSM8974,
MSS_MSM8996,
+ MSS_SDM845,
};
static int q6v5_regulator_init(struct device *dev, struct reg_info *regs,
@@ -384,8 +395,35 @@ static int q6v5proc_reset(struct q6v5 *qproc)
int ret;
int i;
+ if (qproc->version == MSS_SDM845) {
- if (qproc->version == MSS_MSM8996) {
+ val = readl(qproc->reg_base + QDSP6SS_SLEEP);
+ val |= 0x1;
+ writel(val, qproc->reg_base + QDSP6SS_SLEEP);
+
+ ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_SLEEP,
+ val, !(val & BIT(31)), 1,
+ SLEEP_CHECK_MAX_LOOPS);
+ if (ret) {
+ dev_err(qproc->dev, "QDSP6SS Sleep clock timed out\n");
+ return -ETIMEDOUT;
+ }
+
+ /* De-assert QDSP6 stop core */
+ writel(1, qproc->reg_base + QDSP6SS_BOOT_CORE_START);
+ /* Trigger boot FSM */
+ writel(1, qproc->reg_base + QDSP6SS_BOOT_CMD);
+
+ ret = readl_poll_timeout(qproc->rmb_base + RMB_MBA_MSS_STATUS,
+ val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT);
+ if (ret) {
+ dev_err(qproc->dev, "Boot FSM failed to complete.\n");
+ return ret;
+ }
+
+ goto pbl_wait;
+
+ } else if (qproc->version == MSS_MSM8996) {
/* Override the ACC value if required */
writel(QDSP6SS_ACC_OVERRIDE_VAL,
qproc->reg_base + QDSP6SS_STRAP_ACC);
@@ -493,6 +531,7 @@ static int q6v5proc_reset(struct q6v5 *qproc)
val &= ~Q6SS_STOP_CORE;
writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
+pbl_wait:
/* Wait for PBL status */
ret = q6v5_rmb_pbl_wait(qproc, 1000);
if (ret == -ETIMEDOUT) {
@@ -1213,6 +1252,7 @@ static int q6v5_probe(struct platform_device *pdev)
}
qproc->mpss_perm = BIT(QCOM_SCM_VMID_HLOS);
qproc->mba_perm = BIT(QCOM_SCM_VMID_HLOS);
+ qcom_add_glink_subdev(rproc, &qproc->glink_subdev);
qcom_add_smd_subdev(rproc, &qproc->smd_subdev);
qcom_add_ssr_subdev(rproc, &qproc->ssr_subdev, "mpss");
@@ -1234,6 +1274,7 @@ static int q6v5_remove(struct platform_device *pdev)
rproc_del(qproc->rproc);
+ qcom_remove_glink_subdev(qproc->rproc, &qproc->glink_subdev);
qcom_remove_smd_subdev(qproc->rproc, &qproc->smd_subdev);
qcom_remove_ssr_subdev(qproc->rproc, &qproc->ssr_subdev);
rproc_free(qproc->rproc);
@@ -1241,6 +1282,27 @@ static int q6v5_remove(struct platform_device *pdev)
return 0;
}
+static const struct rproc_hexagon_res sdm845_mss = {
+ .hexagon_mba_image = "mba.mbn",
+ .proxy_clk_names = (char*[]){
+ "xo",
+ "axis2",
+ "prng",
+ NULL
+ },
+ .active_clk_names = (char*[]){
+ "iface",
+ "bus",
+ "mem",
+ "gpll0_mss",
+ "snoc_axi",
+ "mnoc_axi",
+ NULL
+ },
+ .need_mem_protection = true,
+ .version = MSS_SDM845,
+};
+
static const struct rproc_hexagon_res msm8996_mss = {
.hexagon_mba_image = "mba.mbn",
.proxy_clk_names = (char*[]){
@@ -1334,6 +1396,7 @@ static int q6v5_remove(struct platform_device *pdev)
{ .compatible = "qcom,msm8916-mss-pil", .data = &msm8916_mss},
{ .compatible = "qcom,msm8974-mss-pil", .data = &msm8974_mss},
{ .compatible = "qcom,msm8996-mss-pil", .data = &msm8996_mss},
+ { .compatible = "qcom,sdm845-mss-pil", .data = &sdm845_mss},
{ },
};
MODULE_DEVICE_TABLE(of, q6v5_of_match);
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 16%]
* [PATCH v3 7/7] remoteproc: qcom: Always assert and deassert reset signals in SDM845
2018-03-14 9:21 11% [PATCH v3 0/7] Add support for remoteproc modem-pil on SDM845 SoCs Sibi S
` (5 preceding siblings ...)
2018-03-14 9:21 16% ` [PATCH v3 6/7] remoteproc: qcom: Add support for mss remoteproc on SDM845 Sibi S
@ 2018-03-14 9:21 14% ` Sibi S
6 siblings, 1 reply; 200+ results
From: Sibi S @ 2018-03-14 9:21 UTC (permalink / raw)
To: bjorn.andersson, p.zabel, robh+dt
Cc: linux-remoteproc, linux-kernel, devicetree, sibis, georgi.djakov,
jassisinghbrar, ohad, mark.rutland, kyan, sricharan, akdwived,
linux-arm-msm, tsoni
SDM845 brings a new reset signal ALT_RESET which is a part of the MSS
subsystem hence requires some of the active clks to be enabled before
assert/deassert
Reset the modem if the BOOT FSM does timeout
Reset assert/deassert sequence vary across SoCs adding reset, adding
start/stop helper functions to handle SoC specific reset sequences
Signed-off-by: Sibi S <sibis@codeaurora.org>
---
drivers/remoteproc/qcom_q6v5_pil.c | 100 ++++++++++++++++++++++++++++++++++---
1 file changed, 94 insertions(+), 6 deletions(-)
diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
index 92bf125..bd8c397 100644
--- a/drivers/remoteproc/qcom_q6v5_pil.c
+++ b/drivers/remoteproc/qcom_q6v5_pil.c
@@ -130,11 +130,14 @@ struct rproc_hexagon_res {
struct qcom_mss_reg_res *proxy_supply;
struct qcom_mss_reg_res *active_supply;
char **proxy_clk_names;
+ char **reset_clk_names;
char **active_clk_names;
int version;
bool need_mem_protection;
};
+struct q6v5_reset_ops;
+
struct q6v5 {
struct device *dev;
struct rproc *rproc;
@@ -153,8 +156,10 @@ struct q6v5 {
unsigned stop_bit;
struct clk *active_clks[8];
+ struct clk *reset_clks[4];
struct clk *proxy_clks[4];
int active_clk_count;
+ int reset_clk_count;
int proxy_clk_count;
struct reg_info active_regs[1];
@@ -175,6 +180,7 @@ struct q6v5 {
void *mpss_region;
size_t mpss_size;
+ const struct q6v5_reset_ops *ops;
struct qcom_rproc_glink glink_subdev;
struct qcom_rproc_subdev smd_subdev;
struct qcom_rproc_ssr ssr_subdev;
@@ -184,6 +190,11 @@ struct q6v5 {
int version;
};
+struct q6v5_reset_ops {
+ int (*reset_start)(struct q6v5 *qproc);
+ int (*reset_stop)(struct q6v5 *qproc);
+};
+
enum {
MSS_MSM8916,
MSS_MSM8974,
@@ -343,6 +354,52 @@ static int q6v5_load(struct rproc *rproc, const struct firmware *fw)
return 0;
}
+static void alt_reset_restart(struct q6v5 *qproc, u32 restart)
+{
+ writel(restart, qproc->rmb_base + RMB_MBA_ALT_RESET);
+}
+
+static int q6v5_msm_reset_stop(struct q6v5 *qproc)
+{
+ return reset_control_assert(qproc->mss_restart);
+}
+
+static int q6v5_msm_reset_start(struct q6v5 *qproc)
+{
+ return reset_control_deassert(qproc->mss_restart);
+}
+
+static int q6v5_sdm_reset_stop(struct q6v5 *qproc)
+{
+ return reset_control_reset(qproc->mss_restart);
+}
+
+static int q6v5_sdm_reset_start(struct q6v5 *qproc)
+{
+ int ret;
+
+ alt_reset_restart(qproc, 1);
+ /* Ensure alt reset is written before restart reg */
+ udelay(100);
+
+ ret = reset_control_reset(qproc->mss_restart);
+
+ udelay(100);
+ alt_reset_restart(qproc, 0);
+
+ return ret;
+}
+
+static const struct q6v5_reset_ops q6v5_msm_ops = {
+ .reset_stop = q6v5_msm_reset_stop,
+ .reset_start = q6v5_msm_reset_start,
+};
+
+static const struct q6v5_reset_ops q6v5_sdm_ops = {
+ .reset_stop = q6v5_sdm_reset_stop,
+ .reset_start = q6v5_sdm_reset_start,
+};
+
static int q6v5_rmb_pbl_wait(struct q6v5 *qproc, int ms)
{
unsigned long timeout;
@@ -418,6 +475,8 @@ static int q6v5proc_reset(struct q6v5 *qproc)
val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT);
if (ret) {
dev_err(qproc->dev, "Boot FSM failed to complete.\n");
+ /* Reset the modem so that boot FSM is in reset state */
+ qproc->ops->reset_start(qproc);
return ret;
}
@@ -785,10 +844,18 @@ static int q6v5_start(struct rproc *rproc)
dev_err(qproc->dev, "failed to enable supplies\n");
goto disable_proxy_clk;
}
- ret = reset_control_deassert(qproc->mss_restart);
+
+ ret = q6v5_clk_enable(qproc->dev, qproc->reset_clks,
+ qproc->reset_clk_count);
+ if (ret) {
+ dev_err(qproc->dev, "failed to enable reset clocks\n");
+ goto disable_vdd;
+ }
+
+ ret = qproc->ops->reset_start(qproc);
if (ret) {
dev_err(qproc->dev, "failed to deassert mss restart\n");
- goto disable_vdd;
+ goto disable_reset_clks;
}
ret = q6v5_clk_enable(qproc->dev, qproc->active_clks,
@@ -880,7 +947,10 @@ static int q6v5_start(struct rproc *rproc)
qproc->active_clk_count);
assert_reset:
- reset_control_assert(qproc->mss_restart);
+ qproc->ops->reset_stop(qproc);
+disable_reset_clks:
+ q6v5_clk_disable(qproc->dev, qproc->reset_clks,
+ qproc->reset_clk_count);
disable_vdd:
q6v5_regulator_disable(qproc, qproc->active_regs,
qproc->active_reg_count);
@@ -930,9 +1000,11 @@ static int q6v5_stop(struct rproc *rproc)
qproc->mpss_phys, qproc->mpss_size);
WARN_ON(ret);
- reset_control_assert(qproc->mss_restart);
+ qproc->ops->reset_stop(qproc);
q6v5_clk_disable(qproc->dev, qproc->active_clks,
qproc->active_clk_count);
+ q6v5_clk_disable(qproc->dev, qproc->reset_clks,
+ qproc->reset_clk_count);
q6v5_regulator_disable(qproc, qproc->active_regs,
qproc->active_reg_count);
@@ -1179,6 +1251,12 @@ static int q6v5_probe(struct platform_device *pdev)
qproc->dev = &pdev->dev;
qproc->rproc = rproc;
platform_set_drvdata(pdev, qproc);
+ qproc->version = desc->version;
+
+ if (qproc->version == MSS_SDM845)
+ qproc->ops = &q6v5_sdm_ops;
+ else
+ qproc->ops = &q6v5_msm_ops;
init_completion(&qproc->start_done);
init_completion(&qproc->stop_done);
@@ -1199,6 +1277,14 @@ static int q6v5_probe(struct platform_device *pdev)
}
qproc->proxy_clk_count = ret;
+ ret = q6v5_init_clocks(&pdev->dev, qproc->reset_clks,
+ desc->reset_clk_names);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "Failed to get reset clocks.\n");
+ goto free_rproc;
+ }
+ qproc->reset_clk_count = ret;
+
ret = q6v5_init_clocks(&pdev->dev, qproc->active_clks,
desc->active_clk_names);
if (ret < 0) {
@@ -1227,7 +1313,6 @@ static int q6v5_probe(struct platform_device *pdev)
if (ret)
goto free_rproc;
- qproc->version = desc->version;
qproc->need_mem_protection = desc->need_mem_protection;
ret = q6v5_request_irq(qproc, pdev, "wdog", q6v5_wdog_interrupt);
if (ret < 0)
@@ -1290,8 +1375,11 @@ static int q6v5_remove(struct platform_device *pdev)
"prng",
NULL
},
- .active_clk_names = (char*[]){
+ .reset_clk_names = (char*[]){
"iface",
+ NULL
+ },
+ .active_clk_names = (char*[]){
"bus",
"mem",
"gpll0_mss",
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 14%]
* Re: [PATCH v3 2/7] reset: qcom: AOSS (always on subsystem) reset controller
2018-03-14 9:21 14% ` [PATCH v3 2/7] reset: qcom: AOSS (always on subsystem) reset controller Sibi S
@ 2018-03-14 10:48 0% ` Vivek Gautam
1 sibling, 0 replies; 200+ results
From: Vivek Gautam @ 2018-03-14 10:48 UTC (permalink / raw)
To: Sibi S, bjorn.andersson, p.zabel, robh+dt
Cc: linux-remoteproc, linux-kernel, devicetree, georgi.djakov,
jassisinghbrar, ohad, mark.rutland, kyan, sricharan, akdwived,
linux-arm-msm, tsoni
Hi Sibi,
On 3/14/2018 2:51 PM, Sibi S wrote:
> Add reset controller driver for Qualcomm SDM845 SoC to
> control reset signals provided by AOSS for Modem, Venus
> ADSP, GPU, Camera, Wireless, Display subsystem
>
> Signed-off-by: Sibi S <sibis@codeaurora.org>
> ---
> drivers/reset/Kconfig | 10 +++
> drivers/reset/Makefile | 1 +
> drivers/reset/reset-qcom-aoss.c | 156 ++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 167 insertions(+)
> create mode 100644 drivers/reset/reset-qcom-aoss.c
>
> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
> index 7fc7769..d06bd1d 100644
> --- a/drivers/reset/Kconfig
> +++ b/drivers/reset/Kconfig
> @@ -81,6 +81,16 @@ config RESET_PISTACHIO
> help
> This enables the reset driver for ImgTec Pistachio SoCs.
>
> +config RESET_QCOM_AOSS
> + bool "Qcom AOSS Reset Driver"
> + depends on ARCH_QCOM || COMPILE_TEST
> + select MFD_SYSCON
I think we don't need this after we moved away from syscon?
> + help
> + This enables the AOSS (always on subsystem) reset driver
> + for Qualcomm SDM845 SoCs. Say Y if you want to control
> + reset signals provided by AOSS for Modem, Venus, ADSP,
> + GPU, Camera, Wireless, Display subsystem. Otherwise, say N.
> +
> config RESET_SIMPLE
> bool "Simple Reset Controller Driver" if COMPILE_TEST
> default ARCH_SOCFPGA || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX
> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
> index 132c24f..c30044a 100644
> --- a/drivers/reset/Makefile
> +++ b/drivers/reset/Makefile
> @@ -14,6 +14,7 @@ obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
> obj-$(CONFIG_RESET_MESON) += reset-meson.o
> obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
> obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o
> +obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o
> obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
> obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
> obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
> diff --git a/drivers/reset/reset-qcom-aoss.c b/drivers/reset/reset-qcom-aoss.c
> new file mode 100644
> index 0000000..e70fb37
> --- /dev/null
> +++ b/drivers/reset/reset-qcom-aoss.c
> @@ -0,0 +1,156 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2018 The Linux Foundation. All rights reserved.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/reset-controller.h>
> +#include <linux/regmap.h>
> +#include <linux/of_device.h>
> +#include <dt-bindings/reset/qcom,sdm845-aoss.h>
> +
> +struct qcom_aoss_reset_map {
> + unsigned int reg;
> + u8 bit;
> +};
> +
> +struct qcom_aoss_desc {
> + const struct regmap_config *config;
> + const struct qcom_aoss_reset_map *resets;
> + int delay;
> + size_t num_resets;
> +};
> +
> +struct qcom_aoss_reset_data {
> + struct reset_controller_dev rcdev;
> + struct regmap *regmap;
> + const struct qcom_aoss_desc *desc;
> +};
> +
> +static const struct regmap_config sdm845_aoss_regmap_config = {
> + .name = "aoss-reset",
> + .reg_bits = 32,
> + .reg_stride = 4,
> + .val_bits = 32,
> + .max_register = 0x20000,
> + .fast_io = true,
> +};
> +
> +static const struct qcom_aoss_reset_map sdm845_aoss_resets[] = {
> + [AOSS_CC_MSS_RESTART] = { 0x0, 0 },
> + [AOSS_CC_CAMSS_RESTART] = { 0x1000, 0 },
> + [AOSS_CC_VENUS_RESTART] = { 0x2000, 0 },
> + [AOSS_CC_GPU_RESTART] = { 0x3000, 0 },
> + [AOSS_CC_DISPSS_RESTART] = { 0x4000, 0 },
> + [AOSS_CC_WCSS_RESTART] = { 0x10000, 0 },
> + [AOSS_CC_LPASS_RESTART] = { 0x20000, 0 },
> +};
> +
> +static const struct qcom_aoss_desc sdm845_aoss_desc = {
> + .config = &sdm845_aoss_regmap_config,
> + .resets = sdm845_aoss_resets,
> + /* Wait 6 32kHz sleep cycles for reset */
> + .delay = 200,
> + .num_resets = ARRAY_SIZE(sdm845_aoss_resets),
> +};
> +
> +static struct qcom_aoss_reset_data *to_qcom_aoss_reset_data(
> + struct reset_controller_dev *rcdev)
> +{
> + return container_of(rcdev, struct qcom_aoss_reset_data, rcdev);
> +}
Either a macro for such definition or 'inline'?
> +
> +static int qcom_aoss_control_assert(struct reset_controller_dev *rcdev,
> + unsigned long idx)
> +{
> + struct qcom_aoss_reset_data *data = to_qcom_aoss_reset_data(rcdev);
> + const struct qcom_aoss_reset_map *map = &data->desc->resets[idx];
> +
> + return regmap_update_bits(data->regmap, map->reg,
> + BIT(map->bit), BIT(map->bit));
> +}
> +
> +static int qcom_aoss_control_deassert(struct reset_controller_dev *rcdev,
> + unsigned long idx)
> +{
> + struct qcom_aoss_reset_data *data = to_qcom_aoss_reset_data(rcdev);
> + const struct qcom_aoss_reset_map *map = &data->desc->resets[idx];
> +
> + return regmap_update_bits(data->regmap, map->reg, BIT(map->bit), 0);
> +}
> +
> +static int qcom_aoss_control_reset(struct reset_controller_dev *rcdev,
> + unsigned long idx)
> +{
> + struct qcom_aoss_reset_data *data = to_qcom_aoss_reset_data(rcdev);
> + int ret;
> +
> + ret = qcom_aoss_control_assert(rcdev, idx);
> + if (ret)
> + return ret;
> +
> + udelay(data->desc->delay);
> +
> + return qcom_aoss_control_deassert(rcdev, idx);
> +}
> +
> +static const struct reset_control_ops qcom_aoss_reset_ops = {
> + .reset = qcom_aoss_control_reset,
> + .assert = qcom_aoss_control_assert,
> + .deassert = qcom_aoss_control_deassert,
> +};
> +
> +static int qcom_aoss_reset_probe(struct platform_device *pdev)
> +{
> + struct qcom_aoss_reset_data *data;
> + struct device *dev = &pdev->dev;
> + const struct qcom_aoss_desc *desc;
> + void __iomem *base;
> + struct resource *res;
> +
> + desc = of_device_get_match_data(dev);
> + if (!desc)
> + return -EINVAL;
> +
> + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
> + if (!data)
> + return -ENOMEM;
> +
> + data->desc = desc;
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + base = devm_ioremap_resource(dev, res);
> + if (IS_ERR(base))
> + return PTR_ERR(base);
> +
> + data->regmap = devm_regmap_init_mmio(dev, base, desc->config);
> + if (IS_ERR(data->regmap)) {
> + dev_err(dev, "Unable to get aoss-reset regmap");
> + return PTR_ERR(data->regmap);
> + }
> +
> + data->rcdev.owner = THIS_MODULE;
> + data->rcdev.ops = &qcom_aoss_reset_ops;
> + data->rcdev.nr_resets = desc->num_resets;
> + data->rcdev.of_node = dev->of_node;
> +
> + return devm_reset_controller_register(dev, &data->rcdev);
> +}
> +
> +static const struct of_device_id qcom_aoss_reset_of_match[] = {
> + { .compatible = "qcom,sdm845-aoss-reset", .data = &sdm845_aoss_desc },
> + {}
> +};
> +
> +static struct platform_driver qcom_aoss_reset_driver = {
> + .probe = qcom_aoss_reset_probe,
> + .driver = {
> + .name = "qcom_aoss_reset",
> + .of_match_table = qcom_aoss_reset_of_match,
> + },
> +};
> +
> +builtin_platform_driver(qcom_aoss_reset_driver);
> +
> +MODULE_DESCRIPTION("Qualcomm AOSS Reset Driver");
> +MODULE_LICENSE("GPL v2");
Rest looks good to me. After taking above changes -
Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org>
regards
Vivek
^ permalink raw reply [relevance 0%]
* Re: [PATCH v3 1/7] dt-bindings: reset: Add AOSS reset bindings for SDM845 SoCs
2018-03-14 9:21 17% ` [PATCH v3 1/7] dt-bindings: reset: Add AOSS reset bindings for " Sibi S
@ 2018-03-18 12:49 0% ` Rob Herring
1 sibling, 0 replies; 200+ results
From: Rob Herring @ 2018-03-18 12:49 UTC (permalink / raw)
To: Sibi S
Cc: bjorn.andersson, p.zabel, linux-remoteproc, linux-kernel,
devicetree, georgi.djakov, jassisinghbrar, ohad, mark.rutland,
kyan, sricharan, akdwived, linux-arm-msm, tsoni
On Wed, Mar 14, 2018 at 02:51:17PM +0530, Sibi S wrote:
> Add SDM845 AOSS (always on subsystem) reset controller binding
>
> Signed-off-by: Sibi S <sibis@codeaurora.org>
Still need a full name.
Otherwise, looks fine.
> ---
> .../devicetree/bindings/reset/qcom,aoss-reset.txt | 54 ++++++++++++++++++++++
> include/dt-bindings/reset/qcom,sdm845-aoss.h | 17 +++++++
> 2 files changed, 71 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
> create mode 100644 include/dt-bindings/reset/qcom,sdm845-aoss.h
^ permalink raw reply [relevance 0%]
* Re: [PATCH v3 3/7] dt-bindings: mailbox: Add APCS global binding for SDM845 SoCs
2018-03-14 9:21 19% ` [PATCH v3 3/7] dt-bindings: mailbox: Add APCS global binding for SDM845 SoCs Sibi S
@ 2018-03-18 22:45 0% ` Bjorn Andersson
0 siblings, 0 replies; 200+ results
From: Bjorn Andersson @ 2018-03-18 22:45 UTC (permalink / raw)
To: Sibi S
Cc: p.zabel, robh+dt, linux-remoteproc, linux-kernel, devicetree,
georgi.djakov, jassisinghbrar, ohad, mark.rutland, kyan,
sricharan, akdwived, linux-arm-msm, tsoni
On Wed 14 Mar 02:21 PDT 2018, Sibi S wrote:
> Include SDM845 APCS binding to the list of possible bindings
>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Regards,
Bjorn
> Signed-off-by: Sibi S <sibis@codeaurora.org>
> ---
> Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt
> index 16964f0..6a7e5d8 100644
> --- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt
> +++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt
> @@ -10,6 +10,7 @@ platforms.
> Definition: must be one of:
> "qcom,msm8916-apcs-kpss-global",
> "qcom,msm8996-apcs-hmss-global"
> + "qcom,sdm845-apcs-hmss-global"
>
> - reg:
> Usage: required
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
^ permalink raw reply [relevance 0%]
* Re: [PATCH v3 4/7] mailbox: Add support for Qualcomm SDM845 SoCs
2018-03-14 9:21 19% ` [PATCH v3 4/7] mailbox: Add support for Qualcomm " Sibi S
@ 2018-03-18 22:45 0% ` Bjorn Andersson
2018-04-19 17:22 0% ` Bjorn Andersson
1 sibling, 0 replies; 200+ results
From: Bjorn Andersson @ 2018-03-18 22:45 UTC (permalink / raw)
To: Sibi S
Cc: p.zabel, robh+dt, linux-remoteproc, linux-kernel, devicetree,
georgi.djakov, jassisinghbrar, ohad, mark.rutland, kyan,
sricharan, akdwived, linux-arm-msm, tsoni
On Wed 14 Mar 02:21 PDT 2018, Sibi S wrote:
> Add the corresponding APCS offset for SDM845 SoC
>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Regards,
Bjorn
> Signed-off-by: Sibi S <sibis@codeaurora.org>
> ---
> drivers/mailbox/qcom-apcs-ipc-mailbox.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
> index 57bde0d..62d704d 100644
> --- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c
> +++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
> @@ -125,6 +125,7 @@ static int qcom_apcs_ipc_remove(struct platform_device *pdev)
> static const struct of_device_id qcom_apcs_ipc_of_match[] = {
> { .compatible = "qcom,msm8916-apcs-kpss-global", .data = (void *)8 },
> { .compatible = "qcom,msm8996-apcs-hmss-global", .data = (void *)16 },
> + { .compatible = "qcom,sdm845-apcs-hmss-global", .data = (void *)12 },
> {}
> };
> MODULE_DEVICE_TABLE(of, qcom_apcs_ipc_of_match);
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
^ permalink raw reply [relevance 0%]
* Re: [PATCH v3 5/7] dt-bindings: remoteproc: Add Q6v5 Modem PIL binding for SDM845
2018-03-14 9:21 19% ` [PATCH v3 5/7] dt-bindings: remoteproc: Add Q6v5 Modem PIL binding for SDM845 Sibi S
@ 2018-03-18 22:46 0% ` Bjorn Andersson
0 siblings, 0 replies; 200+ results
From: Bjorn Andersson @ 2018-03-18 22:46 UTC (permalink / raw)
To: Sibi S
Cc: p.zabel, robh+dt, linux-remoteproc, linux-kernel, devicetree,
georgi.djakov, jassisinghbrar, ohad, mark.rutland, kyan,
sricharan, akdwived, linux-arm-msm, tsoni
On Wed 14 Mar 02:21 PDT 2018, Sibi S wrote:
> Add new compatible string for Qualcomm SDM845 SoCs
>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Regards,
Bjorn
> Signed-off-by: Sibi S <sibis@codeaurora.org>
> ---
> Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
> index 00d3d58..d901824 100644
> --- a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
> +++ b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
> @@ -11,6 +11,7 @@ on the Qualcomm Hexagon core.
> "qcom,msm8916-mss-pil",
> "qcom,msm8974-mss-pil"
> "qcom,msm8996-mss-pil"
> + "qcom,sdm845-mss-pil"
>
> - reg:
> Usage: required
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
^ permalink raw reply [relevance 0%]
* Re: [PATCH v3 1/7] dt-bindings: reset: Add AOSS reset bindings for SDM845 SoCs
@ 2018-03-21 6:29 6% ` Sibi S
0 siblings, 0 replies; 200+ results
From: Sibi S @ 2018-03-21 6:29 UTC (permalink / raw)
To: Bjorn Andersson
Cc: p.zabel, robh+dt, linux-remoteproc, linux-kernel, devicetree,
georgi.djakov, jassisinghbrar, ohad, mark.rutland, kyan,
sricharan, akdwived, linux-arm-msm, tsoni
Hi Bjorn,
Thanks for the review.
On 03/19/2018 04:14 AM, Bjorn Andersson wrote:
> On Wed 14 Mar 02:21 PDT 2018, Sibi S wrote:
>> +- reg:
>> + Usage: required
>> + Value type: <prop-encoded-array>
>> + Definition: must specify the base address and size of the register
>> + space.
>> +
>> +
>
> Double empty lines.
>
will remove them
>> +- #reset-cells:
>> + Usage: required
>> + Value type: <uint>
>> + Definition: must be 1; cell entry represents the reset index.
>> +
>> +example:
>
> Please capitalize the initial char.
>
sure
>> +
>> +aoss_reset: qcom,reset-controller@b2e0100 {
>> + compatible = "qcom,sdm845-aoss-reset";
>> + reg = <0xc2b0000 0x20004>;
>
> 0x20004 does seem very even, please verify this size.
>
even though the reg space after that range is unused, the AOSS reset
driver is supposed to control only those listed reset lines
>> + #reset-cells = <1>;
>> +};
>> +
>> +
>> +Specifying reset lines connected to IP modules
>
> "AOSS reset clients"
>
yep this heading makes much more sense
> Although you could probably get a way with just referring to reset.txt
> and the header file.
>
>> +==============================================
>> +
>> +Device nodes that need access to reset lines should
>> +specify them as a reset phandle in their corresponding node as
>> +specified in reset.txt.
>> +
>> +For list of all valid reset indicies see
>> +<dt-bindings/reset/qcom,sdm845-aoss.h>
>> +
>> +Example:
>> +
>> +modem-pil@4080000 {
>> + ...
>> +
>> + resets = <&aoss_reset AOSS_CC_MSS_RESTART>;
>> + reset-names = "mss_restart";
>> +
>> + ...
>> +};
>> diff --git a/include/dt-bindings/reset/qcom,sdm845-aoss.h b/include/dt-bindings/reset/qcom,sdm845-aoss.h
>> new file mode 100644
>> index 0000000..e9b38fc
>> --- /dev/null
>> +++ b/include/dt-bindings/reset/qcom,sdm845-aoss.h
>> @@ -0,0 +1,17 @@
>> +// SPDX-License-Identifier: GPL-2.0
>
> For tooling reasons header files should have their SPDX License tag
> wrapped in /* */
>
Sure will replace it
>> +/*
>> + * Copyright (C) 2018 The Linux Foundation. All rights reserved.
>> + */
>> +
>> +#ifndef _DT_BINDINGS_RESET_AOSS_SDM_845_H
>> +#define _DT_BINDINGS_RESET_AOSS_SDM_845_H
>> +
>> +#define AOSS_CC_MSS_RESTART 0
>> +#define AOSS_CC_CAMSS_RESTART 1
>> +#define AOSS_CC_VENUS_RESTART 2
>> +#define AOSS_CC_GPU_RESTART 3
>> +#define AOSS_CC_DISPSS_RESTART 4
>> +#define AOSS_CC_WCSS_RESTART 5
>> +#define AOSS_CC_LPASS_RESTART 6
>> +
>> +#endif
>
> Apart from these nits this looks reasonable.
>
> Regards,
> Bjorn
>
--
Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc, is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [relevance 6%]
* Re: [PATCH v3 7/7] remoteproc: qcom: Always assert and deassert reset signals in SDM845
@ 2018-03-22 22:10 6% ` Sibi S
0 siblings, 0 replies; 200+ results
From: Sibi S @ 2018-03-22 22:10 UTC (permalink / raw)
To: Bjorn Andersson
Cc: p.zabel, robh+dt, linux-remoteproc, linux-kernel, devicetree,
georgi.djakov, jassisinghbrar, ohad, mark.rutland, kyan,
sricharan, akdwived, linux-arm-msm, tsoni
Hi Bjorn,
Thanks for the review
On 03/19/2018 04:16 AM, Bjorn Andersson wrote:
> On Wed 14 Mar 02:21 PDT 2018, Sibi S wrote:
>> diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
> [..]
>> +struct q6v5_reset_ops {
>> + int (*reset_start)(struct q6v5 *qproc);
>> + int (*reset_stop)(struct q6v5 *qproc);
>> +};
>
> Please add these two ops directly in q6v5 instead and please keep the
> naming "reset_assert" and "reset_deassert".
>
sure will do
>> +
>> enum {
>> MSS_MSM8916,
>> MSS_MSM8974,
>> @@ -343,6 +354,52 @@ static int q6v5_load(struct rproc *rproc, const struct firmware *fw)
>> return 0;
>> }
>>
>> +static void alt_reset_restart(struct q6v5 *qproc, u32 restart)
>> +{
>> + writel(restart, qproc->rmb_base + RMB_MBA_ALT_RESET);
>
> Just move this write into q6v5_sdm_reset_start()
>
sure will do
>> +}
>> +
>> +static int q6v5_msm_reset_stop(struct q6v5 *qproc)
>> +{
>> + return reset_control_assert(qproc->mss_restart);
>> +}
>> +
>> +static int q6v5_msm_reset_start(struct q6v5 *qproc)
>> +{
>> + return reset_control_deassert(qproc->mss_restart);
>> +}
>> +
>> +static int q6v5_sdm_reset_stop(struct q6v5 *qproc)
>> +{
>> + return reset_control_reset(qproc->mss_restart);
>> +}
>> +
>> +static int q6v5_sdm_reset_start(struct q6v5 *qproc)
>> +{
>> + int ret;
>> +
>> + alt_reset_restart(qproc, 1);
>> + /* Ensure alt reset is written before restart reg */
>
> That's not what udelay does ;)
>
> If you want to make sure that the register is written and then give it
> 100us delay until you reset the reset you have to readl() the same
> register back after the writel()
>
> I think the delay deserves a comment on what we're waiting for.
>
the delay can be removed for the reasons stated below
>> + udelay(100);
>
> Use usleep_range() for delays longer than 10us.
>
>> +
>> + ret = reset_control_reset(qproc->mss_restart);
>> +
>> + udelay(100);
>
> Same as the delay above, what are we waiting for?
>
The point is to wait for 6 32khz sleep cycles both after assert and
after de-assert of the aoss mss reset line. So moving the udelay to
the aoss reset controller should have been right thing to do. alt_reset
shouldn't need delays in between will remove them.
>> + alt_reset_restart(qproc, 0);
>> +
>> + return ret;
>> +}
>> +
> [..]
>> @@ -1179,6 +1251,12 @@ static int q6v5_probe(struct platform_device *pdev)
>> qproc->dev = &pdev->dev;
>> qproc->rproc = rproc;
>> platform_set_drvdata(pdev, qproc);
>> + qproc->version = desc->version;
>> +
>> + if (qproc->version == MSS_SDM845)
>> + qproc->ops = &q6v5_sdm_ops;
>> + else
>> + qproc->ops = &q6v5_msm_ops;
>
> Can we carry a boolean for "has_alt_reset" or something that picks the
> new reset ops, rather than picking by version?
>
Though alt_reset is specific to SDM845 SoCs it also includes another
reset controller (pdc_sync) in the modem bringup sequence, it isn't
included it in the patch series since it doesn't seem to affect the
modem start/stop functionality. Knowing that it may be added wouldn't
version be a better choice here?
> Regards,
> Bjorn
>
--
Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc, is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [relevance 6%]
* Re: [PATCH v3 2/7] reset: qcom: AOSS (always on subsystem) reset controller
@ 2018-03-22 22:32 6% ` Sibi S
0 siblings, 0 replies; 200+ results
From: Sibi S @ 2018-03-22 22:32 UTC (permalink / raw)
To: Bjorn Andersson
Cc: p.zabel, robh+dt, linux-remoteproc, linux-kernel, devicetree,
georgi.djakov, jassisinghbrar, ohad, mark.rutland, kyan,
sricharan, akdwived, linux-arm-msm, tsoni
Hi Bjorn,
Thanks for the review.
On 03/19/2018 04:15 AM, Bjorn Andersson wrote:
> On Wed 14 Mar 02:21 PDT 2018, Sibi S wrote:
>> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
>> index 7fc7769..d06bd1d 100644
>> --- a/drivers/reset/Kconfig
>> +++ b/drivers/reset/Kconfig
>> @@ -81,6 +81,16 @@ config RESET_PISTACHIO
>> help
>> This enables the reset driver for ImgTec Pistachio SoCs.
>>
>> +config RESET_QCOM_AOSS
>> + bool "Qcom AOSS Reset Driver"
>> + depends on ARCH_QCOM || COMPILE_TEST
>> + select MFD_SYSCON
>
> Drop syscon
>
will drop it
>> + help
>> + This enables the AOSS (always on subsystem) reset driver
>> + for Qualcomm SDM845 SoCs. Say Y if you want to control
>> + reset signals provided by AOSS for Modem, Venus, ADSP,
>> + GPU, Camera, Wireless, Display subsystem. Otherwise, say N.
>> +
> [..]
>> diff --git a/drivers/reset/reset-qcom-aoss.c b/drivers/reset/reset-qcom-aoss.c
> [..]
>> +static const struct regmap_config sdm845_aoss_regmap_config = {
>> + .name = "aoss-reset",
>> + .reg_bits = 32,
>> + .reg_stride = 4,
>> + .val_bits = 32,
>> + .max_register = 0x20000,
>> + .fast_io = true,
>> +};
>
> Is there a particular reason why you're setting up a regmap and not just
> operate on the ioremap region directly with readl/writel? It would save
> you a few lines of code and some runtime memory.
>
The idea here is to reuse the driver in modified configuration as
pdc_sync restart controller which is to be used for adsp_pil. PDC sync
reset register is a single register with multiple reset lines hence
would warrant setting up a regmap. I can remove these changes and add
them when I add pdc_sync reset controller though.
>> +
>> +static const struct qcom_aoss_reset_map sdm845_aoss_resets[] = {
>> + [AOSS_CC_MSS_RESTART] = { 0x0, 0 },
>> + [AOSS_CC_CAMSS_RESTART] = { 0x1000, 0 },
>> + [AOSS_CC_VENUS_RESTART] = { 0x2000, 0 },
>> + [AOSS_CC_GPU_RESTART] = { 0x3000, 0 },
>> + [AOSS_CC_DISPSS_RESTART] = { 0x4000, 0 },
>> + [AOSS_CC_WCSS_RESTART] = { 0x10000, 0 },
>> + [AOSS_CC_LPASS_RESTART] = { 0x20000, 0 },
>
> Do you have a case where bit != 0? If not please drop the bit until it's
> necessary.
>
had the bit variable for the above state reason.
>> +};
>> +
>> +static const struct qcom_aoss_desc sdm845_aoss_desc = {
>> + .config = &sdm845_aoss_regmap_config,
>> + .resets = sdm845_aoss_resets,
>> + /* Wait 6 32kHz sleep cycles for reset */
>> + .delay = 200,
>
> Please move this constant into qcom_aoss_control_reset(), until there's
> a need for it to be configurable.
>
>> + .num_resets = ARRAY_SIZE(sdm845_aoss_resets),
>> +};
>> +
> [..]
>> +static int qcom_aoss_control_reset(struct reset_controller_dev *rcdev,
>> + unsigned long idx)
>> +{
>> + struct qcom_aoss_reset_data *data = to_qcom_aoss_reset_data(rcdev);
>> + int ret;
>> +
>> + ret = qcom_aoss_control_assert(rcdev, idx);
>> + if (ret)
>> + return ret;
>> +
>> + udelay(data->desc->delay);
>
> Per Documentation/timers/timers-howto.txt please use usleep_range() when
> delays are between 10us and 20ms.
>
will replace them
>> +
>> + return qcom_aoss_control_deassert(rcdev, idx);
>> +}
>
> Regards,
> Bjorn
>
--
Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc, is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [relevance 6%]
* Re: [PATCH v3 4/7] mailbox: Add support for Qualcomm SDM845 SoCs
2018-03-14 9:21 19% ` [PATCH v3 4/7] mailbox: Add support for Qualcomm " Sibi S
2018-03-18 22:45 0% ` Bjorn Andersson
@ 2018-04-19 17:22 0% ` Bjorn Andersson
1 sibling, 0 replies; 200+ results
From: Bjorn Andersson @ 2018-04-19 17:22 UTC (permalink / raw)
To: Sibi S
Cc: p.zabel, robh+dt, linux-remoteproc, linux-kernel, devicetree,
georgi.djakov, jassisinghbrar, ohad, mark.rutland, kyan,
sricharan, akdwived, linux-arm-msm, tsoni
On Wed 14 Mar 02:21 PDT 2018, Sibi S wrote:
> Add the corresponding APCS offset for SDM845 SoC
>
> Signed-off-by: Sibi S <sibis@codeaurora.org>
Full name please.
> ---
> drivers/mailbox/qcom-apcs-ipc-mailbox.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
> index 57bde0d..62d704d 100644
> --- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c
> +++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
> @@ -125,6 +125,7 @@ static int qcom_apcs_ipc_remove(struct platform_device *pdev)
> static const struct of_device_id qcom_apcs_ipc_of_match[] = {
> { .compatible = "qcom,msm8916-apcs-kpss-global", .data = (void *)8 },
> { .compatible = "qcom,msm8996-apcs-hmss-global", .data = (void *)16 },
> + { .compatible = "qcom,sdm845-apcs-hmss-global", .data = (void *)12 },
The block seems to be called "apss shared", so make the compatible
"qcom,sdm845-apss-shared".
Please resubmit this patch separate from the others in the series, as
they can be merged independently of the rest of the series.
PS. For updates like this you can generally submit the dt and code
together.
Regards,
Bjorn
^ permalink raw reply [relevance 0%]
* [PATCH 1/3] dt-bindings: mailbox: Add APSS shared binding for SDM845 SoCs
@ 2018-04-25 14:38 21% Sibi Sankar
2018-04-25 14:38 21% ` [PATCH 2/3] mailbox: Add support for Qualcomm " Sibi Sankar
` (3 more replies)
0 siblings, 4 replies; 200+ results
From: Sibi Sankar @ 2018-04-25 14:38 UTC (permalink / raw)
To: andy.gross, mark.rutland, bjorn.andersson
Cc: david.brown, linux-arm-msm, georgi.djakov, devicetree, linux-soc,
linux-kernel, jassisinghbrar, will.deacon, catalin.marinas,
Sibi Sankar
Include SDM845 APSS shared to the list of possible bindings
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
.../devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt
index 16964f0c1773..8ea0f12b8d0b 100644
--- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt
+++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt
@@ -10,6 +10,7 @@ platforms.
Definition: must be one of:
"qcom,msm8916-apcs-kpss-global",
"qcom,msm8996-apcs-hmss-global"
+ "qcom,sdm845-apss-shared"
- reg:
Usage: required
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 21%]
* [PATCH 2/3] mailbox: Add support for Qualcomm SDM845 SoCs
2018-04-25 14:38 21% [PATCH 1/3] dt-bindings: mailbox: Add APSS shared binding for SDM845 SoCs Sibi Sankar
@ 2018-04-25 14:38 21% ` Sibi Sankar
2018-04-25 16:26 0% ` Bjorn Andersson
2018-04-25 14:38 21% ` [PATCH 3/3] arm64: dts: qcom: Add APSS shared mailbox node to SDM845 Sibi Sankar
` (2 subsequent siblings)
3 siblings, 1 reply; 200+ results
From: Sibi Sankar @ 2018-04-25 14:38 UTC (permalink / raw)
To: andy.gross, mark.rutland, bjorn.andersson
Cc: david.brown, linux-arm-msm, georgi.djakov, devicetree, linux-soc,
linux-kernel, jassisinghbrar, will.deacon, catalin.marinas,
Sibi Sankar
Add the corresponding APSS shared offset for SDM845 SoC
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
drivers/mailbox/qcom-apcs-ipc-mailbox.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
index 57bde0dfd12f..75da44d25fac 100644
--- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c
+++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
@@ -125,6 +125,7 @@ static int qcom_apcs_ipc_remove(struct platform_device *pdev)
static const struct of_device_id qcom_apcs_ipc_of_match[] = {
{ .compatible = "qcom,msm8916-apcs-kpss-global", .data = (void *)8 },
{ .compatible = "qcom,msm8996-apcs-hmss-global", .data = (void *)16 },
+ { .compatible = "qcom,sdm845-apss-shared", .data = (void *)12 },
{}
};
MODULE_DEVICE_TABLE(of, qcom_apcs_ipc_of_match);
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 21%]
* [PATCH 3/3] arm64: dts: qcom: Add APSS shared mailbox node to SDM845
2018-04-25 14:38 21% [PATCH 1/3] dt-bindings: mailbox: Add APSS shared binding for SDM845 SoCs Sibi Sankar
2018-04-25 14:38 21% ` [PATCH 2/3] mailbox: Add support for Qualcomm " Sibi Sankar
@ 2018-04-25 14:38 21% ` Sibi Sankar
2018-04-25 16:30 0% ` Bjorn Andersson
2018-04-25 16:26 0% ` [PATCH 1/3] dt-bindings: mailbox: Add APSS shared binding for SDM845 SoCs Bjorn Andersson
2018-05-01 14:28 0% ` Rob Herring
3 siblings, 1 reply; 200+ results
From: Sibi Sankar @ 2018-04-25 14:38 UTC (permalink / raw)
To: andy.gross, mark.rutland, bjorn.andersson
Cc: david.brown, linux-arm-msm, georgi.djakov, devicetree, linux-soc,
linux-kernel, jassisinghbrar, will.deacon, catalin.marinas,
Sibi Sankar
This patch add the node to support APSS shared
mailbox on SDM845
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
This patch depends on https://patchwork.kernel.org/patch/10276419/
arch/arm64/boot/dts/qcom/sdm845.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 486ace9a9e8b..9be763da0664 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -338,5 +338,11 @@
status = "disabled";
};
};
+
+ apss_shared: mailbox@17990000 {
+ compatible = "qcom,sdm845-apss-shared";
+ reg = <0x17990000 0x1000>;
+ #mbox-cells = <1>;
+ };
};
};
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 21%]
* [PATCH] arm64: dts: qcom: Add SDM845 SMEM nodes
@ 2018-04-25 14:46 20% Sibi Sankar
0 siblings, 1 reply; 200+ results
From: Sibi Sankar @ 2018-04-25 14:46 UTC (permalink / raw)
To: andy.gross, david.brown, robh+dt, bjorn.andersson
Cc: mark.rutland, catalin.marinas, will.deacon, linux-arm-msm,
linux-kernel, devicetree, linux-soc, Sibi Sankar
Add all the necessary dt nodes to support SMEM driver
on SDM845. It also adds the required memory carveouts
so that the kernel does not access memory that is in
use.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
This patch depends on:
https://patchwork.kernel.org/patch/10276419/
https://patchwork.kernel.org/patch/10363361/
arch/arm64/boot/dts/qcom/sdm845.dtsi | 38 ++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 9be763da0664..bea985045759 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -21,6 +21,27 @@
reg = <0 0x80000000 0 0>;
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ memory@85fc0000 {
+ reg = <0 0x85fc0000 0 0x40000>;
+ no-map;
+ };
+
+ smem_mem: smem-mem@86000000 {
+ reg = <0x0 0x86000000 0x0 0x200000>;
+ no-map;
+ };
+
+ memory@86000000 {
+ reg = <0 0x86200000 0 0x2d00000>;
+ no-map;
+ };
+ };
+
cpus {
#address-cells = <2>;
#size-cells = <0>;
@@ -147,6 +168,18 @@
};
};
+ tcsr_mutex: hwlock {
+ compatible = "qcom,tcsr-mutex";
+ syscon = <&tcsr_mutex_regs 0 0x1000>;
+ #hwlock-cells = <1>;
+ };
+
+ smem {
+ compatible = "qcom,smem";
+ memory-region = <&smem_mem>;
+ hwlocks = <&tcsr_mutex 3>;
+ };
+
psci {
compatible = "arm,psci-1.0";
method = "smc";
@@ -339,6 +372,11 @@
};
};
+ tcsr_mutex_regs: syscon@1f40000 {
+ compatible = "syscon";
+ reg = <0x1f40000 0x40000>;
+ };
+
apss_shared: mailbox@17990000 {
compatible = "qcom,sdm845-apss-shared";
reg = <0x17990000 0x1000>;
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 20%]
* [PATCH] remoteproc: Proxy unvote clk/regs in handover context
@ 2018-04-25 14:50 17% Sibi Sankar
2018-05-18 19:58 0% ` Bjorn Andersson
0 siblings, 1 reply; 200+ results
From: Sibi Sankar @ 2018-04-25 14:50 UTC (permalink / raw)
To: ohad, bjorn.andersson
Cc: clew, linux-remoteproc, linux-kernel, linux-arm-msm, Sibi Sankar
Introduce interrupt handler for smp2p ready interrupt and
handle start completion. Remove the proxy votes for clocks
and regulators in the handover interrupt context. Disable
wdog and fatal interrupts on remoteproc device stop and
re-enable them on remoteproc device start.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
drivers/remoteproc/qcom_q6v5_pil.c | 71 +++++++++++++++++++++++++-----
1 file changed, 60 insertions(+), 11 deletions(-)
diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
index 296eb3f8b551..7e2d04d4f2f0 100644
--- a/drivers/remoteproc/qcom_q6v5_pil.c
+++ b/drivers/remoteproc/qcom_q6v5_pil.c
@@ -143,6 +143,10 @@ struct q6v5 {
struct qcom_smem_state *state;
unsigned stop_bit;
+ unsigned int handover_interrupt;
+ unsigned int wdog_interrupt;
+ unsigned int fatal_interrupt;
+
struct clk *active_clks[8];
struct clk *proxy_clks[4];
int active_clk_count;
@@ -170,6 +174,7 @@ struct q6v5 {
struct qcom_rproc_ssr ssr_subdev;
struct qcom_sysmon *sysmon;
bool need_mem_protection;
+ bool unvoted_flag;
int mpss_perm;
int mba_perm;
int version;
@@ -727,6 +732,7 @@ static int q6v5_start(struct rproc *rproc)
int xfermemop_ret;
int ret;
+ qproc->unvoted_flag = false;
ret = q6v5_regulator_enable(qproc, qproc->proxy_regs,
qproc->proxy_reg_count);
if (ret) {
@@ -793,9 +799,16 @@ static int q6v5_start(struct rproc *rproc)
if (ret)
goto reclaim_mpss;
+ enable_irq(qproc->handover_interrupt);
+ enable_irq(qproc->wdog_interrupt);
+ enable_irq(qproc->fatal_interrupt);
+
ret = wait_for_completion_timeout(&qproc->start_done,
msecs_to_jiffies(5000));
if (ret == 0) {
+ disable_irq(qproc->handover_interrupt);
+ disable_irq(qproc->wdog_interrupt);
+ disable_irq(qproc->fatal_interrupt);
dev_err(qproc->dev, "start timed out\n");
ret = -ETIMEDOUT;
goto reclaim_mpss;
@@ -809,11 +822,6 @@ static int q6v5_start(struct rproc *rproc)
"Failed to reclaim mba buffer system may become unstable\n");
qproc->running = true;
- q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
- qproc->proxy_clk_count);
- q6v5_regulator_disable(qproc, qproc->proxy_regs,
- qproc->proxy_reg_count);
-
return 0;
reclaim_mpss:
@@ -892,6 +900,16 @@ static int q6v5_stop(struct rproc *rproc)
WARN_ON(ret);
reset_control_assert(qproc->mss_restart);
+ disable_irq(qproc->handover_interrupt);
+ if (!qproc->unvoted_flag) {
+ q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
+ qproc->proxy_clk_count);
+ q6v5_regulator_disable(qproc, qproc->proxy_regs,
+ qproc->proxy_reg_count);
+ }
+ disable_irq(qproc->wdog_interrupt);
+ disable_irq(qproc->fatal_interrupt);
+
q6v5_clk_disable(qproc->dev, qproc->active_clks,
qproc->active_clk_count);
q6v5_regulator_disable(qproc, qproc->active_regs,
@@ -959,7 +977,7 @@ static irqreturn_t q6v5_fatal_interrupt(int irq, void *dev)
return IRQ_HANDLED;
}
-static irqreturn_t q6v5_handover_interrupt(int irq, void *dev)
+static irqreturn_t q6v5_ready_interrupt(int irq, void *dev)
{
struct q6v5 *qproc = dev;
@@ -967,6 +985,21 @@ static irqreturn_t q6v5_handover_interrupt(int irq, void *dev)
return IRQ_HANDLED;
}
+static irqreturn_t q6v5_handover_interrupt(int irq, void *dev)
+{
+ struct q6v5 *qproc = dev;
+
+ if (!qproc->unvoted_flag) {
+ qproc->unvoted_flag = true;
+ q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
+ qproc->proxy_clk_count);
+ q6v5_regulator_disable(qproc, qproc->proxy_regs,
+ qproc->proxy_reg_count);
+ }
+
+ return IRQ_HANDLED;
+}
+
static irqreturn_t q6v5_stop_ack_interrupt(int irq, void *dev)
{
struct q6v5 *qproc = dev;
@@ -1048,7 +1081,8 @@ static int q6v5_init_reset(struct q6v5 *qproc)
static int q6v5_request_irq(struct q6v5 *qproc,
struct platform_device *pdev,
const char *name,
- irq_handler_t thread_fn)
+ irq_handler_t thread_fn,
+ unsigned int *irq_num)
{
int ret;
@@ -1058,6 +1092,9 @@ static int q6v5_request_irq(struct q6v5 *qproc,
return ret;
}
+ if (irq_num)
+ *irq_num = ret;
+
ret = devm_request_threaded_irq(&pdev->dev, ret,
NULL, thread_fn,
IRQF_TRIGGER_RISING | IRQF_ONESHOT,
@@ -1184,19 +1221,31 @@ static int q6v5_probe(struct platform_device *pdev)
qproc->version = desc->version;
qproc->need_mem_protection = desc->need_mem_protection;
- ret = q6v5_request_irq(qproc, pdev, "wdog", q6v5_wdog_interrupt);
+ ret = q6v5_request_irq(qproc, pdev, "wdog", q6v5_wdog_interrupt,
+ &qproc->wdog_interrupt);
+ if (ret < 0)
+ goto free_rproc;
+ disable_irq(qproc->wdog_interrupt);
+
+ ret = q6v5_request_irq(qproc, pdev, "fatal", q6v5_fatal_interrupt,
+ &qproc->fatal_interrupt);
if (ret < 0)
goto free_rproc;
+ disable_irq(qproc->fatal_interrupt);
- ret = q6v5_request_irq(qproc, pdev, "fatal", q6v5_fatal_interrupt);
+ ret = q6v5_request_irq(qproc, pdev, "ready", q6v5_ready_interrupt,
+ NULL);
if (ret < 0)
goto free_rproc;
- ret = q6v5_request_irq(qproc, pdev, "handover", q6v5_handover_interrupt);
+ ret = q6v5_request_irq(qproc, pdev, "handover", q6v5_handover_interrupt,
+ &qproc->handover_interrupt);
if (ret < 0)
goto free_rproc;
+ disable_irq(qproc->handover_interrupt);
- ret = q6v5_request_irq(qproc, pdev, "stop-ack", q6v5_stop_ack_interrupt);
+ ret = q6v5_request_irq(qproc, pdev, "stop-ack", q6v5_stop_ack_interrupt,
+ NULL);
if (ret < 0)
goto free_rproc;
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 17%]
* [PATCH v4 0/5] Add support for remoteproc modem-pil on SDM845 SoCs
@ 2018-04-25 15:08 13% Sibi Sankar
2018-04-25 15:08 19% ` [PATCH v4 1/5] dt-bindings: reset: Add AOSS reset bindings for " Sibi Sankar
` (4 more replies)
0 siblings, 5 replies; 200+ results
From: Sibi Sankar @ 2018-04-25 15:08 UTC (permalink / raw)
To: bjorn.andersson, p.zabel, robh+dt
Cc: linux-remoteproc, linux-kernel, devicetree, sibis, georgi.djakov,
jassisinghbrar, ohad, mark.rutland, kyan, sricharan, akdwived,
linux-arm-msm, tsoni
This patch series add support for remoteproc Q6v5 modem-pil on Qualcomm
SDM845 SoC. The first patch adds AOSS (Always on subsystem) reset driver
to provide for mss reset line. The last couple of patches add the resets
sequence for Q6 on SDM845 and adds helper functions for arbitrary reset
assert/deassert sequences.
V4:
Removed regmap depencencies from aoss reset driver
Separted apss shared mailbox into separate patch
Corrected all nits and replaced with author full name
V3:
Removed syscon dependency for the aoss reset driver
Split dt-bindings and the aoss reset driver into separate patches
Corrected few typos and replaced misconfigured author name
V2:
Addressed reset-qcom-aoss review suggestions and reworked
re-ordering of the active clk and reset sequence in
qcom_q6v5_pil
Depends on:
https://patchwork.kernel.org/patch/10363397/
Sibi Sankar (5):
dt-bindings: reset: Add AOSS reset bindings for SDM845 SoCs
reset: qcom: AOSS (always on subsystem) reset controller
dt-bindings: remoteproc: Add Q6v5 Modem PIL binding for SDM845
remoteproc: qcom: Add support for mss remoteproc on SDM845
remoteproc: qcom: Always assert and deassert reset signals in SDM845
.../bindings/remoteproc/qcom,q6v5.txt | 1 +
.../bindings/reset/qcom,aoss-reset.txt | 52 +++++++
drivers/remoteproc/qcom_q6v5_pil.c | 144 +++++++++++++++++-
drivers/reset/Kconfig | 9 ++
drivers/reset/Makefile | 1 +
drivers/reset/reset-qcom-aoss.c | 133 ++++++++++++++++
include/dt-bindings/reset/qcom,sdm845-aoss.h | 17 +++
7 files changed, 352 insertions(+), 5 deletions(-)
create mode 100644 Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
create mode 100644 drivers/reset/reset-qcom-aoss.c
create mode 100644 include/dt-bindings/reset/qcom,sdm845-aoss.h
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [relevance 13%]
* [PATCH v4 1/5] dt-bindings: reset: Add AOSS reset bindings for SDM845 SoCs
2018-04-25 15:08 13% [PATCH v4 0/5] Add support for remoteproc modem-pil on SDM845 SoCs Sibi Sankar
@ 2018-04-25 15:08 19% ` Sibi Sankar
2018-04-27 10:24 0% ` Philipp Zabel
2018-04-25 15:08 16% ` [PATCH v4 2/5] reset: qcom: AOSS (always on subsystem) reset controller Sibi Sankar
` (3 subsequent siblings)
4 siblings, 1 reply; 200+ results
From: Sibi Sankar @ 2018-04-25 15:08 UTC (permalink / raw)
To: bjorn.andersson, p.zabel, robh+dt
Cc: linux-remoteproc, linux-kernel, devicetree, sibis, georgi.djakov,
jassisinghbrar, ohad, mark.rutland, kyan, sricharan, akdwived,
linux-arm-msm, tsoni
Add SDM845 AOSS (always on subsystem) reset controller binding
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
.../bindings/reset/qcom,aoss-reset.txt | 52 +++++++++++++++++++
include/dt-bindings/reset/qcom,sdm845-aoss.h | 17 ++++++
2 files changed, 69 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
create mode 100644 include/dt-bindings/reset/qcom,sdm845-aoss.h
diff --git a/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
new file mode 100644
index 000000000000..e5201de9a314
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
@@ -0,0 +1,52 @@
+Qualcomm AOSS Reset Controller
+======================================
+
+This binding describes a reset-controller found on AOSS (always on subsystem)
+for Qualcomm SDM845 SoCs.
+
+Required properties:
+- compatible:
+ Usage: required
+ Value type: <string>
+ Definition: must be:
+ "qcom,sdm845-aoss-reset"
+
+- reg:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: must specify the base address and size of the register
+ space.
+
+- #reset-cells:
+ Usage: required
+ Value type: <uint>
+ Definition: must be 1; cell entry represents the reset index.
+
+Example:
+
+aoss_reset: qcom,reset-controller@b2e0100 {
+ compatible = "qcom,sdm845-aoss-reset";
+ reg = <0xc2b0000 0x21000>;
+ #reset-cells = <1>;
+};
+
+Specifying reset lines connected to IP modules
+==============================================
+
+Device nodes that need access to reset lines should
+specify them as a reset phandle in their corresponding node as
+specified in reset.txt.
+
+For list of all valid reset indicies see
+<dt-bindings/reset/qcom,sdm845-aoss.h>
+
+Example:
+
+modem-pil@4080000 {
+ ...
+
+ resets = <&aoss_reset AOSS_CC_MSS_RESTART>;
+ reset-names = "mss_restart";
+
+ ...
+};
diff --git a/include/dt-bindings/reset/qcom,sdm845-aoss.h b/include/dt-bindings/reset/qcom,sdm845-aoss.h
new file mode 100644
index 000000000000..476c5fc873b6
--- /dev/null
+++ b/include/dt-bindings/reset/qcom,sdm845-aoss.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_RESET_AOSS_SDM_845_H
+#define _DT_BINDINGS_RESET_AOSS_SDM_845_H
+
+#define AOSS_CC_MSS_RESTART 0
+#define AOSS_CC_CAMSS_RESTART 1
+#define AOSS_CC_VENUS_RESTART 2
+#define AOSS_CC_GPU_RESTART 3
+#define AOSS_CC_DISPSS_RESTART 4
+#define AOSS_CC_WCSS_RESTART 5
+#define AOSS_CC_LPASS_RESTART 6
+
+#endif
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 19%]
* [PATCH v4 2/5] reset: qcom: AOSS (always on subsystem) reset controller
2018-04-25 15:08 13% [PATCH v4 0/5] Add support for remoteproc modem-pil on SDM845 SoCs Sibi Sankar
2018-04-25 15:08 19% ` [PATCH v4 1/5] dt-bindings: reset: Add AOSS reset bindings for " Sibi Sankar
@ 2018-04-25 15:08 16% ` Sibi Sankar
2018-04-27 10:41 0% ` Philipp Zabel
2018-04-25 15:08 21% ` [PATCH v4 3/5] dt-bindings: remoteproc: Add Q6v5 Modem PIL binding for SDM845 Sibi Sankar
` (2 subsequent siblings)
4 siblings, 1 reply; 200+ results
From: Sibi Sankar @ 2018-04-25 15:08 UTC (permalink / raw)
To: bjorn.andersson, p.zabel, robh+dt
Cc: linux-remoteproc, linux-kernel, devicetree, sibis, georgi.djakov,
jassisinghbrar, ohad, mark.rutland, kyan, sricharan, akdwived,
linux-arm-msm, tsoni
Add reset controller driver for Qualcomm SDM845 SoC to
control reset signals provided by AOSS for Modem, Venus
ADSP, GPU, Camera, Wireless, Display subsystem
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
drivers/reset/Kconfig | 9 +++
drivers/reset/Makefile | 1 +
drivers/reset/reset-qcom-aoss.c | 133 ++++++++++++++++++++++++++++++++
3 files changed, 143 insertions(+)
create mode 100644 drivers/reset/reset-qcom-aoss.c
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index c0b292be1b72..756ad2b27d0f 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -82,6 +82,15 @@ config RESET_PISTACHIO
help
This enables the reset driver for ImgTec Pistachio SoCs.
+config RESET_QCOM_AOSS
+ bool "Qcom AOSS Reset Driver"
+ depends on ARCH_QCOM || COMPILE_TEST
+ help
+ This enables the AOSS (always on subsystem) reset driver
+ for Qualcomm SDM845 SoCs. Say Y if you want to control
+ reset signals provided by AOSS for Modem, Venus, ADSP,
+ GPU, Camera, Wireless, Display subsystem. Otherwise, say N.
+
config RESET_SIMPLE
bool "Simple Reset Controller Driver" if COMPILE_TEST
default ARCH_SOCFPGA || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index c1261dcfe9ad..6881e4d287f0 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
obj-$(CONFIG_RESET_MESON) += reset-meson.o
obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o
+obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o
obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
obj-$(CONFIG_RESET_STM32MP157) += reset-stm32mp1.o
obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
diff --git a/drivers/reset/reset-qcom-aoss.c b/drivers/reset/reset-qcom-aoss.c
new file mode 100644
index 000000000000..3b0bbb387f7b
--- /dev/null
+++ b/drivers/reset/reset-qcom-aoss.c
@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/of_device.h>
+#include <dt-bindings/reset/qcom,sdm845-aoss.h>
+
+struct qcom_aoss_reset_map {
+ unsigned int reg;
+};
+
+struct qcom_aoss_desc {
+ const struct qcom_aoss_reset_map *resets;
+ size_t num_resets;
+};
+
+struct qcom_aoss_reset_data {
+ struct reset_controller_dev rcdev;
+ void __iomem *base;
+ const struct qcom_aoss_desc *desc;
+};
+
+static const struct qcom_aoss_reset_map sdm845_aoss_resets[] = {
+ [AOSS_CC_MSS_RESTART] = {0x0},
+ [AOSS_CC_CAMSS_RESTART] = {0x1000},
+ [AOSS_CC_VENUS_RESTART] = {0x2000},
+ [AOSS_CC_GPU_RESTART] = {0x3000},
+ [AOSS_CC_DISPSS_RESTART] = {0x4000},
+ [AOSS_CC_WCSS_RESTART] = {0x10000},
+ [AOSS_CC_LPASS_RESTART] = {0x20000},
+};
+
+static const struct qcom_aoss_desc sdm845_aoss_desc = {
+ .resets = sdm845_aoss_resets,
+ .num_resets = ARRAY_SIZE(sdm845_aoss_resets),
+};
+
+static inline struct qcom_aoss_reset_data *to_qcom_aoss_reset_data(
+ struct reset_controller_dev *rcdev)
+{
+ return container_of(rcdev, struct qcom_aoss_reset_data, rcdev);
+}
+
+static int qcom_aoss_control_assert(struct reset_controller_dev *rcdev,
+ unsigned long idx)
+{
+ struct qcom_aoss_reset_data *data = to_qcom_aoss_reset_data(rcdev);
+ const struct qcom_aoss_reset_map *map = &data->desc->resets[idx];
+
+ writel(1, data->base + map->reg);
+ /* Wait 6 32kHz sleep cycles for reset */
+ usleep_range(200, 210);
+ return 0;
+}
+
+static int qcom_aoss_control_deassert(struct reset_controller_dev *rcdev,
+ unsigned long idx)
+{
+ struct qcom_aoss_reset_data *data = to_qcom_aoss_reset_data(rcdev);
+ const struct qcom_aoss_reset_map *map = &data->desc->resets[idx];
+
+ writel(0, data->base + map->reg);
+ /* Wait 6 32kHz sleep cycles for reset */
+ usleep_range(200, 210);
+ return 0;
+}
+
+static int qcom_aoss_control_reset(struct reset_controller_dev *rcdev,
+ unsigned long idx)
+{
+ qcom_aoss_control_assert(rcdev, idx);
+
+ return qcom_aoss_control_deassert(rcdev, idx);
+}
+
+static const struct reset_control_ops qcom_aoss_reset_ops = {
+ .reset = qcom_aoss_control_reset,
+ .assert = qcom_aoss_control_assert,
+ .deassert = qcom_aoss_control_deassert,
+};
+
+static int qcom_aoss_reset_probe(struct platform_device *pdev)
+{
+ struct qcom_aoss_reset_data *data;
+ struct device *dev = &pdev->dev;
+ const struct qcom_aoss_desc *desc;
+ struct resource *res;
+
+ desc = of_device_get_match_data(dev);
+ if (!desc)
+ return -EINVAL;
+
+ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ data->desc = desc;
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ data->base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(data->base))
+ return PTR_ERR(data->base);
+
+ data->rcdev.owner = THIS_MODULE;
+ data->rcdev.ops = &qcom_aoss_reset_ops;
+ data->rcdev.nr_resets = desc->num_resets;
+ data->rcdev.of_node = dev->of_node;
+
+ return devm_reset_controller_register(dev, &data->rcdev);
+}
+
+static const struct of_device_id qcom_aoss_reset_of_match[] = {
+ { .compatible = "qcom,sdm845-aoss-reset", .data = &sdm845_aoss_desc },
+ {}
+};
+
+static struct platform_driver qcom_aoss_reset_driver = {
+ .probe = qcom_aoss_reset_probe,
+ .driver = {
+ .name = "qcom_aoss_reset",
+ .of_match_table = qcom_aoss_reset_of_match,
+ },
+};
+
+builtin_platform_driver(qcom_aoss_reset_driver);
+
+MODULE_DESCRIPTION("Qualcomm AOSS Reset Driver");
+MODULE_LICENSE("GPL v2");
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 16%]
* [PATCH v4 3/5] dt-bindings: remoteproc: Add Q6v5 Modem PIL binding for SDM845
2018-04-25 15:08 13% [PATCH v4 0/5] Add support for remoteproc modem-pil on SDM845 SoCs Sibi Sankar
2018-04-25 15:08 19% ` [PATCH v4 1/5] dt-bindings: reset: Add AOSS reset bindings for " Sibi Sankar
2018-04-25 15:08 16% ` [PATCH v4 2/5] reset: qcom: AOSS (always on subsystem) reset controller Sibi Sankar
@ 2018-04-25 15:08 21% ` Sibi Sankar
2018-04-27 14:32 0% ` Rob Herring
2018-04-25 15:08 18% ` [PATCH v4 4/5] remoteproc: qcom: Add support for mss remoteproc on SDM845 Sibi Sankar
2018-04-25 15:08 16% ` [PATCH v4 5/5] remoteproc: qcom: Always assert and deassert reset signals in SDM845 Sibi Sankar
4 siblings, 1 reply; 200+ results
From: Sibi Sankar @ 2018-04-25 15:08 UTC (permalink / raw)
To: bjorn.andersson, p.zabel, robh+dt
Cc: linux-remoteproc, linux-kernel, devicetree, sibis, georgi.djakov,
jassisinghbrar, ohad, mark.rutland, kyan, sricharan, akdwived,
linux-arm-msm, tsoni
Add new compatible string for Qualcomm SDM845 SoCs
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
index 00d3d58a102f..d90182425450 100644
--- a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
+++ b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
@@ -11,6 +11,7 @@ on the Qualcomm Hexagon core.
"qcom,msm8916-mss-pil",
"qcom,msm8974-mss-pil"
"qcom,msm8996-mss-pil"
+ "qcom,sdm845-mss-pil"
- reg:
Usage: required
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 21%]
* [PATCH v4 4/5] remoteproc: qcom: Add support for mss remoteproc on SDM845
2018-04-25 15:08 13% [PATCH v4 0/5] Add support for remoteproc modem-pil on SDM845 SoCs Sibi Sankar
` (2 preceding siblings ...)
2018-04-25 15:08 21% ` [PATCH v4 3/5] dt-bindings: remoteproc: Add Q6v5 Modem PIL binding for SDM845 Sibi Sankar
@ 2018-04-25 15:08 18% ` Sibi Sankar
2018-05-18 21:31 0% ` Bjorn Andersson
2018-04-25 15:08 16% ` [PATCH v4 5/5] remoteproc: qcom: Always assert and deassert reset signals in SDM845 Sibi Sankar
4 siblings, 1 reply; 200+ results
From: Sibi Sankar @ 2018-04-25 15:08 UTC (permalink / raw)
To: bjorn.andersson, p.zabel, robh+dt
Cc: linux-remoteproc, linux-kernel, devicetree, sibis, georgi.djakov,
jassisinghbrar, ohad, mark.rutland, kyan, sricharan, akdwived,
linux-arm-msm, tsoni
>From SDM845, the Q6SS reset sequence on software side has been
simplified with the introduction of boot FSM which assists in
bringing the Q6 out of reset
Add GLINK subdevice to allow definition of GLINK edge as a
child of modem-pil
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
drivers/remoteproc/qcom_q6v5_pil.c | 65 +++++++++++++++++++++++++++++-
1 file changed, 64 insertions(+), 1 deletion(-)
diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
index 7e2d04d4f2f0..4d9504e8bf8e 100644
--- a/drivers/remoteproc/qcom_q6v5_pil.c
+++ b/drivers/remoteproc/qcom_q6v5_pil.c
@@ -57,6 +57,8 @@
#define RMB_PMI_META_DATA_REG 0x10
#define RMB_PMI_CODE_START_REG 0x14
#define RMB_PMI_CODE_LENGTH_REG 0x18
+#define RMB_MBA_MSS_STATUS 0x40
+#define RMB_MBA_ALT_RESET 0x44
#define RMB_CMD_META_DATA_READY 0x1
#define RMB_CMD_LOAD_READY 0x2
@@ -104,6 +106,13 @@
#define QDSP6SS_XO_CBCR 0x0038
#define QDSP6SS_ACC_OVERRIDE_VAL 0x20
+/* QDSP6v65 parameters */
+#define QDSP6SS_SLEEP 0x3C
+#define QDSP6SS_BOOT_CORE_START 0x400
+#define QDSP6SS_BOOT_CMD 0x404
+#define SLEEP_CHECK_MAX_LOOPS 200
+#define BOOT_FSM_TIMEOUT 10000
+
struct reg_info {
struct regulator *reg;
int uV;
@@ -170,6 +179,7 @@ struct q6v5 {
void *mpss_region;
size_t mpss_size;
+ struct qcom_rproc_glink glink_subdev;
struct qcom_rproc_subdev smd_subdev;
struct qcom_rproc_ssr ssr_subdev;
struct qcom_sysmon *sysmon;
@@ -184,6 +194,7 @@ enum {
MSS_MSM8916,
MSS_MSM8974,
MSS_MSM8996,
+ MSS_SDM845,
};
static int q6v5_regulator_init(struct device *dev, struct reg_info *regs,
@@ -390,8 +401,35 @@ static int q6v5proc_reset(struct q6v5 *qproc)
int ret;
int i;
+ if (qproc->version == MSS_SDM845) {
- if (qproc->version == MSS_MSM8996) {
+ val = readl(qproc->reg_base + QDSP6SS_SLEEP);
+ val |= 0x1;
+ writel(val, qproc->reg_base + QDSP6SS_SLEEP);
+
+ ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_SLEEP,
+ val, !(val & BIT(31)), 1,
+ SLEEP_CHECK_MAX_LOOPS);
+ if (ret) {
+ dev_err(qproc->dev, "QDSP6SS Sleep clock timed out\n");
+ return -ETIMEDOUT;
+ }
+
+ /* De-assert QDSP6 stop core */
+ writel(1, qproc->reg_base + QDSP6SS_BOOT_CORE_START);
+ /* Trigger boot FSM */
+ writel(1, qproc->reg_base + QDSP6SS_BOOT_CMD);
+
+ ret = readl_poll_timeout(qproc->rmb_base + RMB_MBA_MSS_STATUS,
+ val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT);
+ if (ret) {
+ dev_err(qproc->dev, "Boot FSM failed to complete.\n");
+ return ret;
+ }
+
+ goto pbl_wait;
+
+ } else if (qproc->version == MSS_MSM8996) {
/* Override the ACC value if required */
writel(QDSP6SS_ACC_OVERRIDE_VAL,
qproc->reg_base + QDSP6SS_STRAP_ACC);
@@ -499,6 +537,7 @@ static int q6v5proc_reset(struct q6v5 *qproc)
val &= ~Q6SS_STOP_CORE;
writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
+pbl_wait:
/* Wait for PBL status */
ret = q6v5_rmb_pbl_wait(qproc, 1000);
if (ret == -ETIMEDOUT) {
@@ -1256,6 +1295,7 @@ static int q6v5_probe(struct platform_device *pdev)
}
qproc->mpss_perm = BIT(QCOM_SCM_VMID_HLOS);
qproc->mba_perm = BIT(QCOM_SCM_VMID_HLOS);
+ qcom_add_glink_subdev(rproc, &qproc->glink_subdev);
qcom_add_smd_subdev(rproc, &qproc->smd_subdev);
qcom_add_ssr_subdev(rproc, &qproc->ssr_subdev, "mpss");
qproc->sysmon = qcom_add_sysmon_subdev(rproc, "modem", 0x12);
@@ -1279,6 +1319,7 @@ static int q6v5_remove(struct platform_device *pdev)
rproc_del(qproc->rproc);
qcom_remove_sysmon_subdev(qproc->sysmon);
+ qcom_remove_glink_subdev(qproc->rproc, &qproc->glink_subdev);
qcom_remove_smd_subdev(qproc->rproc, &qproc->smd_subdev);
qcom_remove_ssr_subdev(qproc->rproc, &qproc->ssr_subdev);
rproc_free(qproc->rproc);
@@ -1286,6 +1327,27 @@ static int q6v5_remove(struct platform_device *pdev)
return 0;
}
+static const struct rproc_hexagon_res sdm845_mss = {
+ .hexagon_mba_image = "mba.mbn",
+ .proxy_clk_names = (char*[]){
+ "xo",
+ "axis2",
+ "prng",
+ NULL
+ },
+ .active_clk_names = (char*[]){
+ "iface",
+ "bus",
+ "mem",
+ "gpll0_mss",
+ "snoc_axi",
+ "mnoc_axi",
+ NULL
+ },
+ .need_mem_protection = true,
+ .version = MSS_SDM845,
+};
+
static const struct rproc_hexagon_res msm8996_mss = {
.hexagon_mba_image = "mba.mbn",
.proxy_clk_names = (char*[]){
@@ -1379,6 +1441,7 @@ static const struct of_device_id q6v5_of_match[] = {
{ .compatible = "qcom,msm8916-mss-pil", .data = &msm8916_mss},
{ .compatible = "qcom,msm8974-mss-pil", .data = &msm8974_mss},
{ .compatible = "qcom,msm8996-mss-pil", .data = &msm8996_mss},
+ { .compatible = "qcom,sdm845-mss-pil", .data = &sdm845_mss},
{ },
};
MODULE_DEVICE_TABLE(of, q6v5_of_match);
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 18%]
* [PATCH v4 5/5] remoteproc: qcom: Always assert and deassert reset signals in SDM845
2018-04-25 15:08 13% [PATCH v4 0/5] Add support for remoteproc modem-pil on SDM845 SoCs Sibi Sankar
` (3 preceding siblings ...)
2018-04-25 15:08 18% ` [PATCH v4 4/5] remoteproc: qcom: Add support for mss remoteproc on SDM845 Sibi Sankar
@ 2018-04-25 15:08 16% ` Sibi Sankar
2018-05-18 21:47 0% ` Bjorn Andersson
4 siblings, 1 reply; 200+ results
From: Sibi Sankar @ 2018-04-25 15:08 UTC (permalink / raw)
To: bjorn.andersson, p.zabel, robh+dt
Cc: linux-remoteproc, linux-kernel, devicetree, sibis, georgi.djakov,
jassisinghbrar, ohad, mark.rutland, kyan, sricharan, akdwived,
linux-arm-msm, tsoni
SDM845 brings a new reset signal ALT_RESET which is a part of the MSS
subsystem hence requires some of the active clks to be enabled before
assert/deassert
Reset the modem if the BOOT FSM does timeout
Reset assert/deassert sequence vary across SoCs adding reset, adding
start/stop helper functions to handle SoC specific reset sequences
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
drivers/remoteproc/qcom_q6v5_pil.c | 81 ++++++++++++++++++++++++++++--
1 file changed, 76 insertions(+), 5 deletions(-)
diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
index 4d9504e8bf8e..99ef3f51c528 100644
--- a/drivers/remoteproc/qcom_q6v5_pil.c
+++ b/drivers/remoteproc/qcom_q6v5_pil.c
@@ -130,9 +130,11 @@ struct rproc_hexagon_res {
struct qcom_mss_reg_res *proxy_supply;
struct qcom_mss_reg_res *active_supply;
char **proxy_clk_names;
+ char **reset_clk_names;
char **active_clk_names;
int version;
bool need_mem_protection;
+ bool has_alt_reset;
};
struct q6v5 {
@@ -157,8 +159,10 @@ struct q6v5 {
unsigned int fatal_interrupt;
struct clk *active_clks[8];
+ struct clk *reset_clks[4];
struct clk *proxy_clks[4];
int active_clk_count;
+ int reset_clk_count;
int proxy_clk_count;
struct reg_info active_regs[1];
@@ -179,6 +183,9 @@ struct q6v5 {
void *mpss_region;
size_t mpss_size;
+ int (*reset_deassert)(struct q6v5 *qproc);
+ int (*reset_assert)(struct q6v5 *qproc);
+
struct qcom_rproc_glink glink_subdev;
struct qcom_rproc_subdev smd_subdev;
struct qcom_rproc_ssr ssr_subdev;
@@ -349,6 +356,32 @@ static int q6v5_load(struct rproc *rproc, const struct firmware *fw)
return 0;
}
+static int q6v5_reset_assert(struct q6v5 *qproc)
+{
+ return reset_control_assert(qproc->mss_restart);
+}
+
+static int q6v5_reset_deassert(struct q6v5 *qproc)
+{
+ return reset_control_deassert(qproc->mss_restart);
+}
+
+static int q6v5_alt_reset_assert(struct q6v5 *qproc)
+{
+ return reset_control_reset(qproc->mss_restart);
+}
+
+static int q6v5_alt_reset_deassert(struct q6v5 *qproc)
+{
+ /* Ensure alt reset is written before restart reg */
+ writel(1, qproc->rmb_base + RMB_MBA_ALT_RESET);
+
+ reset_control_reset(qproc->mss_restart);
+
+ writel(0, qproc->rmb_base + RMB_MBA_ALT_RESET);
+ return 0;
+}
+
static int q6v5_rmb_pbl_wait(struct q6v5 *qproc, int ms)
{
unsigned long timeout;
@@ -424,6 +457,8 @@ static int q6v5proc_reset(struct q6v5 *qproc)
val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT);
if (ret) {
dev_err(qproc->dev, "Boot FSM failed to complete.\n");
+ /* Reset the modem so that boot FSM is in reset state */
+ qproc->reset_deassert(qproc);
return ret;
}
@@ -792,12 +827,20 @@ static int q6v5_start(struct rproc *rproc)
dev_err(qproc->dev, "failed to enable supplies\n");
goto disable_proxy_clk;
}
- ret = reset_control_deassert(qproc->mss_restart);
+
+ ret = q6v5_clk_enable(qproc->dev, qproc->reset_clks,
+ qproc->reset_clk_count);
if (ret) {
- dev_err(qproc->dev, "failed to deassert mss restart\n");
+ dev_err(qproc->dev, "failed to enable reset clocks\n");
goto disable_vdd;
}
+ ret = qproc->reset_deassert(qproc);
+ if (ret) {
+ dev_err(qproc->dev, "failed to deassert mss restart\n");
+ goto disable_reset_clks;
+ }
+
ret = q6v5_clk_enable(qproc->dev, qproc->active_clks,
qproc->active_clk_count);
if (ret) {
@@ -888,7 +931,10 @@ static int q6v5_start(struct rproc *rproc)
qproc->active_clk_count);
assert_reset:
- reset_control_assert(qproc->mss_restart);
+ qproc->reset_assert(qproc);
+disable_reset_clks:
+ q6v5_clk_disable(qproc->dev, qproc->reset_clks,
+ qproc->reset_clk_count);
disable_vdd:
q6v5_regulator_disable(qproc, qproc->active_regs,
qproc->active_reg_count);
@@ -938,7 +984,7 @@ static int q6v5_stop(struct rproc *rproc)
qproc->mpss_phys, qproc->mpss_size);
WARN_ON(ret);
- reset_control_assert(qproc->mss_restart);
+ qproc->reset_assert(qproc);
disable_irq(qproc->handover_interrupt);
if (!qproc->unvoted_flag) {
q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
@@ -949,6 +995,8 @@ static int q6v5_stop(struct rproc *rproc)
disable_irq(qproc->wdog_interrupt);
disable_irq(qproc->fatal_interrupt);
+ q6v5_clk_disable(qproc->dev, qproc->reset_clks,
+ qproc->reset_clk_count);
q6v5_clk_disable(qproc->dev, qproc->active_clks,
qproc->active_clk_count);
q6v5_regulator_disable(qproc, qproc->active_regs,
@@ -1211,6 +1259,14 @@ static int q6v5_probe(struct platform_device *pdev)
qproc->rproc = rproc;
platform_set_drvdata(pdev, qproc);
+ if (desc->has_alt_reset) {
+ qproc->reset_deassert = q6v5_alt_reset_deassert;
+ qproc->reset_assert = q6v5_alt_reset_assert;
+ } else {
+ qproc->reset_deassert = q6v5_reset_deassert;
+ qproc->reset_assert = q6v5_reset_assert;
+ }
+
init_completion(&qproc->start_done);
init_completion(&qproc->stop_done);
@@ -1230,6 +1286,14 @@ static int q6v5_probe(struct platform_device *pdev)
}
qproc->proxy_clk_count = ret;
+ ret = q6v5_init_clocks(&pdev->dev, qproc->reset_clks,
+ desc->reset_clk_names);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "Failed to get reset clocks.\n");
+ goto free_rproc;
+ }
+ qproc->reset_clk_count = ret;
+
ret = q6v5_init_clocks(&pdev->dev, qproc->active_clks,
desc->active_clk_names);
if (ret < 0) {
@@ -1335,8 +1399,11 @@ static const struct rproc_hexagon_res sdm845_mss = {
"prng",
NULL
},
- .active_clk_names = (char*[]){
+ .reset_clk_names = (char*[]){
"iface",
+ NULL
+ },
+ .active_clk_names = (char*[]){
"bus",
"mem",
"gpll0_mss",
@@ -1345,6 +1412,7 @@ static const struct rproc_hexagon_res sdm845_mss = {
NULL
},
.need_mem_protection = true,
+ .has_alt_reset = true,
.version = MSS_SDM845,
};
@@ -1363,6 +1431,7 @@ static const struct rproc_hexagon_res msm8996_mss = {
NULL
},
.need_mem_protection = true,
+ .has_alt_reset = false,
.version = MSS_MSM8996,
};
@@ -1394,6 +1463,7 @@ static const struct rproc_hexagon_res msm8916_mss = {
NULL
},
.need_mem_protection = false,
+ .has_alt_reset = false,
.version = MSS_MSM8916,
};
@@ -1433,6 +1503,7 @@ static const struct rproc_hexagon_res msm8974_mss = {
NULL
},
.need_mem_protection = false,
+ .has_alt_reset = false,
.version = MSS_MSM8974,
};
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 16%]
* Re: [PATCH 2/3] mailbox: Add support for Qualcomm SDM845 SoCs
2018-04-25 14:38 21% ` [PATCH 2/3] mailbox: Add support for Qualcomm " Sibi Sankar
@ 2018-04-25 16:26 0% ` Bjorn Andersson
0 siblings, 0 replies; 200+ results
From: Bjorn Andersson @ 2018-04-25 16:26 UTC (permalink / raw)
To: Sibi Sankar
Cc: andy.gross, mark.rutland, david.brown, linux-arm-msm,
georgi.djakov, devicetree, linux-soc, linux-kernel,
jassisinghbrar, will.deacon, catalin.marinas
On Wed 25 Apr 07:38 PDT 2018, Sibi Sankar wrote:
> Add the corresponding APSS shared offset for SDM845 SoC
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Regards,
Bjorn
> ---
> drivers/mailbox/qcom-apcs-ipc-mailbox.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
> index 57bde0dfd12f..75da44d25fac 100644
> --- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c
> +++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
> @@ -125,6 +125,7 @@ static int qcom_apcs_ipc_remove(struct platform_device *pdev)
> static const struct of_device_id qcom_apcs_ipc_of_match[] = {
> { .compatible = "qcom,msm8916-apcs-kpss-global", .data = (void *)8 },
> { .compatible = "qcom,msm8996-apcs-hmss-global", .data = (void *)16 },
> + { .compatible = "qcom,sdm845-apss-shared", .data = (void *)12 },
> {}
> };
> MODULE_DEVICE_TABLE(of, qcom_apcs_ipc_of_match);
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
^ permalink raw reply [relevance 0%]
* Re: [PATCH 1/3] dt-bindings: mailbox: Add APSS shared binding for SDM845 SoCs
2018-04-25 14:38 21% [PATCH 1/3] dt-bindings: mailbox: Add APSS shared binding for SDM845 SoCs Sibi Sankar
2018-04-25 14:38 21% ` [PATCH 2/3] mailbox: Add support for Qualcomm " Sibi Sankar
2018-04-25 14:38 21% ` [PATCH 3/3] arm64: dts: qcom: Add APSS shared mailbox node to SDM845 Sibi Sankar
@ 2018-04-25 16:26 0% ` Bjorn Andersson
2018-05-01 14:28 0% ` Rob Herring
3 siblings, 0 replies; 200+ results
From: Bjorn Andersson @ 2018-04-25 16:26 UTC (permalink / raw)
To: Sibi Sankar
Cc: andy.gross, mark.rutland, david.brown, linux-arm-msm,
georgi.djakov, devicetree, linux-soc, linux-kernel,
jassisinghbrar, will.deacon, catalin.marinas
On Wed 25 Apr 07:38 PDT 2018, Sibi Sankar wrote:
> Include SDM845 APSS shared to the list of possible bindings
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Regards,
Bjorn
> ---
> .../devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt
> index 16964f0c1773..8ea0f12b8d0b 100644
> --- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt
> +++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt
> @@ -10,6 +10,7 @@ platforms.
> Definition: must be one of:
> "qcom,msm8916-apcs-kpss-global",
> "qcom,msm8996-apcs-hmss-global"
> + "qcom,sdm845-apss-shared"
>
> - reg:
> Usage: required
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
^ permalink raw reply [relevance 0%]
* Re: [PATCH 3/3] arm64: dts: qcom: Add APSS shared mailbox node to SDM845
2018-04-25 14:38 21% ` [PATCH 3/3] arm64: dts: qcom: Add APSS shared mailbox node to SDM845 Sibi Sankar
@ 2018-04-25 16:30 0% ` Bjorn Andersson
0 siblings, 0 replies; 200+ results
From: Bjorn Andersson @ 2018-04-25 16:30 UTC (permalink / raw)
To: Sibi Sankar
Cc: andy.gross, mark.rutland, david.brown, linux-arm-msm,
georgi.djakov, devicetree, linux-soc, linux-kernel,
jassisinghbrar, will.deacon, catalin.marinas
On Wed 25 Apr 07:38 PDT 2018, Sibi Sankar wrote:
> This patch add the node to support APSS shared
> mailbox on SDM845
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Regards,
Bjorn
> ---
>
> This patch depends on https://patchwork.kernel.org/patch/10276419/
>
> arch/arm64/boot/dts/qcom/sdm845.dtsi | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> index 486ace9a9e8b..9be763da0664 100644
> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> @@ -338,5 +338,11 @@
> status = "disabled";
> };
> };
> +
> + apss_shared: mailbox@17990000 {
> + compatible = "qcom,sdm845-apss-shared";
> + reg = <0x17990000 0x1000>;
> + #mbox-cells = <1>;
> + };
> };
> };
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
^ permalink raw reply [relevance 0%]
* Re: [PATCH] arm64: dts: qcom: Add SDM845 SMEM nodes
@ 2018-04-26 14:25 6% ` Sibi S
0 siblings, 0 replies; 200+ results
From: Sibi S @ 2018-04-26 14:25 UTC (permalink / raw)
To: Bjorn Andersson
Cc: andy.gross, david.brown, robh+dt, mark.rutland, catalin.marinas,
will.deacon, linux-arm-msm, linux-kernel, devicetree, linux-soc
Hi Bjorn,
Thanks for the review
On 04/26/2018 03:36 AM, Bjorn Andersson wrote:
> On Wed 25 Apr 07:46 PDT 2018, Sibi Sankar wrote:
>> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
>> index 9be763da0664..bea985045759 100644
>> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
>> @@ -21,6 +21,27 @@
>> reg = <0 0x80000000 0 0>;
>> };
>>
>> + reserved-memory {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> +
>> + memory@85fc0000 {
>> + reg = <0 0x85fc0000 0 0x40000>;
>
> The region 0x85fe0000 + 0x20000 seems to be command db, which should be
> described on its own. So please reduce the size to 0x20000.
>
>> + no-map;
>> + };
>> +
>> + smem_mem: smem-mem@86000000 {
>
> smem_mem: memory@86000000 ?
Should I update kernel docs as well to say all nodes should
have memory has default name? Just followed what was done in
msm8916 and msm8996.
>
>> + reg = <0x0 0x86000000 0x0 0x200000>;
>> + no-map;
>> + };
>> +
>> + memory@86000000 {
>
> memory@86200000
>
>> + reg = <0 0x86200000 0 0x2d00000>;
>> + no-map;
>> + };
>> + };
>> +
>
> The rest looks good.
>
> Regards,
> Bjorn
>
--
Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc, is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [relevance 6%]
* Re: [PATCH v4 1/5] dt-bindings: reset: Add AOSS reset bindings for SDM845 SoCs
2018-04-25 15:08 19% ` [PATCH v4 1/5] dt-bindings: reset: Add AOSS reset bindings for " Sibi Sankar
@ 2018-04-27 10:24 0% ` Philipp Zabel
2018-04-27 10:45 6% ` Sibi S
0 siblings, 1 reply; 200+ results
From: Philipp Zabel @ 2018-04-27 10:24 UTC (permalink / raw)
To: Sibi Sankar, bjorn.andersson, robh+dt
Cc: linux-remoteproc, linux-kernel, devicetree, georgi.djakov,
jassisinghbrar, ohad, mark.rutland, kyan, sricharan, akdwived,
linux-arm-msm, tsoni
Hi Sibi,
On Wed, 2018-04-25 at 20:38 +0530, Sibi Sankar wrote:
> Add SDM845 AOSS (always on subsystem) reset controller binding
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
> .../bindings/reset/qcom,aoss-reset.txt | 52 +++++++++++++++++++
> include/dt-bindings/reset/qcom,sdm845-aoss.h | 17 ++++++
> 2 files changed, 69 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
> create mode 100644 include/dt-bindings/reset/qcom,sdm845-aoss.h
>
> diff --git a/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
> new file mode 100644
> index 000000000000..e5201de9a314
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
> @@ -0,0 +1,52 @@
> +Qualcomm AOSS Reset Controller
> +======================================
> +
> +This binding describes a reset-controller found on AOSS (always on subsystem)
> +for Qualcomm SDM845 SoCs.
> +
> +Required properties:
> +- compatible:
> + Usage: required
> + Value type: <string>
> + Definition: must be:
> + "qcom,sdm845-aoss-reset"
> +
> +- reg:
> + Usage: required
> + Value type: <prop-encoded-array>
> + Definition: must specify the base address and size of the register
> + space.
> +
> +- #reset-cells:
> + Usage: required
> + Value type: <uint>
> + Definition: must be 1; cell entry represents the reset index.
> +
> +Example:
> +
> +aoss_reset: qcom,reset-controller@b2e0100 {
The node name should be "reset-controller", not "qcom,reset-controller"
> + compatible = "qcom,sdm845-aoss-reset";
> + reg = <0xc2b0000 0x21000>;
The address here should match the address part of the node name above.
Apart from those two nitpicks, the binding looks good to me.
regards
Philipp
^ permalink raw reply [relevance 0%]
* Re: [PATCH v4 2/5] reset: qcom: AOSS (always on subsystem) reset controller
2018-04-25 15:08 16% ` [PATCH v4 2/5] reset: qcom: AOSS (always on subsystem) reset controller Sibi Sankar
@ 2018-04-27 10:41 0% ` Philipp Zabel
2018-04-27 11:15 6% ` Sibi S
0 siblings, 1 reply; 200+ results
From: Philipp Zabel @ 2018-04-27 10:41 UTC (permalink / raw)
To: Sibi Sankar, bjorn.andersson, robh+dt
Cc: linux-remoteproc, linux-kernel, devicetree, georgi.djakov,
jassisinghbrar, ohad, mark.rutland, kyan, sricharan, akdwived,
linux-arm-msm, tsoni
On Wed, 2018-04-25 at 20:38 +0530, Sibi Sankar wrote:
> Add reset controller driver for Qualcomm SDM845 SoC to
> control reset signals provided by AOSS for Modem, Venus
> ADSP, GPU, Camera, Wireless, Display subsystem
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
> drivers/reset/Kconfig | 9 +++
> drivers/reset/Makefile | 1 +
> drivers/reset/reset-qcom-aoss.c | 133 ++++++++++++++++++++++++++++++++
> 3 files changed, 143 insertions(+)
> create mode 100644 drivers/reset/reset-qcom-aoss.c
>
> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
> index c0b292be1b72..756ad2b27d0f 100644
> --- a/drivers/reset/Kconfig
> +++ b/drivers/reset/Kconfig
> @@ -82,6 +82,15 @@ config RESET_PISTACHIO
> help
> This enables the reset driver for ImgTec Pistachio SoCs.
>
> +config RESET_QCOM_AOSS
> + bool "Qcom AOSS Reset Driver"
> + depends on ARCH_QCOM || COMPILE_TEST
> + help
> + This enables the AOSS (always on subsystem) reset driver
> + for Qualcomm SDM845 SoCs. Say Y if you want to control
> + reset signals provided by AOSS for Modem, Venus, ADSP,
> + GPU, Camera, Wireless, Display subsystem. Otherwise, say N.
> +
> config RESET_SIMPLE
> bool "Simple Reset Controller Driver" if COMPILE_TEST
> default ARCH_SOCFPGA || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED
> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
> index c1261dcfe9ad..6881e4d287f0 100644
> --- a/drivers/reset/Makefile
> +++ b/drivers/reset/Makefile
> @@ -14,6 +14,7 @@ obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
> obj-$(CONFIG_RESET_MESON) += reset-meson.o
> obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
> obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o
> +obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o
> obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
> obj-$(CONFIG_RESET_STM32MP157) += reset-stm32mp1.o
> obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
> diff --git a/drivers/reset/reset-qcom-aoss.c b/drivers/reset/reset-qcom-aoss.c
> new file mode 100644
> index 000000000000..3b0bbb387f7b
> --- /dev/null
> +++ b/drivers/reset/reset-qcom-aoss.c
> @@ -0,0 +1,133 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2018 The Linux Foundation. All rights reserved.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/reset-controller.h>
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +#include <linux/of_device.h>
> +#include <dt-bindings/reset/qcom,sdm845-aoss.h>
> +
> +struct qcom_aoss_reset_map {
> + unsigned int reg;
> +};
> +
> +struct qcom_aoss_desc {
> + const struct qcom_aoss_reset_map *resets;
> + size_t num_resets;
> +};
> +
> +struct qcom_aoss_reset_data {
> + struct reset_controller_dev rcdev;
> + void __iomem *base;
> + const struct qcom_aoss_desc *desc;
> +};
> +
> +static const struct qcom_aoss_reset_map sdm845_aoss_resets[] = {
> + [AOSS_CC_MSS_RESTART] = {0x0},
> + [AOSS_CC_CAMSS_RESTART] = {0x1000},
> + [AOSS_CC_VENUS_RESTART] = {0x2000},
> + [AOSS_CC_GPU_RESTART] = {0x3000},
> + [AOSS_CC_DISPSS_RESTART] = {0x4000},
> + [AOSS_CC_WCSS_RESTART] = {0x10000},
> + [AOSS_CC_LPASS_RESTART] = {0x20000},
> +};
> +
> +static const struct qcom_aoss_desc sdm845_aoss_desc = {
> + .resets = sdm845_aoss_resets,
> + .num_resets = ARRAY_SIZE(sdm845_aoss_resets),
> +};
> +
> +static inline struct qcom_aoss_reset_data *to_qcom_aoss_reset_data(
> + struct reset_controller_dev *rcdev)
> +{
> + return container_of(rcdev, struct qcom_aoss_reset_data, rcdev);
> +}
> +
> +static int qcom_aoss_control_assert(struct reset_controller_dev *rcdev,
> + unsigned long idx)
> +{
> + struct qcom_aoss_reset_data *data = to_qcom_aoss_reset_data(rcdev);
> + const struct qcom_aoss_reset_map *map = &data->desc->resets[idx];
> +
> + writel(1, data->base + map->reg);
> + /* Wait 6 32kHz sleep cycles for reset */
> + usleep_range(200, 210);
> + return 0;
> +}
> +
> +static int qcom_aoss_control_deassert(struct reset_controller_dev *rcdev,
> + unsigned long idx)
> +{
> + struct qcom_aoss_reset_data *data = to_qcom_aoss_reset_data(rcdev);
> + const struct qcom_aoss_reset_map *map = &data->desc->resets[idx];
> +
> + writel(0, data->base + map->reg);
> + /* Wait 6 32kHz sleep cycles for reset */
> + usleep_range(200, 210);
6 32 kHz cycles are about 188 µs (184 µs for 32.768 kHz).
Just out of curiosity, is the minimum increased to 200 µs on purpose, or
to have a nice round number? The maximum seems oddly small, unless it is
essential to wait less than 7 cycles.
The driver looks good to me now. I plan to apply patches 1 and 2 with
Rob's ack.
Is it ok to merge them independently from the remoteproc driver, or is
there a dependency?
regards
Philipp
^ permalink raw reply [relevance 0%]
* Re: [PATCH v4 1/5] dt-bindings: reset: Add AOSS reset bindings for SDM845 SoCs
2018-04-27 10:24 0% ` Philipp Zabel
@ 2018-04-27 10:45 6% ` Sibi S
0 siblings, 0 replies; 200+ results
From: Sibi S @ 2018-04-27 10:45 UTC (permalink / raw)
To: Philipp Zabel, bjorn.andersson, robh+dt
Cc: linux-remoteproc, linux-kernel, devicetree, georgi.djakov,
jassisinghbrar, ohad, mark.rutland, kyan, sricharan, akdwived,
linux-arm-msm, tsoni
Hi Philipp,
Thanks for the review
On 04/27/2018 03:54 PM, Philipp Zabel wrote:
> Hi Sibi,
>
> On Wed, 2018-04-25 at 20:38 +0530, Sibi Sankar wrote:
>> Add SDM845 AOSS (always on subsystem) reset controller binding
>>
>> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
>> ---
>> .../bindings/reset/qcom,aoss-reset.txt | 52 +++++++++++++++++++
>> include/dt-bindings/reset/qcom,sdm845-aoss.h | 17 ++++++
>> 2 files changed, 69 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
>> create mode 100644 include/dt-bindings/reset/qcom,sdm845-aoss.h
>>
>> diff --git a/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
>> new file mode 100644
>> index 000000000000..e5201de9a314
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
>> @@ -0,0 +1,52 @@
>> +Qualcomm AOSS Reset Controller
>> +======================================
>> +
>> +This binding describes a reset-controller found on AOSS (always on subsystem)
>> +for Qualcomm SDM845 SoCs.
>> +
>> +Required properties:
>> +- compatible:
>> + Usage: required
>> + Value type: <string>
>> + Definition: must be:
>> + "qcom,sdm845-aoss-reset"
>> +
>> +- reg:
>> + Usage: required
>> + Value type: <prop-encoded-array>
>> + Definition: must specify the base address and size of the register
>> + space.
>> +
>> +- #reset-cells:
>> + Usage: required
>> + Value type: <uint>
>> + Definition: must be 1; cell entry represents the reset index.
>> +
>> +Example:
>> +
>> +aoss_reset: qcom,reset-controller@b2e0100 {
>
> The node name should be "reset-controller", not "qcom,reset-controller"
>
>> + compatible = "qcom,sdm845-aoss-reset";
>> + reg = <0xc2b0000 0x21000>;
>
> The address here should match the address part of the node name above.
>
sure will change them
> Apart from those two nitpicks, the binding looks good to me.
>
> regards
> Philipp
>
--
Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc, is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [relevance 6%]
* Re: [PATCH v4 2/5] reset: qcom: AOSS (always on subsystem) reset controller
2018-04-27 10:41 0% ` Philipp Zabel
@ 2018-04-27 11:15 6% ` Sibi S
0 siblings, 0 replies; 200+ results
From: Sibi S @ 2018-04-27 11:15 UTC (permalink / raw)
To: Philipp Zabel, bjorn.andersson, robh+dt
Cc: linux-remoteproc, linux-kernel, devicetree, georgi.djakov,
jassisinghbrar, ohad, mark.rutland, kyan, sricharan, akdwived,
linux-arm-msm, tsoni
Hi Philipp,
Thanks for the review.
On 04/27/2018 04:11 PM, Philipp Zabel wrote:
> On Wed, 2018-04-25 at 20:38 +0530, Sibi Sankar wrote:
>> Add reset controller driver for Qualcomm SDM845 SoC to
>> control reset signals provided by AOSS for Modem, Venus
>> ADSP, GPU, Camera, Wireless, Display subsystem
>>
>> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
>> ---
>> drivers/reset/Kconfig | 9 +++
>> drivers/reset/Makefile | 1 +
>> drivers/reset/reset-qcom-aoss.c | 133 ++++++++++++++++++++++++++++++++
>> 3 files changed, 143 insertions(+)
>> create mode 100644 drivers/reset/reset-qcom-aoss.c
>>
>> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
>> index c0b292be1b72..756ad2b27d0f 100644
>> --- a/drivers/reset/Kconfig
>> +++ b/drivers/reset/Kconfig
>> @@ -82,6 +82,15 @@ config RESET_PISTACHIO
>> help
>> This enables the reset driver for ImgTec Pistachio SoCs.
>>
>> +config RESET_QCOM_AOSS
>> + bool "Qcom AOSS Reset Driver"
>> + depends on ARCH_QCOM || COMPILE_TEST
>> + help
>> + This enables the AOSS (always on subsystem) reset driver
>> + for Qualcomm SDM845 SoCs. Say Y if you want to control
>> + reset signals provided by AOSS for Modem, Venus, ADSP,
>> + GPU, Camera, Wireless, Display subsystem. Otherwise, say N.
>> +
>> config RESET_SIMPLE
>> bool "Simple Reset Controller Driver" if COMPILE_TEST
>> default ARCH_SOCFPGA || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED
>> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
>> index c1261dcfe9ad..6881e4d287f0 100644
>> --- a/drivers/reset/Makefile
>> +++ b/drivers/reset/Makefile
>> @@ -14,6 +14,7 @@ obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
>> obj-$(CONFIG_RESET_MESON) += reset-meson.o
>> obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
>> obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o
>> +obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o
>> obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
>> obj-$(CONFIG_RESET_STM32MP157) += reset-stm32mp1.o
>> obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
>> diff --git a/drivers/reset/reset-qcom-aoss.c b/drivers/reset/reset-qcom-aoss.c
>> new file mode 100644
>> index 000000000000..3b0bbb387f7b
>> --- /dev/null
>> +++ b/drivers/reset/reset-qcom-aoss.c
>> @@ -0,0 +1,133 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (C) 2018 The Linux Foundation. All rights reserved.
>> + */
>> +
>> +#include <linux/module.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/reset-controller.h>
>> +#include <linux/delay.h>
>> +#include <linux/io.h>
>> +#include <linux/of_device.h>
>> +#include <dt-bindings/reset/qcom,sdm845-aoss.h>
>> +
>> +struct qcom_aoss_reset_map {
>> + unsigned int reg;
>> +};
>> +
>> +struct qcom_aoss_desc {
>> + const struct qcom_aoss_reset_map *resets;
>> + size_t num_resets;
>> +};
>> +
>> +struct qcom_aoss_reset_data {
>> + struct reset_controller_dev rcdev;
>> + void __iomem *base;
>> + const struct qcom_aoss_desc *desc;
>> +};
>> +
>> +static const struct qcom_aoss_reset_map sdm845_aoss_resets[] = {
>> + [AOSS_CC_MSS_RESTART] = {0x0},
>> + [AOSS_CC_CAMSS_RESTART] = {0x1000},
>> + [AOSS_CC_VENUS_RESTART] = {0x2000},
>> + [AOSS_CC_GPU_RESTART] = {0x3000},
>> + [AOSS_CC_DISPSS_RESTART] = {0x4000},
>> + [AOSS_CC_WCSS_RESTART] = {0x10000},
>> + [AOSS_CC_LPASS_RESTART] = {0x20000},
>> +};
>> +
>> +static const struct qcom_aoss_desc sdm845_aoss_desc = {
>> + .resets = sdm845_aoss_resets,
>> + .num_resets = ARRAY_SIZE(sdm845_aoss_resets),
>> +};
>> +
>> +static inline struct qcom_aoss_reset_data *to_qcom_aoss_reset_data(
>> + struct reset_controller_dev *rcdev)
>> +{
>> + return container_of(rcdev, struct qcom_aoss_reset_data, rcdev);
>> +}
>> +
>> +static int qcom_aoss_control_assert(struct reset_controller_dev *rcdev,
>> + unsigned long idx)
>> +{
>> + struct qcom_aoss_reset_data *data = to_qcom_aoss_reset_data(rcdev);
>> + const struct qcom_aoss_reset_map *map = &data->desc->resets[idx];
>> +
>> + writel(1, data->base + map->reg);
>> + /* Wait 6 32kHz sleep cycles for reset */
>> + usleep_range(200, 210);
>> + return 0;
>> +}
>> +
>> +static int qcom_aoss_control_deassert(struct reset_controller_dev *rcdev,
>> + unsigned long idx)
>> +{
>> + struct qcom_aoss_reset_data *data = to_qcom_aoss_reset_data(rcdev);
>> + const struct qcom_aoss_reset_map *map = &data->desc->resets[idx];
>> +
>> + writel(0, data->base + map->reg);
>> + /* Wait 6 32kHz sleep cycles for reset */
>> + usleep_range(200, 210);
>
> 6 32 kHz cycles are about 188 µs (184 µs for 32.768 kHz).
> Just out of curiosity, is the minimum increased to 200 µs on purpose, or
> to have a nice round number? The maximum seems oddly small, unless it is
> essential to wait less than 7 cycles.
>
anything above 188 µs should be fine 200 µs is just a round number.
no it is not essential to wait less than 7 cycles so I can increase
the max limit to 300 µs.
> The driver looks good to me now. I plan to apply patches 1 and 2 with
> Rob's ack.
> Is it ok to merge them independently from the remoteproc driver, or is
> there a dependency?
>
Yes it should be fine to merge them independently. I can add a dt entry
to the dtsi and separate the 2 patches from the remoteproc patches if
that helps ?
> regards
> Philipp
>
--
Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc, is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [relevance 6%]
* Re: [PATCH v4 3/5] dt-bindings: remoteproc: Add Q6v5 Modem PIL binding for SDM845
2018-04-25 15:08 21% ` [PATCH v4 3/5] dt-bindings: remoteproc: Add Q6v5 Modem PIL binding for SDM845 Sibi Sankar
@ 2018-04-27 14:32 0% ` Rob Herring
0 siblings, 0 replies; 200+ results
From: Rob Herring @ 2018-04-27 14:32 UTC (permalink / raw)
To: Sibi Sankar
Cc: bjorn.andersson, p.zabel, linux-remoteproc, linux-kernel,
devicetree, georgi.djakov, jassisinghbrar, ohad, mark.rutland,
kyan, sricharan, akdwived, linux-arm-msm, tsoni
On Wed, Apr 25, 2018 at 08:38:41PM +0530, Sibi Sankar wrote:
> Add new compatible string for Qualcomm SDM845 SoCs
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
> Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [relevance 0%]
* [PATCH v2] arm64: dts: qcom: Add SDM845 SMEM nodes
@ 2018-04-30 14:44 20% Sibi Sankar
2018-05-01 0:20 0% ` Bjorn Andersson
0 siblings, 1 reply; 200+ results
From: Sibi Sankar @ 2018-04-30 14:44 UTC (permalink / raw)
To: andy.gross, david.brown, robh+dt, bjorn.andersson
Cc: mark.rutland, catalin.marinas, will.deacon, linux-arm-msm,
linux-kernel, devicetree, linux-soc, Sibi Sankar
Add all the necessary dt nodes to support SMEM driver
on SDM845. It also adds the required memory carveouts
so that the kernel does not access memory that is in
use.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
This patch depends on:
https://patchwork.kernel.org/patch/10276419/
https://patchwork.kernel.org/patch/10363361/
arch/arm64/boot/dts/qcom/sdm845.dtsi | 38 ++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 9be763da0664..55e7d7e23b10 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -21,6 +21,27 @@
reg = <0 0x80000000 0 0>;
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ memory@85fc0000 {
+ reg = <0 0x85fc0000 0 0x20000>;
+ no-map;
+ };
+
+ smem_mem: memory@86000000 {
+ reg = <0x0 0x86000000 0x0 0x200000>;
+ no-map;
+ };
+
+ memory@86200000 {
+ reg = <0 0x86200000 0 0x2d00000>;
+ no-map;
+ };
+ };
+
cpus {
#address-cells = <2>;
#size-cells = <0>;
@@ -147,6 +168,18 @@
};
};
+ tcsr_mutex: hwlock {
+ compatible = "qcom,tcsr-mutex";
+ syscon = <&tcsr_mutex_regs 0 0x1000>;
+ #hwlock-cells = <1>;
+ };
+
+ smem {
+ compatible = "qcom,smem";
+ memory-region = <&smem_mem>;
+ hwlocks = <&tcsr_mutex 3>;
+ };
+
psci {
compatible = "arm,psci-1.0";
method = "smc";
@@ -339,6 +372,11 @@
};
};
+ tcsr_mutex_regs: syscon@1f40000 {
+ compatible = "syscon";
+ reg = <0x1f40000 0x40000>;
+ };
+
apss_shared: mailbox@17990000 {
compatible = "qcom,sdm845-apss-shared";
reg = <0x17990000 0x1000>;
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 20%]
* Re: [PATCH v2] arm64: dts: qcom: Add SDM845 SMEM nodes
2018-04-30 14:44 20% [PATCH v2] arm64: dts: qcom: Add SDM845 SMEM nodes Sibi Sankar
@ 2018-05-01 0:20 0% ` Bjorn Andersson
0 siblings, 0 replies; 200+ results
From: Bjorn Andersson @ 2018-05-01 0:20 UTC (permalink / raw)
To: Sibi Sankar
Cc: andy.gross, david.brown, robh+dt, mark.rutland, catalin.marinas,
will.deacon, linux-arm-msm, linux-kernel, devicetree, linux-soc
On Mon 30 Apr 07:44 PDT 2018, Sibi Sankar wrote:
> Add all the necessary dt nodes to support SMEM driver
> on SDM845. It also adds the required memory carveouts
> so that the kernel does not access memory that is in
> use.
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Regards,
Bjorn
> ---
>
> This patch depends on:
> https://patchwork.kernel.org/patch/10276419/
> https://patchwork.kernel.org/patch/10363361/
>
> arch/arm64/boot/dts/qcom/sdm845.dtsi | 38 ++++++++++++++++++++++++++++
> 1 file changed, 38 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> index 9be763da0664..55e7d7e23b10 100644
> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> @@ -21,6 +21,27 @@
> reg = <0 0x80000000 0 0>;
> };
>
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + memory@85fc0000 {
> + reg = <0 0x85fc0000 0 0x20000>;
> + no-map;
> + };
> +
> + smem_mem: memory@86000000 {
> + reg = <0x0 0x86000000 0x0 0x200000>;
> + no-map;
> + };
> +
> + memory@86200000 {
> + reg = <0 0x86200000 0 0x2d00000>;
> + no-map;
> + };
> + };
> +
> cpus {
> #address-cells = <2>;
> #size-cells = <0>;
> @@ -147,6 +168,18 @@
> };
> };
>
> + tcsr_mutex: hwlock {
> + compatible = "qcom,tcsr-mutex";
> + syscon = <&tcsr_mutex_regs 0 0x1000>;
> + #hwlock-cells = <1>;
> + };
> +
> + smem {
> + compatible = "qcom,smem";
> + memory-region = <&smem_mem>;
> + hwlocks = <&tcsr_mutex 3>;
> + };
> +
> psci {
> compatible = "arm,psci-1.0";
> method = "smc";
> @@ -339,6 +372,11 @@
> };
> };
>
> + tcsr_mutex_regs: syscon@1f40000 {
> + compatible = "syscon";
> + reg = <0x1f40000 0x40000>;
> + };
> +
> apss_shared: mailbox@17990000 {
> compatible = "qcom,sdm845-apss-shared";
> reg = <0x17990000 0x1000>;
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
^ permalink raw reply [relevance 0%]
* Re: [PATCH 1/3] dt-bindings: mailbox: Add APSS shared binding for SDM845 SoCs
2018-04-25 14:38 21% [PATCH 1/3] dt-bindings: mailbox: Add APSS shared binding for SDM845 SoCs Sibi Sankar
` (2 preceding siblings ...)
2018-04-25 16:26 0% ` [PATCH 1/3] dt-bindings: mailbox: Add APSS shared binding for SDM845 SoCs Bjorn Andersson
@ 2018-05-01 14:28 0% ` Rob Herring
3 siblings, 0 replies; 200+ results
From: Rob Herring @ 2018-05-01 14:28 UTC (permalink / raw)
To: Sibi Sankar
Cc: andy.gross, mark.rutland, bjorn.andersson, david.brown,
linux-arm-msm, georgi.djakov, devicetree, linux-soc,
linux-kernel, jassisinghbrar, will.deacon, catalin.marinas
On Wed, Apr 25, 2018 at 08:08:01PM +0530, Sibi Sankar wrote:
> Include SDM845 APSS shared to the list of possible bindings
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
> .../devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [relevance 0%]
* [PATCH] remoteproc: Introduce prepare/unprepare ops for rproc coredump
@ 2018-05-12 14:21 15% Sibi Sankar
0 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2018-05-12 14:21 UTC (permalink / raw)
To: bjorn.andersson, ohad
Cc: linux-remoteproc, linux-kernel, linux-arm-msm, Sibi Sankar
In some occasions the remoteproc device might need to
prepare some hardware before the coredump can be performed
and cleanup the state afterwards.
Q6V5 modem requires the mba to be loaded before the
coredump and some cleanup of the resources afterwards.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
This patch depends on:
https://patchwork.kernel.org/patch/10363399/
drivers/remoteproc/qcom_q6v5_pil.c | 64 ++++++++++++++++++++----
drivers/remoteproc/remoteproc_core.c | 5 ++
drivers/remoteproc/remoteproc_internal.h | 16 ++++++
include/linux/remoteproc.h | 4 ++
4 files changed, 79 insertions(+), 10 deletions(-)
diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
index 1f861b214850..ef643c0aec5f 100644
--- a/drivers/remoteproc/qcom_q6v5_pil.c
+++ b/drivers/remoteproc/qcom_q6v5_pil.c
@@ -160,6 +160,7 @@ struct q6v5 {
struct completion start_done;
struct completion stop_done;
bool running;
+ bool coredump_pending;
phys_addr_t mba_phys;
void *mba_region;
@@ -663,6 +664,7 @@ static int q6v5_mpss_load(struct q6v5 *qproc)
}
mpss_reloc = relocate ? min_addr : qproc->mpss_phys;
+ qproc->mpss_reloc = mpss_reloc;
/* Load firmware segments */
for (i = 0; i < ehdr->e_phnum; i++) {
phdr = &phdrs[i];
@@ -737,7 +739,7 @@ static int q6v5_start(struct rproc *rproc)
qproc->proxy_reg_count);
if (ret) {
dev_err(qproc->dev, "failed to enable proxy supplies\n");
- return ret;
+ goto clear_coredump_pending;
}
ret = q6v5_clk_enable(qproc->dev, qproc->proxy_clks,
@@ -793,6 +795,21 @@ static int q6v5_start(struct rproc *rproc)
goto halt_axi_ports;
}
+ if (qproc->coredump_pending) {
+ dev_info(qproc->dev, "MBA booted, skipping mpss for coredump\n");
+ qproc->coredump_pending = false;
+ enable_irq(qproc->handover_interrupt);
+ enable_irq(qproc->wdog_interrupt);
+ enable_irq(qproc->fatal_interrupt);
+ xfermemop_ret = q6v5_xfer_mem_ownership(qproc,
+ &qproc->mba_perm, false,
+ qproc->mba_phys,
+ qproc->mba_size);
+ if (xfermemop_ret)
+ dev_err(qproc->dev, "Failed to reclaim mba buffer\n");
+ return 0;
+ }
+
dev_info(qproc->dev, "MBA booted, loading mpss\n");
ret = q6v5_mpss_load(qproc);
@@ -859,6 +876,8 @@ static int q6v5_start(struct rproc *rproc)
disable_proxy_reg:
q6v5_regulator_disable(qproc, qproc->proxy_regs,
qproc->proxy_reg_count);
+clear_coredump_pending:
+ qproc->coredump_pending = false;
return ret;
}
@@ -869,17 +888,19 @@ static int q6v5_stop(struct rproc *rproc)
int ret;
u32 val;
- qproc->running = false;
-
- qcom_smem_state_update_bits(qproc->state,
- BIT(qproc->stop_bit), BIT(qproc->stop_bit));
+ if (qproc->running) {
+ qproc->running = false;
+ qcom_smem_state_update_bits(qproc->state,
+ BIT(qproc->stop_bit), BIT(qproc->stop_bit));
- ret = wait_for_completion_timeout(&qproc->stop_done,
- msecs_to_jiffies(5000));
- if (ret == 0)
- dev_err(qproc->dev, "timed out on wait\n");
+ ret = wait_for_completion_timeout(&qproc->stop_done,
+ msecs_to_jiffies(5000));
+ if (ret == 0)
+ dev_err(qproc->dev, "timed out on wait\n");
- qcom_smem_state_update_bits(qproc->state, BIT(qproc->stop_bit), 0);
+ qcom_smem_state_update_bits(qproc->state,
+ BIT(qproc->stop_bit), 0);
+ }
q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
@@ -930,10 +951,31 @@ static void *q6v5_da_to_va(struct rproc *rproc, u64 da, int len)
return qproc->mpss_region + offset;
}
+static int qcom_mpss_register_dump_segments(struct rproc *rproc,
+ const struct firmware *fw_unused)
+{
+ const struct firmware *fw;
+ struct q6v5 *qproc = (struct q6v5 *)rproc->priv;
+ int ret;
+
+ ret = request_firmware(&fw, "modem.mdt", qproc->dev);
+ if (ret < 0) {
+ dev_err(qproc->dev, "unable to load modem.mdt\n");
+ return ret;
+ }
+ ret = qcom_register_dump_segments(rproc, fw);
+
+ release_firmware(fw);
+ return ret;
+}
+
static const struct rproc_ops q6v5_ops = {
.start = q6v5_start,
.stop = q6v5_stop,
.da_to_va = q6v5_da_to_va,
+ .parse_fw = qcom_mpss_register_dump_segments,
+ .prepare_coredump = q6v5_start,
+ .unprepare_coredump = q6v5_stop,
.load = q6v5_load,
};
@@ -949,6 +991,7 @@ static irqreturn_t q6v5_wdog_interrupt(int irq, void *dev)
return IRQ_HANDLED;
}
+ qproc->coredump_pending = true;
msg = qcom_smem_get(QCOM_SMEM_HOST_ANY, MPSS_CRASH_REASON_SMEM, &len);
if (!IS_ERR(msg) && len > 0 && msg[0])
dev_err(qproc->dev, "watchdog received: %s\n", msg);
@@ -966,6 +1009,7 @@ static irqreturn_t q6v5_fatal_interrupt(int irq, void *dev)
size_t len;
char *msg;
+ qproc->coredump_pending = true;
msg = qcom_smem_get(QCOM_SMEM_HOST_ANY, MPSS_CRASH_REASON_SMEM, &len);
if (!IS_ERR(msg) && len > 0 && msg[0])
dev_err(qproc->dev, "fatal error received: %s\n", msg);
diff --git a/drivers/remoteproc/remoteproc_core.c b/drivers/remoteproc/remoteproc_core.c
index a9609d971f7f..8c254d9b5c67 100644
--- a/drivers/remoteproc/remoteproc_core.c
+++ b/drivers/remoteproc/remoteproc_core.c
@@ -1083,6 +1083,9 @@ static void rproc_coredump(struct rproc *rproc)
if (list_empty(&rproc->dump_segments))
return;
+ if (rproc_prepare_coredump(rproc))
+ return;
+
data_size = sizeof(*ehdr);
list_for_each_entry(segment, &rproc->dump_segments, node) {
data_size += sizeof(*phdr) + segment->size;
@@ -1139,6 +1142,8 @@ static void rproc_coredump(struct rproc *rproc)
}
dev_coredumpv(&rproc->dev, data, data_size, GFP_KERNEL);
+
+ rproc_unprepare_coredump(rproc);
}
/**
diff --git a/drivers/remoteproc/remoteproc_internal.h b/drivers/remoteproc/remoteproc_internal.h
index 7570beb035b5..22a1b276e110 100644
--- a/drivers/remoteproc/remoteproc_internal.h
+++ b/drivers/remoteproc/remoteproc_internal.h
@@ -96,6 +96,22 @@ static inline int rproc_parse_fw(struct rproc *rproc, const struct firmware *fw)
return 0;
}
+static inline int rproc_prepare_coredump(struct rproc *rproc)
+{
+ if (rproc->ops->prepare_coredump)
+ return rproc->ops->prepare_coredump(rproc);
+
+ return 0;
+}
+
+static inline int rproc_unprepare_coredump(struct rproc *rproc)
+{
+ if (rproc->ops->unprepare_coredump)
+ return rproc->ops->unprepare_coredump(rproc);
+
+ return 0;
+}
+
static inline
struct resource_table *rproc_find_loaded_rsc_table(struct rproc *rproc,
const struct firmware *fw)
diff --git a/include/linux/remoteproc.h b/include/linux/remoteproc.h
index dfdaede9139e..010819e01279 100644
--- a/include/linux/remoteproc.h
+++ b/include/linux/remoteproc.h
@@ -333,6 +333,8 @@ struct firmware;
* @kick: kick a virtqueue (virtqueue id given as a parameter)
* @da_to_va: optional platform hook to perform address translations
* @load_rsc_table: load resource table from firmware image
+ * @prepare_coredump: prepare function, called before coredump
+ * @unprepare_coredump: unprepare function, called post coredump
* @find_loaded_rsc_table: find the loaded resouce table
* @load: load firmeware to memory, where the remote processor
* expects to find it
@@ -345,6 +347,8 @@ struct rproc_ops {
void (*kick)(struct rproc *rproc, int vqid);
void * (*da_to_va)(struct rproc *rproc, u64 da, int len);
int (*parse_fw)(struct rproc *rproc, const struct firmware *fw);
+ int (*prepare_coredump)(struct rproc *rproc);
+ int (*unprepare_coredump)(struct rproc *rproc);
struct resource_table *(*find_loaded_rsc_table)(
struct rproc *rproc, const struct firmware *fw);
int (*load)(struct rproc *rproc, const struct firmware *fw);
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 15%]
* Re: [PATCH] remoteproc: Proxy unvote clk/regs in handover context
2018-04-25 14:50 17% [PATCH] remoteproc: Proxy unvote clk/regs in handover context Sibi Sankar
@ 2018-05-18 19:58 0% ` Bjorn Andersson
2018-05-21 16:49 6% ` Sibi S
0 siblings, 1 reply; 200+ results
From: Bjorn Andersson @ 2018-05-18 19:58 UTC (permalink / raw)
To: Sibi Sankar; +Cc: ohad, clew, linux-remoteproc, linux-kernel, linux-arm-msm
On Wed 25 Apr 07:50 PDT 2018, Sibi Sankar wrote:
> Introduce interrupt handler for smp2p ready interrupt and
> handle start completion. Remove the proxy votes for clocks
> and regulators in the handover interrupt context. Disable
> wdog and fatal interrupts on remoteproc device stop and
> re-enable them on remoteproc device start.
Can't the enable/disable dance be split out into a separate commit?
Making the introduction of them cleaner in the git history?
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
> drivers/remoteproc/qcom_q6v5_pil.c | 71 +++++++++++++++++++++++++-----
> 1 file changed, 60 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
> index 296eb3f8b551..7e2d04d4f2f0 100644
> --- a/drivers/remoteproc/qcom_q6v5_pil.c
> +++ b/drivers/remoteproc/qcom_q6v5_pil.c
> @@ -143,6 +143,10 @@ struct q6v5 {
> struct qcom_smem_state *state;
> unsigned stop_bit;
>
> + unsigned int handover_interrupt;
> + unsigned int wdog_interrupt;
> + unsigned int fatal_interrupt;
Make these "int", and write "irq" instead of "interrupt".
> +
> struct clk *active_clks[8];
> struct clk *proxy_clks[4];
> int active_clk_count;
> @@ -170,6 +174,7 @@ struct q6v5 {
> struct qcom_rproc_ssr ssr_subdev;
> struct qcom_sysmon *sysmon;
> bool need_mem_protection;
> + bool unvoted_flag;
> int mpss_perm;
> int mba_perm;
> int version;
> @@ -727,6 +732,7 @@ static int q6v5_start(struct rproc *rproc)
> int xfermemop_ret;
> int ret;
>
> + qproc->unvoted_flag = false;
> ret = q6v5_regulator_enable(qproc, qproc->proxy_regs,
> qproc->proxy_reg_count);
> if (ret) {
> @@ -793,9 +799,16 @@ static int q6v5_start(struct rproc *rproc)
> if (ret)
> goto reclaim_mpss;
>
> + enable_irq(qproc->handover_interrupt);
> + enable_irq(qproc->wdog_interrupt);
> + enable_irq(qproc->fatal_interrupt);
> +
> ret = wait_for_completion_timeout(&qproc->start_done,
> msecs_to_jiffies(5000));
> if (ret == 0) {
> + disable_irq(qproc->handover_interrupt);
> + disable_irq(qproc->wdog_interrupt);
> + disable_irq(qproc->fatal_interrupt);
> dev_err(qproc->dev, "start timed out\n");
> ret = -ETIMEDOUT;
> goto reclaim_mpss;
> @@ -809,11 +822,6 @@ static int q6v5_start(struct rproc *rproc)
> "Failed to reclaim mba buffer system may become unstable\n");
> qproc->running = true;
>
> - q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
> - qproc->proxy_clk_count);
> - q6v5_regulator_disable(qproc, qproc->proxy_regs,
> - qproc->proxy_reg_count);
> -
> return 0;
>
> reclaim_mpss:
> @@ -892,6 +900,16 @@ static int q6v5_stop(struct rproc *rproc)
> WARN_ON(ret);
>
> reset_control_assert(qproc->mss_restart);
> + disable_irq(qproc->handover_interrupt);
> + if (!qproc->unvoted_flag) {
> + q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
> + qproc->proxy_clk_count);
> + q6v5_regulator_disable(qproc, qproc->proxy_regs,
> + qproc->proxy_reg_count);
> + }
Perhaps break this out into a separate function and call it from the two
places?
> + disable_irq(qproc->wdog_interrupt);
> + disable_irq(qproc->fatal_interrupt);
Any particular reason why you didn't group the disable_irq() calls
together? Would look prettier than spreading them on each side of the
resource disable.
> +
> q6v5_clk_disable(qproc->dev, qproc->active_clks,
> qproc->active_clk_count);
> q6v5_regulator_disable(qproc, qproc->active_regs,
[..]
> @@ -1184,19 +1221,31 @@ static int q6v5_probe(struct platform_device *pdev)
>
> qproc->version = desc->version;
> qproc->need_mem_protection = desc->need_mem_protection;
> - ret = q6v5_request_irq(qproc, pdev, "wdog", q6v5_wdog_interrupt);
> + ret = q6v5_request_irq(qproc, pdev, "wdog", q6v5_wdog_interrupt,
> + &qproc->wdog_interrupt);
I think it's time to inline this function instead. You can omit the
first error handling and rely on request_irq to fail if you pass it an
invalid irq number.
> + if (ret < 0)
> + goto free_rproc;
> + disable_irq(qproc->wdog_interrupt);
I presume this is to balance the IRQ enable/disable later?
> +
Regards,
Bjorn
^ permalink raw reply [relevance 0%]
* Re: [PATCH v4 4/5] remoteproc: qcom: Add support for mss remoteproc on SDM845
2018-04-25 15:08 18% ` [PATCH v4 4/5] remoteproc: qcom: Add support for mss remoteproc on SDM845 Sibi Sankar
@ 2018-05-18 21:31 0% ` Bjorn Andersson
2018-05-21 16:51 6% ` Sibi S
0 siblings, 1 reply; 200+ results
From: Bjorn Andersson @ 2018-05-18 21:31 UTC (permalink / raw)
To: Sibi Sankar
Cc: p.zabel, robh+dt, linux-remoteproc, linux-kernel, devicetree,
georgi.djakov, jassisinghbrar, ohad, mark.rutland, kyan,
sricharan, akdwived, linux-arm-msm, tsoni
On Wed 25 Apr 08:08 PDT 2018, Sibi Sankar wrote:
> From SDM845, the Q6SS reset sequence on software side has been
> simplified with the introduction of boot FSM which assists in
> bringing the Q6 out of reset
>
> Add GLINK subdevice to allow definition of GLINK edge as a
> child of modem-pil
>
Please split this in two patches; one adding sdm845 and one adding the
glink subdev. You can squash in the addition of the compatible in the dt
binding into the sdm845 code patch, you wish as well.
Apart from that this looks good!
Regards,
Bjorn
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
> drivers/remoteproc/qcom_q6v5_pil.c | 65 +++++++++++++++++++++++++++++-
> 1 file changed, 64 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
> index 7e2d04d4f2f0..4d9504e8bf8e 100644
> --- a/drivers/remoteproc/qcom_q6v5_pil.c
> +++ b/drivers/remoteproc/qcom_q6v5_pil.c
> @@ -57,6 +57,8 @@
> #define RMB_PMI_META_DATA_REG 0x10
> #define RMB_PMI_CODE_START_REG 0x14
> #define RMB_PMI_CODE_LENGTH_REG 0x18
> +#define RMB_MBA_MSS_STATUS 0x40
> +#define RMB_MBA_ALT_RESET 0x44
>
> #define RMB_CMD_META_DATA_READY 0x1
> #define RMB_CMD_LOAD_READY 0x2
> @@ -104,6 +106,13 @@
> #define QDSP6SS_XO_CBCR 0x0038
> #define QDSP6SS_ACC_OVERRIDE_VAL 0x20
>
> +/* QDSP6v65 parameters */
> +#define QDSP6SS_SLEEP 0x3C
> +#define QDSP6SS_BOOT_CORE_START 0x400
> +#define QDSP6SS_BOOT_CMD 0x404
> +#define SLEEP_CHECK_MAX_LOOPS 200
> +#define BOOT_FSM_TIMEOUT 10000
> +
> struct reg_info {
> struct regulator *reg;
> int uV;
> @@ -170,6 +179,7 @@ struct q6v5 {
> void *mpss_region;
> size_t mpss_size;
>
> + struct qcom_rproc_glink glink_subdev;
> struct qcom_rproc_subdev smd_subdev;
> struct qcom_rproc_ssr ssr_subdev;
> struct qcom_sysmon *sysmon;
> @@ -184,6 +194,7 @@ enum {
> MSS_MSM8916,
> MSS_MSM8974,
> MSS_MSM8996,
> + MSS_SDM845,
> };
>
> static int q6v5_regulator_init(struct device *dev, struct reg_info *regs,
> @@ -390,8 +401,35 @@ static int q6v5proc_reset(struct q6v5 *qproc)
> int ret;
> int i;
>
> + if (qproc->version == MSS_SDM845) {
>
> - if (qproc->version == MSS_MSM8996) {
> + val = readl(qproc->reg_base + QDSP6SS_SLEEP);
> + val |= 0x1;
> + writel(val, qproc->reg_base + QDSP6SS_SLEEP);
> +
> + ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_SLEEP,
> + val, !(val & BIT(31)), 1,
> + SLEEP_CHECK_MAX_LOOPS);
> + if (ret) {
> + dev_err(qproc->dev, "QDSP6SS Sleep clock timed out\n");
> + return -ETIMEDOUT;
> + }
> +
> + /* De-assert QDSP6 stop core */
> + writel(1, qproc->reg_base + QDSP6SS_BOOT_CORE_START);
> + /* Trigger boot FSM */
> + writel(1, qproc->reg_base + QDSP6SS_BOOT_CMD);
> +
> + ret = readl_poll_timeout(qproc->rmb_base + RMB_MBA_MSS_STATUS,
> + val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT);
> + if (ret) {
> + dev_err(qproc->dev, "Boot FSM failed to complete.\n");
> + return ret;
> + }
> +
> + goto pbl_wait;
> +
> + } else if (qproc->version == MSS_MSM8996) {
> /* Override the ACC value if required */
> writel(QDSP6SS_ACC_OVERRIDE_VAL,
> qproc->reg_base + QDSP6SS_STRAP_ACC);
> @@ -499,6 +537,7 @@ static int q6v5proc_reset(struct q6v5 *qproc)
> val &= ~Q6SS_STOP_CORE;
> writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
>
> +pbl_wait:
> /* Wait for PBL status */
> ret = q6v5_rmb_pbl_wait(qproc, 1000);
> if (ret == -ETIMEDOUT) {
> @@ -1256,6 +1295,7 @@ static int q6v5_probe(struct platform_device *pdev)
> }
> qproc->mpss_perm = BIT(QCOM_SCM_VMID_HLOS);
> qproc->mba_perm = BIT(QCOM_SCM_VMID_HLOS);
> + qcom_add_glink_subdev(rproc, &qproc->glink_subdev);
> qcom_add_smd_subdev(rproc, &qproc->smd_subdev);
> qcom_add_ssr_subdev(rproc, &qproc->ssr_subdev, "mpss");
> qproc->sysmon = qcom_add_sysmon_subdev(rproc, "modem", 0x12);
> @@ -1279,6 +1319,7 @@ static int q6v5_remove(struct platform_device *pdev)
> rproc_del(qproc->rproc);
>
> qcom_remove_sysmon_subdev(qproc->sysmon);
> + qcom_remove_glink_subdev(qproc->rproc, &qproc->glink_subdev);
> qcom_remove_smd_subdev(qproc->rproc, &qproc->smd_subdev);
> qcom_remove_ssr_subdev(qproc->rproc, &qproc->ssr_subdev);
> rproc_free(qproc->rproc);
> @@ -1286,6 +1327,27 @@ static int q6v5_remove(struct platform_device *pdev)
> return 0;
> }
>
> +static const struct rproc_hexagon_res sdm845_mss = {
> + .hexagon_mba_image = "mba.mbn",
> + .proxy_clk_names = (char*[]){
> + "xo",
> + "axis2",
> + "prng",
> + NULL
> + },
> + .active_clk_names = (char*[]){
> + "iface",
> + "bus",
> + "mem",
> + "gpll0_mss",
> + "snoc_axi",
> + "mnoc_axi",
> + NULL
> + },
> + .need_mem_protection = true,
> + .version = MSS_SDM845,
> +};
> +
> static const struct rproc_hexagon_res msm8996_mss = {
> .hexagon_mba_image = "mba.mbn",
> .proxy_clk_names = (char*[]){
> @@ -1379,6 +1441,7 @@ static const struct of_device_id q6v5_of_match[] = {
> { .compatible = "qcom,msm8916-mss-pil", .data = &msm8916_mss},
> { .compatible = "qcom,msm8974-mss-pil", .data = &msm8974_mss},
> { .compatible = "qcom,msm8996-mss-pil", .data = &msm8996_mss},
> + { .compatible = "qcom,sdm845-mss-pil", .data = &sdm845_mss},
> { },
> };
> MODULE_DEVICE_TABLE(of, q6v5_of_match);
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
^ permalink raw reply [relevance 0%]
* Re: [PATCH v4 5/5] remoteproc: qcom: Always assert and deassert reset signals in SDM845
2018-04-25 15:08 16% ` [PATCH v4 5/5] remoteproc: qcom: Always assert and deassert reset signals in SDM845 Sibi Sankar
@ 2018-05-18 21:47 0% ` Bjorn Andersson
2018-05-21 16:57 6% ` Sibi S
0 siblings, 1 reply; 200+ results
From: Bjorn Andersson @ 2018-05-18 21:47 UTC (permalink / raw)
To: Sibi Sankar
Cc: p.zabel, robh+dt, linux-remoteproc, linux-kernel, devicetree,
georgi.djakov, jassisinghbrar, ohad, mark.rutland, kyan,
sricharan, akdwived, linux-arm-msm, tsoni
On Wed 25 Apr 08:08 PDT 2018, Sibi Sankar wrote:
> SDM845 brings a new reset signal ALT_RESET which is a part of the MSS
> subsystem hence requires some of the active clks to be enabled before
> assert/deassert
>
> Reset the modem if the BOOT FSM does timeout
>
> Reset assert/deassert sequence vary across SoCs adding reset, adding
> start/stop helper functions to handle SoC specific reset sequences
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
> drivers/remoteproc/qcom_q6v5_pil.c | 81 ++++++++++++++++++++++++++++--
> 1 file changed, 76 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
[..]
> @@ -349,6 +356,32 @@ static int q6v5_load(struct rproc *rproc, const struct firmware *fw)
> return 0;
> }
>
> +static int q6v5_reset_assert(struct q6v5 *qproc)
> +{
> + return reset_control_assert(qproc->mss_restart);
> +}
> +
> +static int q6v5_reset_deassert(struct q6v5 *qproc)
> +{
> + return reset_control_deassert(qproc->mss_restart);
> +}
> +
> +static int q6v5_alt_reset_assert(struct q6v5 *qproc)
> +{
> + return reset_control_reset(qproc->mss_restart);
> +}
> +
> +static int q6v5_alt_reset_deassert(struct q6v5 *qproc)
> +{
> + /* Ensure alt reset is written before restart reg */
> + writel(1, qproc->rmb_base + RMB_MBA_ALT_RESET);
> +
> + reset_control_reset(qproc->mss_restart);
> +
> + writel(0, qproc->rmb_base + RMB_MBA_ALT_RESET);
> + return 0;
> +}
> +
Rather than having these four functions and scattering jumps to some
function pointer in the code I think it will be shorter and cleaner to
just have the q6v5_reset_{asert,deassert}() functions and in there check
if has_alt_reset and take appropriate action.
> static int q6v5_rmb_pbl_wait(struct q6v5 *qproc, int ms)
> {
> unsigned long timeout;
> @@ -424,6 +457,8 @@ static int q6v5proc_reset(struct q6v5 *qproc)
> val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT);
> if (ret) {
> dev_err(qproc->dev, "Boot FSM failed to complete.\n");
> + /* Reset the modem so that boot FSM is in reset state */
> + qproc->reset_deassert(qproc);
A thing like this typically should go into it's own patch, to keep a
clear record of why it was changed, but as this is simply amending the
previous patch it indicates that that one wasn't complete.
So if you reorder the two patches you can just put this directly into
the sdm845 patch, making it "complete".
(This also means that I want to merge the handover vs ready interrupt
patch before that one, so please include it in the next revision of the
series).
> return ret;
> }
>
> @@ -792,12 +827,20 @@ static int q6v5_start(struct rproc *rproc)
> dev_err(qproc->dev, "failed to enable supplies\n");
> goto disable_proxy_clk;
> }
> - ret = reset_control_deassert(qproc->mss_restart);
> +
> + ret = q6v5_clk_enable(qproc->dev, qproc->reset_clks,
> + qproc->reset_clk_count);
Remind me, why can't you always enable the active clock before
deasserting reset? That way we wouldn't have to split out the iface
clock handling to be just slightly longer than the active clocks.
> if (ret) {
> - dev_err(qproc->dev, "failed to deassert mss restart\n");
> + dev_err(qproc->dev, "failed to enable reset clocks\n");
> goto disable_vdd;
> }
>
> + ret = qproc->reset_deassert(qproc);
> + if (ret) {
> + dev_err(qproc->dev, "failed to deassert mss restart\n");
> + goto disable_reset_clks;
> + }
> +
[..]
> @@ -1335,8 +1399,11 @@ static const struct rproc_hexagon_res sdm845_mss = {
> "prng",
> NULL
> },
> - .active_clk_names = (char*[]){
> + .reset_clk_names = (char*[]){
> "iface",
> + NULL
> + },
> + .active_clk_names = (char*[]){
Again, if you reorder your patches to first add the support for
alt_reset and then introduce sdm845 you don't need to modify the
previous patch directly to make it work.
> "bus",
> "mem",
> "gpll0_mss",
Regards,
Bjorn
^ permalink raw reply [relevance 0%]
* Re: [PATCH] remoteproc: Proxy unvote clk/regs in handover context
2018-05-18 19:58 0% ` Bjorn Andersson
@ 2018-05-21 16:49 6% ` Sibi S
0 siblings, 0 replies; 200+ results
From: Sibi S @ 2018-05-21 16:49 UTC (permalink / raw)
To: Bjorn Andersson; +Cc: ohad, clew, linux-remoteproc, linux-kernel, linux-arm-msm
Hi Bjorn,
Thanks for the review. Will make all the suggested changes.
On 05/19/2018 01:28 AM, Bjorn Andersson wrote:
> On Wed 25 Apr 07:50 PDT 2018, Sibi Sankar wrote:
>
>> Introduce interrupt handler for smp2p ready interrupt and
>> handle start completion. Remove the proxy votes for clocks
>> and regulators in the handover interrupt context. Disable
>> wdog and fatal interrupts on remoteproc device stop and
>> re-enable them on remoteproc device start.
>
> Can't the enable/disable dance be split out into a separate commit?
> Making the introduction of them cleaner in the git history?
>
will split it into separate commits
>>
>> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
>> ---
>> drivers/remoteproc/qcom_q6v5_pil.c | 71 +++++++++++++++++++++++++-----
>> 1 file changed, 60 insertions(+), 11 deletions(-)
>>
>> diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
>> index 296eb3f8b551..7e2d04d4f2f0 100644
>> --- a/drivers/remoteproc/qcom_q6v5_pil.c
>> +++ b/drivers/remoteproc/qcom_q6v5_pil.c
>> @@ -143,6 +143,10 @@ struct q6v5 {
>> struct qcom_smem_state *state;
>> unsigned stop_bit;
>>
>> + unsigned int handover_interrupt;
>> + unsigned int wdog_interrupt;
>> + unsigned int fatal_interrupt;
>
> Make these "int", and write "irq" instead of "interrupt".
>
ok
>> +
>> struct clk *active_clks[8];
>> struct clk *proxy_clks[4];
>> int active_clk_count;
>> @@ -170,6 +174,7 @@ struct q6v5 {
>> struct qcom_rproc_ssr ssr_subdev;
>> struct qcom_sysmon *sysmon;
>> bool need_mem_protection;
>> + bool unvoted_flag;
>> int mpss_perm;
>> int mba_perm;
>> int version;
>> @@ -727,6 +732,7 @@ static int q6v5_start(struct rproc *rproc)
>> int xfermemop_ret;
>> int ret;
>>
>> + qproc->unvoted_flag = false;
>> ret = q6v5_regulator_enable(qproc, qproc->proxy_regs,
>> qproc->proxy_reg_count);
>> if (ret) {
>> @@ -793,9 +799,16 @@ static int q6v5_start(struct rproc *rproc)
>> if (ret)
>> goto reclaim_mpss;
>>
>> + enable_irq(qproc->handover_interrupt);
>> + enable_irq(qproc->wdog_interrupt);
>> + enable_irq(qproc->fatal_interrupt);
>> +
>> ret = wait_for_completion_timeout(&qproc->start_done,
>> msecs_to_jiffies(5000));
>> if (ret == 0) {
>> + disable_irq(qproc->handover_interrupt);
>> + disable_irq(qproc->wdog_interrupt);
>> + disable_irq(qproc->fatal_interrupt);
>> dev_err(qproc->dev, "start timed out\n");
>> ret = -ETIMEDOUT;
>> goto reclaim_mpss;
>> @@ -809,11 +822,6 @@ static int q6v5_start(struct rproc *rproc)
>> "Failed to reclaim mba buffer system may become unstable\n");
>> qproc->running = true;
>>
>> - q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
>> - qproc->proxy_clk_count);
>> - q6v5_regulator_disable(qproc, qproc->proxy_regs,
>> - qproc->proxy_reg_count);
>> -
>> return 0;
>>
>> reclaim_mpss:
>> @@ -892,6 +900,16 @@ static int q6v5_stop(struct rproc *rproc)
>> WARN_ON(ret);
>>
>> reset_control_assert(qproc->mss_restart);
>> + disable_irq(qproc->handover_interrupt);
>> + if (!qproc->unvoted_flag) {
>> + q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
>> + qproc->proxy_clk_count);
>> + q6v5_regulator_disable(qproc, qproc->proxy_regs,
>> + qproc->proxy_reg_count);
>> + }
>
> Perhaps break this out into a separate function and call it from the two
> places?
Will create two separate functions for enable/disable
>
>> + disable_irq(qproc->wdog_interrupt);
>> + disable_irq(qproc->fatal_interrupt);
>
> Any particular reason why you didn't group the disable_irq() calls
> together? Would look prettier than spreading them on each side of the
> resource disable.
Nope they can be grouped together.
>
>> +
>> q6v5_clk_disable(qproc->dev, qproc->active_clks,
>> qproc->active_clk_count);
>> q6v5_regulator_disable(qproc, qproc->active_regs,
> [..]
>> @@ -1184,19 +1221,31 @@ static int q6v5_probe(struct platform_device *pdev)
>>
>> qproc->version = desc->version;
>> qproc->need_mem_protection = desc->need_mem_protection;
>> - ret = q6v5_request_irq(qproc, pdev, "wdog", q6v5_wdog_interrupt);
>> + ret = q6v5_request_irq(qproc, pdev, "wdog", q6v5_wdog_interrupt,
>> + &qproc->wdog_interrupt);
>
> I think it's time to inline this function instead. You can omit the
> first error handling and rely on request_irq to fail if you pass it an
> invalid irq number.
I'll inline the function.
>
>> + if (ret < 0)
>> + goto free_rproc;
>> + disable_irq(qproc->wdog_interrupt);
>
> I presume this is to balance the IRQ enable/disable later?
>
yes just to keep things symmetric.
>> +
>
> Regards,
> Bjorn
>
--
Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc, is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [relevance 6%]
* Re: [PATCH v4 4/5] remoteproc: qcom: Add support for mss remoteproc on SDM845
2018-05-18 21:31 0% ` Bjorn Andersson
@ 2018-05-21 16:51 6% ` Sibi S
0 siblings, 0 replies; 200+ results
From: Sibi S @ 2018-05-21 16:51 UTC (permalink / raw)
To: Bjorn Andersson
Cc: p.zabel, robh+dt, linux-remoteproc, linux-kernel, devicetree,
georgi.djakov, jassisinghbrar, ohad, mark.rutland, kyan,
sricharan, akdwived, linux-arm-msm, tsoni
Hi Bjorn,
Thanks for the review.
On 05/19/2018 03:01 AM, Bjorn Andersson wrote:
> On Wed 25 Apr 08:08 PDT 2018, Sibi Sankar wrote:
>
>> From SDM845, the Q6SS reset sequence on software side has been
>> simplified with the introduction of boot FSM which assists in
>> bringing the Q6 out of reset
>>
>> Add GLINK subdevice to allow definition of GLINK edge as a
>> child of modem-pil
>>
>
> Please split this in two patches; one adding sdm845 and one adding the
> glink subdev. You can squash in the addition of the compatible in the dt
> binding into the sdm845 code patch, you wish as well.
>
Will split it into two commits
Will still keep the dt-binding as a separate patch
> Apart from that this looks good!
>
> Regards,
> Bjorn
>
>> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
>> ---
>> drivers/remoteproc/qcom_q6v5_pil.c | 65 +++++++++++++++++++++++++++++-
>> 1 file changed, 64 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
>> index 7e2d04d4f2f0..4d9504e8bf8e 100644
>> --- a/drivers/remoteproc/qcom_q6v5_pil.c
>> +++ b/drivers/remoteproc/qcom_q6v5_pil.c
>> @@ -57,6 +57,8 @@
>> #define RMB_PMI_META_DATA_REG 0x10
>> #define RMB_PMI_CODE_START_REG 0x14
>> #define RMB_PMI_CODE_LENGTH_REG 0x18
>> +#define RMB_MBA_MSS_STATUS 0x40
>> +#define RMB_MBA_ALT_RESET 0x44
>>
>> #define RMB_CMD_META_DATA_READY 0x1
>> #define RMB_CMD_LOAD_READY 0x2
>> @@ -104,6 +106,13 @@
>> #define QDSP6SS_XO_CBCR 0x0038
>> #define QDSP6SS_ACC_OVERRIDE_VAL 0x20
>>
>> +/* QDSP6v65 parameters */
>> +#define QDSP6SS_SLEEP 0x3C
>> +#define QDSP6SS_BOOT_CORE_START 0x400
>> +#define QDSP6SS_BOOT_CMD 0x404
>> +#define SLEEP_CHECK_MAX_LOOPS 200
>> +#define BOOT_FSM_TIMEOUT 10000
>> +
>> struct reg_info {
>> struct regulator *reg;
>> int uV;
>> @@ -170,6 +179,7 @@ struct q6v5 {
>> void *mpss_region;
>> size_t mpss_size;
>>
>> + struct qcom_rproc_glink glink_subdev;
>> struct qcom_rproc_subdev smd_subdev;
>> struct qcom_rproc_ssr ssr_subdev;
>> struct qcom_sysmon *sysmon;
>> @@ -184,6 +194,7 @@ enum {
>> MSS_MSM8916,
>> MSS_MSM8974,
>> MSS_MSM8996,
>> + MSS_SDM845,
>> };
>>
>> static int q6v5_regulator_init(struct device *dev, struct reg_info *regs,
>> @@ -390,8 +401,35 @@ static int q6v5proc_reset(struct q6v5 *qproc)
>> int ret;
>> int i;
>>
>> + if (qproc->version == MSS_SDM845) {
>>
>> - if (qproc->version == MSS_MSM8996) {
>> + val = readl(qproc->reg_base + QDSP6SS_SLEEP);
>> + val |= 0x1;
>> + writel(val, qproc->reg_base + QDSP6SS_SLEEP);
>> +
>> + ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_SLEEP,
>> + val, !(val & BIT(31)), 1,
>> + SLEEP_CHECK_MAX_LOOPS);
>> + if (ret) {
>> + dev_err(qproc->dev, "QDSP6SS Sleep clock timed out\n");
>> + return -ETIMEDOUT;
>> + }
>> +
>> + /* De-assert QDSP6 stop core */
>> + writel(1, qproc->reg_base + QDSP6SS_BOOT_CORE_START);
>> + /* Trigger boot FSM */
>> + writel(1, qproc->reg_base + QDSP6SS_BOOT_CMD);
>> +
>> + ret = readl_poll_timeout(qproc->rmb_base + RMB_MBA_MSS_STATUS,
>> + val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT);
>> + if (ret) {
>> + dev_err(qproc->dev, "Boot FSM failed to complete.\n");
>> + return ret;
>> + }
>> +
>> + goto pbl_wait;
>> +
>> + } else if (qproc->version == MSS_MSM8996) {
>> /* Override the ACC value if required */
>> writel(QDSP6SS_ACC_OVERRIDE_VAL,
>> qproc->reg_base + QDSP6SS_STRAP_ACC);
>> @@ -499,6 +537,7 @@ static int q6v5proc_reset(struct q6v5 *qproc)
>> val &= ~Q6SS_STOP_CORE;
>> writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
>>
>> +pbl_wait:
>> /* Wait for PBL status */
>> ret = q6v5_rmb_pbl_wait(qproc, 1000);
>> if (ret == -ETIMEDOUT) {
>> @@ -1256,6 +1295,7 @@ static int q6v5_probe(struct platform_device *pdev)
>> }
>> qproc->mpss_perm = BIT(QCOM_SCM_VMID_HLOS);
>> qproc->mba_perm = BIT(QCOM_SCM_VMID_HLOS);
>> + qcom_add_glink_subdev(rproc, &qproc->glink_subdev);
>> qcom_add_smd_subdev(rproc, &qproc->smd_subdev);
>> qcom_add_ssr_subdev(rproc, &qproc->ssr_subdev, "mpss");
>> qproc->sysmon = qcom_add_sysmon_subdev(rproc, "modem", 0x12);
>> @@ -1279,6 +1319,7 @@ static int q6v5_remove(struct platform_device *pdev)
>> rproc_del(qproc->rproc);
>>
>> qcom_remove_sysmon_subdev(qproc->sysmon);
>> + qcom_remove_glink_subdev(qproc->rproc, &qproc->glink_subdev);
>> qcom_remove_smd_subdev(qproc->rproc, &qproc->smd_subdev);
>> qcom_remove_ssr_subdev(qproc->rproc, &qproc->ssr_subdev);
>> rproc_free(qproc->rproc);
>> @@ -1286,6 +1327,27 @@ static int q6v5_remove(struct platform_device *pdev)
>> return 0;
>> }
>>
>> +static const struct rproc_hexagon_res sdm845_mss = {
>> + .hexagon_mba_image = "mba.mbn",
>> + .proxy_clk_names = (char*[]){
>> + "xo",
>> + "axis2",
>> + "prng",
>> + NULL
>> + },
>> + .active_clk_names = (char*[]){
>> + "iface",
>> + "bus",
>> + "mem",
>> + "gpll0_mss",
>> + "snoc_axi",
>> + "mnoc_axi",
>> + NULL
>> + },
>> + .need_mem_protection = true,
>> + .version = MSS_SDM845,
>> +};
>> +
>> static const struct rproc_hexagon_res msm8996_mss = {
>> .hexagon_mba_image = "mba.mbn",
>> .proxy_clk_names = (char*[]){
>> @@ -1379,6 +1441,7 @@ static const struct of_device_id q6v5_of_match[] = {
>> { .compatible = "qcom,msm8916-mss-pil", .data = &msm8916_mss},
>> { .compatible = "qcom,msm8974-mss-pil", .data = &msm8974_mss},
>> { .compatible = "qcom,msm8996-mss-pil", .data = &msm8996_mss},
>> + { .compatible = "qcom,sdm845-mss-pil", .data = &sdm845_mss},
>> { },
>> };
>> MODULE_DEVICE_TABLE(of, q6v5_of_match);
>> --
>> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
>> a Linux Foundation Collaborative Project
>>
>
--
Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc, is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [relevance 6%]
* Re: [PATCH v4 5/5] remoteproc: qcom: Always assert and deassert reset signals in SDM845
2018-05-18 21:47 0% ` Bjorn Andersson
@ 2018-05-21 16:57 6% ` Sibi S
0 siblings, 0 replies; 200+ results
From: Sibi S @ 2018-05-21 16:57 UTC (permalink / raw)
To: Bjorn Andersson
Cc: p.zabel, robh+dt, linux-remoteproc, linux-kernel, devicetree,
georgi.djakov, jassisinghbrar, ohad, mark.rutland, kyan,
sricharan, akdwived, linux-arm-msm, tsoni
Hi Bjorn,
Thanks for the review. Will make all the required changes in v5.
On 05/19/2018 03:17 AM, Bjorn Andersson wrote:
> On Wed 25 Apr 08:08 PDT 2018, Sibi Sankar wrote:
>
>> SDM845 brings a new reset signal ALT_RESET which is a part of the MSS
>> subsystem hence requires some of the active clks to be enabled before
>> assert/deassert
>>
>> Reset the modem if the BOOT FSM does timeout
>>
>> Reset assert/deassert sequence vary across SoCs adding reset, adding
>> start/stop helper functions to handle SoC specific reset sequences
>>
>> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
>> ---
>> drivers/remoteproc/qcom_q6v5_pil.c | 81 ++++++++++++++++++++++++++++--
>> 1 file changed, 76 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
> [..]
>> @@ -349,6 +356,32 @@ static int q6v5_load(struct rproc *rproc, const struct firmware *fw)
>> return 0;
>> }
>>
>> +static int q6v5_reset_assert(struct q6v5 *qproc)
>> +{
>> + return reset_control_assert(qproc->mss_restart);
>> +}
>> +
>> +static int q6v5_reset_deassert(struct q6v5 *qproc)
>> +{
>> + return reset_control_deassert(qproc->mss_restart);
>> +}
>> +
>> +static int q6v5_alt_reset_assert(struct q6v5 *qproc)
>> +{
>> + return reset_control_reset(qproc->mss_restart);
>> +}
>> +
>> +static int q6v5_alt_reset_deassert(struct q6v5 *qproc)
>> +{
>> + /* Ensure alt reset is written before restart reg */
>> + writel(1, qproc->rmb_base + RMB_MBA_ALT_RESET);
>> +
>> + reset_control_reset(qproc->mss_restart);
>> +
>> + writel(0, qproc->rmb_base + RMB_MBA_ALT_RESET);
>> + return 0;
>> +}
>> +
>
> Rather than having these four functions and scattering jumps to some
> function pointer in the code I think it will be shorter and cleaner to
> just have the q6v5_reset_{asert,deassert}() functions and in there check
> if has_alt_reset and take appropriate action.
>
yes this seems simpler
>> static int q6v5_rmb_pbl_wait(struct q6v5 *qproc, int ms)
>> {
>> unsigned long timeout;
>> @@ -424,6 +457,8 @@ static int q6v5proc_reset(struct q6v5 *qproc)
>> val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT);
>> if (ret) {
>> dev_err(qproc->dev, "Boot FSM failed to complete.\n");
>> + /* Reset the modem so that boot FSM is in reset state */
>> + qproc->reset_deassert(qproc);
>
>
> A thing like this typically should go into it's own patch, to keep a
> clear record of why it was changed, but as this is simply amending the
> previous patch it indicates that that one wasn't complete.
>
> So if you reorder the two patches you can just put this directly into
> the sdm845 patch, making it "complete".
>
> (This also means that I want to merge the handover vs ready interrupt
> patch before that one, so please include it in the next revision of the
> series).
>
Will re-order them.
>> return ret;
>> }
>>
>> @@ -792,12 +827,20 @@ static int q6v5_start(struct rproc *rproc)
>> dev_err(qproc->dev, "failed to enable supplies\n");
>> goto disable_proxy_clk;
>> }
>> - ret = reset_control_deassert(qproc->mss_restart);
>> +
>> + ret = q6v5_clk_enable(qproc->dev, qproc->reset_clks,
>> + qproc->reset_clk_count);
>
> Remind me, why can't you always enable the active clock before
> deasserting reset? That way we wouldn't have to split out the iface
> clock handling to be just slightly longer than the active clocks.
>
Have to introduce reset clks for backward compatibility, both msm8916
and msm8996 require the mss_reset to be deasserted before enabling
the active clks.
>> if (ret) {
>> - dev_err(qproc->dev, "failed to deassert mss restart\n");
>> + dev_err(qproc->dev, "failed to enable reset clocks\n");
>> goto disable_vdd;
>> }
>>
>> + ret = qproc->reset_deassert(qproc);
>> + if (ret) {
>> + dev_err(qproc->dev, "failed to deassert mss restart\n");
>> + goto disable_reset_clks;
>> + }
>> +
> [..]
>> @@ -1335,8 +1399,11 @@ static const struct rproc_hexagon_res sdm845_mss = {
>> "prng",
>> NULL
>> },
>> - .active_clk_names = (char*[]){
>> + .reset_clk_names = (char*[]){
>> "iface",
>> + NULL
>> + },
>> + .active_clk_names = (char*[]){
>
> Again, if you reorder your patches to first add the support for
> alt_reset and then introduce sdm845 you don't need to modify the
> previous patch directly to make it work.
>
yeah I'll re-order them
>> "bus",
>> "mem",
>> "gpll0_mss",
>
> Regards,
> Bjorn
>
--
Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc, is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [relevance 6%]
* [PATCH v5 0/8] Add support for remoteproc modem-pil on SDM845 SoCs
@ 2018-05-21 17:27 13% Sibi Sankar
2018-05-21 17:27 19% ` [PATCH v5 1/8] dt-bindings: reset: Add AOSS reset bindings for " Sibi Sankar
` (7 more replies)
0 siblings, 8 replies; 200+ results
From: Sibi Sankar @ 2018-05-21 17:27 UTC (permalink / raw)
To: bjorn.andersson, p.zabel, robh+dt
Cc: linux-remoteproc, linux-kernel, devicetree, sibis, georgi.djakov,
jassisinghbrar, ohad, mark.rutland, kyan, sricharan, akdwived,
linux-arm-msm, tsoni
This patch series add support for remoteproc Q6v5 modem-pil on Qualcomm
SDM845 SoC. The first patch adds AOSS (Always on subsystem) reset driver
to provide for mss reset line. The last couple of patches add the resets
sequence for Q6 on SDM845 and adds helper functions for arbitrary reset
assert/deassert sequences.
V5:
corrected dt-binding and increased usleep_range for aoss reset driver
Include the ready interrupt handling in the patch series
Replaced reset ops with a simpler helper function
Re-ordered and split patches as recommended
Inlined q6v5_request_irq function
V4:
Removed regmap depencencies from aoss reset driver
Separted apss shared mailbox into separate patch
Corrected all nits and replaced with author full name
V3:
Removed syscon dependency for the aoss reset driver
Split dt-bindings and the aoss reset driver into separate patches
Corrected few typos and replaced misconfigured author name
V2:
Addressed reset-qcom-aoss review suggestions and reworked
re-ordering of the active clk and reset sequence in
qcom_q6v5_pil
Sibi Sankar (8):
dt-bindings: reset: Add AOSS reset bindings for SDM845 SoCs
reset: qcom: AOSS (always on subsystem) reset controller
remoteproc: Move proxy unvote to handover irq handler
remoteproc: Synchronize proxy unvote from multiple contexts
dt-bindings: remoteproc: Add Q6v5 Modem PIL binding for SDM845
remoteproc: qcom: Introduce reset assert/deassert helper functions
remoteproc: qcom: Add support for mss remoteproc on SDM845
remoteproc: qcom: Allow defining GLINK edge for mss remoteproc
.../bindings/remoteproc/qcom,q6v5.txt | 1 +
.../bindings/reset/qcom,aoss-reset.txt | 52 +++++
drivers/remoteproc/qcom_q6v5_pil.c | 212 ++++++++++++++++--
drivers/reset/Kconfig | 9 +
drivers/reset/Makefile | 1 +
drivers/reset/reset-qcom-aoss.c | 133 +++++++++++
include/dt-bindings/reset/qcom,sdm845-aoss.h | 17 ++
7 files changed, 404 insertions(+), 21 deletions(-)
create mode 100644 Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
create mode 100644 drivers/reset/reset-qcom-aoss.c
create mode 100644 include/dt-bindings/reset/qcom,sdm845-aoss.h
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [relevance 13%]
* [PATCH v5 1/8] dt-bindings: reset: Add AOSS reset bindings for SDM845 SoCs
2018-05-21 17:27 13% [PATCH v5 0/8] Add support for remoteproc modem-pil on SDM845 SoCs Sibi Sankar
@ 2018-05-21 17:27 19% ` Sibi Sankar
2018-05-22 16:17 0% ` Rob Herring
2018-06-23 0:44 0% ` Bjorn Andersson
2018-05-21 17:27 16% ` [PATCH v5 2/8] reset: qcom: AOSS (always on subsystem) reset controller Sibi Sankar
` (6 subsequent siblings)
7 siblings, 2 replies; 200+ results
From: Sibi Sankar @ 2018-05-21 17:27 UTC (permalink / raw)
To: bjorn.andersson, p.zabel, robh+dt
Cc: linux-remoteproc, linux-kernel, devicetree, sibis, georgi.djakov,
jassisinghbrar, ohad, mark.rutland, kyan, sricharan, akdwived,
linux-arm-msm, tsoni
Add SDM845 AOSS (always on subsystem) reset controller binding
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
.../bindings/reset/qcom,aoss-reset.txt | 52 +++++++++++++++++++
include/dt-bindings/reset/qcom,sdm845-aoss.h | 17 ++++++
2 files changed, 69 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
create mode 100644 include/dt-bindings/reset/qcom,sdm845-aoss.h
diff --git a/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
new file mode 100644
index 000000000000..cd5dcafb4ed7
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
@@ -0,0 +1,52 @@
+Qualcomm AOSS Reset Controller
+======================================
+
+This binding describes a reset-controller found on AOSS (always on subsystem)
+for Qualcomm SDM845 SoCs.
+
+Required properties:
+- compatible:
+ Usage: required
+ Value type: <string>
+ Definition: must be:
+ "qcom,sdm845-aoss-reset"
+
+- reg:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: must specify the base address and size of the register
+ space.
+
+- #reset-cells:
+ Usage: required
+ Value type: <uint>
+ Definition: must be 1; cell entry represents the reset index.
+
+Example:
+
+aoss_reset: reset-controller@c2b0000 {
+ compatible = "qcom,sdm845-aoss-reset";
+ reg = <0xc2b0000 0x21000>;
+ #reset-cells = <1>;
+};
+
+Specifying reset lines connected to IP modules
+==============================================
+
+Device nodes that need access to reset lines should
+specify them as a reset phandle in their corresponding node as
+specified in reset.txt.
+
+For list of all valid reset indicies see
+<dt-bindings/reset/qcom,sdm845-aoss.h>
+
+Example:
+
+modem-pil@4080000 {
+ ...
+
+ resets = <&aoss_reset AOSS_CC_MSS_RESTART>;
+ reset-names = "mss_restart";
+
+ ...
+};
diff --git a/include/dt-bindings/reset/qcom,sdm845-aoss.h b/include/dt-bindings/reset/qcom,sdm845-aoss.h
new file mode 100644
index 000000000000..476c5fc873b6
--- /dev/null
+++ b/include/dt-bindings/reset/qcom,sdm845-aoss.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_RESET_AOSS_SDM_845_H
+#define _DT_BINDINGS_RESET_AOSS_SDM_845_H
+
+#define AOSS_CC_MSS_RESTART 0
+#define AOSS_CC_CAMSS_RESTART 1
+#define AOSS_CC_VENUS_RESTART 2
+#define AOSS_CC_GPU_RESTART 3
+#define AOSS_CC_DISPSS_RESTART 4
+#define AOSS_CC_WCSS_RESTART 5
+#define AOSS_CC_LPASS_RESTART 6
+
+#endif
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 19%]
* [PATCH v5 2/8] reset: qcom: AOSS (always on subsystem) reset controller
2018-05-21 17:27 13% [PATCH v5 0/8] Add support for remoteproc modem-pil on SDM845 SoCs Sibi Sankar
2018-05-21 17:27 19% ` [PATCH v5 1/8] dt-bindings: reset: Add AOSS reset bindings for " Sibi Sankar
@ 2018-05-21 17:27 16% ` Sibi Sankar
2018-06-23 0:46 0% ` Bjorn Andersson
2018-05-21 17:27 19% ` [PATCH v5 3/8] remoteproc: Move proxy unvote to handover irq handler Sibi Sankar
` (5 subsequent siblings)
7 siblings, 1 reply; 200+ results
From: Sibi Sankar @ 2018-05-21 17:27 UTC (permalink / raw)
To: bjorn.andersson, p.zabel, robh+dt
Cc: linux-remoteproc, linux-kernel, devicetree, sibis, georgi.djakov,
jassisinghbrar, ohad, mark.rutland, kyan, sricharan, akdwived,
linux-arm-msm, tsoni
Add reset controller driver for Qualcomm SDM845 SoC to
control reset signals provided by AOSS for Modem, Venus
ADSP, GPU, Camera, Wireless, Display subsystem
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
drivers/reset/Kconfig | 9 +++
drivers/reset/Makefile | 1 +
drivers/reset/reset-qcom-aoss.c | 133 ++++++++++++++++++++++++++++++++
3 files changed, 143 insertions(+)
create mode 100644 drivers/reset/reset-qcom-aoss.c
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index c0b292be1b72..756ad2b27d0f 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -82,6 +82,15 @@ config RESET_PISTACHIO
help
This enables the reset driver for ImgTec Pistachio SoCs.
+config RESET_QCOM_AOSS
+ bool "Qcom AOSS Reset Driver"
+ depends on ARCH_QCOM || COMPILE_TEST
+ help
+ This enables the AOSS (always on subsystem) reset driver
+ for Qualcomm SDM845 SoCs. Say Y if you want to control
+ reset signals provided by AOSS for Modem, Venus, ADSP,
+ GPU, Camera, Wireless, Display subsystem. Otherwise, say N.
+
config RESET_SIMPLE
bool "Simple Reset Controller Driver" if COMPILE_TEST
default ARCH_SOCFPGA || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index c1261dcfe9ad..6881e4d287f0 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
obj-$(CONFIG_RESET_MESON) += reset-meson.o
obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o
+obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o
obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
obj-$(CONFIG_RESET_STM32MP157) += reset-stm32mp1.o
obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
diff --git a/drivers/reset/reset-qcom-aoss.c b/drivers/reset/reset-qcom-aoss.c
new file mode 100644
index 000000000000..d9ca7339c434
--- /dev/null
+++ b/drivers/reset/reset-qcom-aoss.c
@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/of_device.h>
+#include <dt-bindings/reset/qcom,sdm845-aoss.h>
+
+struct qcom_aoss_reset_map {
+ unsigned int reg;
+};
+
+struct qcom_aoss_desc {
+ const struct qcom_aoss_reset_map *resets;
+ size_t num_resets;
+};
+
+struct qcom_aoss_reset_data {
+ struct reset_controller_dev rcdev;
+ void __iomem *base;
+ const struct qcom_aoss_desc *desc;
+};
+
+static const struct qcom_aoss_reset_map sdm845_aoss_resets[] = {
+ [AOSS_CC_MSS_RESTART] = {0x0},
+ [AOSS_CC_CAMSS_RESTART] = {0x1000},
+ [AOSS_CC_VENUS_RESTART] = {0x2000},
+ [AOSS_CC_GPU_RESTART] = {0x3000},
+ [AOSS_CC_DISPSS_RESTART] = {0x4000},
+ [AOSS_CC_WCSS_RESTART] = {0x10000},
+ [AOSS_CC_LPASS_RESTART] = {0x20000},
+};
+
+static const struct qcom_aoss_desc sdm845_aoss_desc = {
+ .resets = sdm845_aoss_resets,
+ .num_resets = ARRAY_SIZE(sdm845_aoss_resets),
+};
+
+static inline struct qcom_aoss_reset_data *to_qcom_aoss_reset_data(
+ struct reset_controller_dev *rcdev)
+{
+ return container_of(rcdev, struct qcom_aoss_reset_data, rcdev);
+}
+
+static int qcom_aoss_control_assert(struct reset_controller_dev *rcdev,
+ unsigned long idx)
+{
+ struct qcom_aoss_reset_data *data = to_qcom_aoss_reset_data(rcdev);
+ const struct qcom_aoss_reset_map *map = &data->desc->resets[idx];
+
+ writel(1, data->base + map->reg);
+ /* Wait 6 32kHz sleep cycles for reset */
+ usleep_range(200, 300);
+ return 0;
+}
+
+static int qcom_aoss_control_deassert(struct reset_controller_dev *rcdev,
+ unsigned long idx)
+{
+ struct qcom_aoss_reset_data *data = to_qcom_aoss_reset_data(rcdev);
+ const struct qcom_aoss_reset_map *map = &data->desc->resets[idx];
+
+ writel(0, data->base + map->reg);
+ /* Wait 6 32kHz sleep cycles for reset */
+ usleep_range(200, 300);
+ return 0;
+}
+
+static int qcom_aoss_control_reset(struct reset_controller_dev *rcdev,
+ unsigned long idx)
+{
+ qcom_aoss_control_assert(rcdev, idx);
+
+ return qcom_aoss_control_deassert(rcdev, idx);
+}
+
+static const struct reset_control_ops qcom_aoss_reset_ops = {
+ .reset = qcom_aoss_control_reset,
+ .assert = qcom_aoss_control_assert,
+ .deassert = qcom_aoss_control_deassert,
+};
+
+static int qcom_aoss_reset_probe(struct platform_device *pdev)
+{
+ struct qcom_aoss_reset_data *data;
+ struct device *dev = &pdev->dev;
+ const struct qcom_aoss_desc *desc;
+ struct resource *res;
+
+ desc = of_device_get_match_data(dev);
+ if (!desc)
+ return -EINVAL;
+
+ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ data->desc = desc;
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ data->base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(data->base))
+ return PTR_ERR(data->base);
+
+ data->rcdev.owner = THIS_MODULE;
+ data->rcdev.ops = &qcom_aoss_reset_ops;
+ data->rcdev.nr_resets = desc->num_resets;
+ data->rcdev.of_node = dev->of_node;
+
+ return devm_reset_controller_register(dev, &data->rcdev);
+}
+
+static const struct of_device_id qcom_aoss_reset_of_match[] = {
+ { .compatible = "qcom,sdm845-aoss-reset", .data = &sdm845_aoss_desc },
+ {}
+};
+
+static struct platform_driver qcom_aoss_reset_driver = {
+ .probe = qcom_aoss_reset_probe,
+ .driver = {
+ .name = "qcom_aoss_reset",
+ .of_match_table = qcom_aoss_reset_of_match,
+ },
+};
+
+builtin_platform_driver(qcom_aoss_reset_driver);
+
+MODULE_DESCRIPTION("Qualcomm AOSS Reset Driver");
+MODULE_LICENSE("GPL v2");
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 16%]
* [PATCH v5 3/8] remoteproc: Move proxy unvote to handover irq handler
2018-05-21 17:27 13% [PATCH v5 0/8] Add support for remoteproc modem-pil on SDM845 SoCs Sibi Sankar
2018-05-21 17:27 19% ` [PATCH v5 1/8] dt-bindings: reset: Add AOSS reset bindings for " Sibi Sankar
2018-05-21 17:27 16% ` [PATCH v5 2/8] reset: qcom: AOSS (always on subsystem) reset controller Sibi Sankar
@ 2018-05-21 17:27 19% ` Sibi Sankar
2018-05-22 4:35 0% ` Bjorn Andersson
2018-05-21 17:27 17% ` [PATCH v5 4/8] remoteproc: Synchronize proxy unvote from multiple contexts Sibi Sankar
` (4 subsequent siblings)
7 siblings, 1 reply; 200+ results
From: Sibi Sankar @ 2018-05-21 17:27 UTC (permalink / raw)
To: bjorn.andersson, p.zabel, robh+dt
Cc: linux-remoteproc, linux-kernel, devicetree, sibis, georgi.djakov,
jassisinghbrar, ohad, mark.rutland, kyan, sricharan, akdwived,
linux-arm-msm, tsoni
Introduce interrupt handler for smp2p ready interrupt to
handle start completion. Move the proxy votes for clocks
and regulators to the handover interrupt context.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
drivers/remoteproc/qcom_q6v5_pil.c | 29 +++++++++++++++++++++++------
1 file changed, 23 insertions(+), 6 deletions(-)
diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
index 76a0c00aa04a..6333bdcd9448 100644
--- a/drivers/remoteproc/qcom_q6v5_pil.c
+++ b/drivers/remoteproc/qcom_q6v5_pil.c
@@ -809,11 +809,6 @@ static int q6v5_start(struct rproc *rproc)
"Failed to reclaim mba buffer system may become unstable\n");
qproc->running = true;
- q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
- qproc->proxy_clk_count);
- q6v5_regulator_disable(qproc, qproc->proxy_regs,
- qproc->proxy_reg_count);
-
return 0;
reclaim_mpss:
@@ -892,6 +887,12 @@ static int q6v5_stop(struct rproc *rproc)
WARN_ON(ret);
reset_control_assert(qproc->mss_restart);
+
+ q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
+ qproc->proxy_clk_count);
+ q6v5_regulator_disable(qproc, qproc->proxy_regs,
+ qproc->proxy_reg_count);
+
q6v5_clk_disable(qproc->dev, qproc->active_clks,
qproc->active_clk_count);
q6v5_regulator_disable(qproc, qproc->active_regs,
@@ -959,7 +960,7 @@ static irqreturn_t q6v5_fatal_interrupt(int irq, void *dev)
return IRQ_HANDLED;
}
-static irqreturn_t q6v5_handover_interrupt(int irq, void *dev)
+static irqreturn_t q6v5_ready_interrupt(int irq, void *dev)
{
struct q6v5 *qproc = dev;
@@ -967,6 +968,18 @@ static irqreturn_t q6v5_handover_interrupt(int irq, void *dev)
return IRQ_HANDLED;
}
+static irqreturn_t q6v5_handover_interrupt(int irq, void *dev)
+{
+ struct q6v5 *qproc = dev;
+
+ q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
+ qproc->proxy_clk_count);
+ q6v5_regulator_disable(qproc, qproc->proxy_regs,
+ qproc->proxy_reg_count);
+
+ return IRQ_HANDLED;
+}
+
static irqreturn_t q6v5_stop_ack_interrupt(int irq, void *dev)
{
struct q6v5 *qproc = dev;
@@ -1194,6 +1207,10 @@ static int q6v5_probe(struct platform_device *pdev)
if (ret < 0)
goto free_rproc;
+ ret = q6v5_request_irq(qproc, pdev, "ready", q6v5_ready_interrupt);
+ if (ret < 0)
+ goto free_rproc;
+
ret = q6v5_request_irq(qproc, pdev, "handover", q6v5_handover_interrupt);
if (ret < 0)
goto free_rproc;
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 19%]
* [PATCH v5 4/8] remoteproc: Synchronize proxy unvote from multiple contexts
2018-05-21 17:27 13% [PATCH v5 0/8] Add support for remoteproc modem-pil on SDM845 SoCs Sibi Sankar
` (2 preceding siblings ...)
2018-05-21 17:27 19% ` [PATCH v5 3/8] remoteproc: Move proxy unvote to handover irq handler Sibi Sankar
@ 2018-05-21 17:27 17% ` Sibi Sankar
2018-05-21 17:27 21% ` [PATCH v5 5/8] dt-bindings: remoteproc: Add Q6v5 Modem PIL binding for SDM845 Sibi Sankar
` (3 subsequent siblings)
7 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2018-05-21 17:27 UTC (permalink / raw)
To: bjorn.andersson, p.zabel, robh+dt
Cc: linux-remoteproc, linux-kernel, devicetree, sibis, georgi.djakov,
jassisinghbrar, ohad, mark.rutland, kyan, sricharan, akdwived,
linux-arm-msm, tsoni
Synchronize proxy unvote of clks/regs from q6v5_stop and
handover interrupt to prevent multiple proxy unvotes
for a single rproc start.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
drivers/remoteproc/qcom_q6v5_pil.c | 73 ++++++++++++++++++++++--------
1 file changed, 54 insertions(+), 19 deletions(-)
diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
index 6333bdcd9448..a5fa6521bb83 100644
--- a/drivers/remoteproc/qcom_q6v5_pil.c
+++ b/drivers/remoteproc/qcom_q6v5_pil.c
@@ -143,6 +143,10 @@ struct q6v5 {
struct qcom_smem_state *state;
unsigned stop_bit;
+ int handover_irq;
+ int wdog_irq;
+ int fatal_irq;
+
struct clk *active_clks[8];
struct clk *proxy_clks[4];
int active_clk_count;
@@ -170,6 +174,7 @@ struct q6v5 {
struct qcom_rproc_ssr ssr_subdev;
struct qcom_sysmon *sysmon;
bool need_mem_protection;
+ bool unvoted_flag;
int mpss_perm;
int mba_perm;
int version;
@@ -304,6 +309,20 @@ static void q6v5_clk_disable(struct device *dev,
clk_disable_unprepare(clks[i]);
}
+static void q6v5_enable_irqs(struct q6v5 *qproc)
+{
+ enable_irq(qproc->wdog_irq);
+ enable_irq(qproc->fatal_irq);
+ enable_irq(qproc->handover_irq);
+}
+
+static void q6v5_disable_irqs(struct q6v5 *qproc)
+{
+ disable_irq(qproc->handover_irq);
+ disable_irq(qproc->fatal_irq);
+ disable_irq(qproc->wdog_irq);
+}
+
static int q6v5_xfer_mem_ownership(struct q6v5 *qproc, int *current_perm,
bool remote_owner, phys_addr_t addr,
size_t size)
@@ -727,6 +746,7 @@ static int q6v5_start(struct rproc *rproc)
int xfermemop_ret;
int ret;
+ qproc->unvoted_flag = false;
ret = q6v5_regulator_enable(qproc, qproc->proxy_regs,
qproc->proxy_reg_count);
if (ret) {
@@ -793,9 +813,12 @@ static int q6v5_start(struct rproc *rproc)
if (ret)
goto reclaim_mpss;
+ q6v5_enable_irqs(qproc);
+
ret = wait_for_completion_timeout(&qproc->start_done,
msecs_to_jiffies(5000));
if (ret == 0) {
+ q6v5_disable_irqs(qproc);
dev_err(qproc->dev, "start timed out\n");
ret = -ETIMEDOUT;
goto reclaim_mpss;
@@ -887,11 +910,14 @@ static int q6v5_stop(struct rproc *rproc)
WARN_ON(ret);
reset_control_assert(qproc->mss_restart);
+ q6v5_disable_irqs(qproc);
- q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
- qproc->proxy_clk_count);
- q6v5_regulator_disable(qproc, qproc->proxy_regs,
- qproc->proxy_reg_count);
+ if (!qproc->unvoted_flag) {
+ q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
+ qproc->proxy_clk_count);
+ q6v5_regulator_disable(qproc, qproc->proxy_regs,
+ qproc->proxy_reg_count);
+ }
q6v5_clk_disable(qproc->dev, qproc->active_clks,
qproc->active_clk_count);
@@ -972,10 +998,13 @@ static irqreturn_t q6v5_handover_interrupt(int irq, void *dev)
{
struct q6v5 *qproc = dev;
- q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
- qproc->proxy_clk_count);
- q6v5_regulator_disable(qproc, qproc->proxy_regs,
- qproc->proxy_reg_count);
+ if (!qproc->unvoted_flag) {
+ qproc->unvoted_flag = true;
+ q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
+ qproc->proxy_clk_count);
+ q6v5_regulator_disable(qproc, qproc->proxy_regs,
+ qproc->proxy_reg_count);
+ }
return IRQ_HANDLED;
}
@@ -1058,18 +1087,18 @@ static int q6v5_init_reset(struct q6v5 *qproc)
return 0;
}
-static int q6v5_request_irq(struct q6v5 *qproc,
+static inline int q6v5_request_irq(struct q6v5 *qproc,
struct platform_device *pdev,
const char *name,
- irq_handler_t thread_fn)
+ irq_handler_t thread_fn,
+ unsigned int *irq_num)
{
int ret;
ret = platform_get_irq_byname(pdev, name);
- if (ret < 0) {
- dev_err(&pdev->dev, "no %s IRQ defined\n", name);
- return ret;
- }
+
+ if (irq_num)
+ *irq_num = ret;
ret = devm_request_threaded_irq(&pdev->dev, ret,
NULL, thread_fn,
@@ -1199,26 +1228,32 @@ static int q6v5_probe(struct platform_device *pdev)
qproc->version = desc->version;
qproc->need_mem_protection = desc->need_mem_protection;
- ret = q6v5_request_irq(qproc, pdev, "wdog", q6v5_wdog_interrupt);
+ ret = q6v5_request_irq(qproc, pdev, "wdog", q6v5_wdog_interrupt,
+ &qproc->wdog_irq);
if (ret < 0)
goto free_rproc;
- ret = q6v5_request_irq(qproc, pdev, "fatal", q6v5_fatal_interrupt);
+ ret = q6v5_request_irq(qproc, pdev, "fatal", q6v5_fatal_interrupt,
+ &qproc->fatal_irq);
if (ret < 0)
goto free_rproc;
- ret = q6v5_request_irq(qproc, pdev, "ready", q6v5_ready_interrupt);
+ ret = q6v5_request_irq(qproc, pdev, "ready", q6v5_ready_interrupt,
+ NULL);
if (ret < 0)
goto free_rproc;
- ret = q6v5_request_irq(qproc, pdev, "handover", q6v5_handover_interrupt);
+ ret = q6v5_request_irq(qproc, pdev, "handover", q6v5_handover_interrupt,
+ &qproc->handover_irq);
if (ret < 0)
goto free_rproc;
- ret = q6v5_request_irq(qproc, pdev, "stop-ack", q6v5_stop_ack_interrupt);
+ ret = q6v5_request_irq(qproc, pdev, "stop-ack", q6v5_stop_ack_interrupt,
+ NULL);
if (ret < 0)
goto free_rproc;
+ q6v5_disable_irqs(qproc);
qproc->state = qcom_smem_state_get(&pdev->dev, "stop", &qproc->stop_bit);
if (IS_ERR(qproc->state)) {
ret = PTR_ERR(qproc->state);
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 17%]
* [PATCH v5 5/8] dt-bindings: remoteproc: Add Q6v5 Modem PIL binding for SDM845
2018-05-21 17:27 13% [PATCH v5 0/8] Add support for remoteproc modem-pil on SDM845 SoCs Sibi Sankar
` (3 preceding siblings ...)
2018-05-21 17:27 17% ` [PATCH v5 4/8] remoteproc: Synchronize proxy unvote from multiple contexts Sibi Sankar
@ 2018-05-21 17:27 21% ` Sibi Sankar
2018-05-22 15:56 0% ` Rob Herring
2018-05-21 17:27 20% ` [PATCH v5 6/8] remoteproc: qcom: Introduce reset assert/deassert helper functions Sibi Sankar
` (2 subsequent siblings)
7 siblings, 1 reply; 200+ results
From: Sibi Sankar @ 2018-05-21 17:27 UTC (permalink / raw)
To: bjorn.andersson, p.zabel, robh+dt
Cc: linux-remoteproc, linux-kernel, devicetree, sibis, georgi.djakov,
jassisinghbrar, ohad, mark.rutland, kyan, sricharan, akdwived,
linux-arm-msm, tsoni
Add new compatible string for Qualcomm SDM845 SoCs
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
index 00d3d58a102f..d90182425450 100644
--- a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
+++ b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
@@ -11,6 +11,7 @@ on the Qualcomm Hexagon core.
"qcom,msm8916-mss-pil",
"qcom,msm8974-mss-pil"
"qcom,msm8996-mss-pil"
+ "qcom,sdm845-mss-pil"
- reg:
Usage: required
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 21%]
* [PATCH v5 6/8] remoteproc: qcom: Introduce reset assert/deassert helper functions
2018-05-21 17:27 13% [PATCH v5 0/8] Add support for remoteproc modem-pil on SDM845 SoCs Sibi Sankar
` (4 preceding siblings ...)
2018-05-21 17:27 21% ` [PATCH v5 5/8] dt-bindings: remoteproc: Add Q6v5 Modem PIL binding for SDM845 Sibi Sankar
@ 2018-05-21 17:27 20% ` Sibi Sankar
2018-05-21 17:27 15% ` [PATCH v5 7/8] remoteproc: qcom: Add support for mss remoteproc on SDM845 Sibi Sankar
2018-05-21 17:27 20% ` [PATCH v5 8/8] remoteproc: qcom: Allow defining GLINK edge for mss remoteproc Sibi Sankar
7 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2018-05-21 17:27 UTC (permalink / raw)
To: bjorn.andersson, p.zabel, robh+dt
Cc: linux-remoteproc, linux-kernel, devicetree, sibis, georgi.djakov,
jassisinghbrar, ohad, mark.rutland, kyan, sricharan, akdwived,
linux-arm-msm, tsoni
Adding reset assert/deassert helper functions to handle SoC
specific reset sequences. This wil be used by SDM845 to assert and
deassert ALT_RESET and MSS_RESET signals.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
drivers/remoteproc/qcom_q6v5_pil.c | 16 +++++++++++++---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
index a5fa6521bb83..552805bc07c1 100644
--- a/drivers/remoteproc/qcom_q6v5_pil.c
+++ b/drivers/remoteproc/qcom_q6v5_pil.c
@@ -352,6 +352,16 @@ static int q6v5_load(struct rproc *rproc, const struct firmware *fw)
return 0;
}
+static int q6v5_reset_assert(struct q6v5 *qproc)
+{
+ return reset_control_assert(qproc->mss_restart);
+}
+
+static int q6v5_reset_deassert(struct q6v5 *qproc)
+{
+ return reset_control_deassert(qproc->mss_restart);
+}
+
static int q6v5_rmb_pbl_wait(struct q6v5 *qproc, int ms)
{
unsigned long timeout;
@@ -767,7 +777,7 @@ static int q6v5_start(struct rproc *rproc)
dev_err(qproc->dev, "failed to enable supplies\n");
goto disable_proxy_clk;
}
- ret = reset_control_deassert(qproc->mss_restart);
+ ret = q6v5_reset_deassert(qproc);
if (ret) {
dev_err(qproc->dev, "failed to deassert mss restart\n");
goto disable_vdd;
@@ -859,7 +869,7 @@ static int q6v5_start(struct rproc *rproc)
qproc->active_clk_count);
assert_reset:
- reset_control_assert(qproc->mss_restart);
+ q6v5_reset_assert(qproc);
disable_vdd:
q6v5_regulator_disable(qproc, qproc->active_regs,
qproc->active_reg_count);
@@ -909,7 +919,7 @@ static int q6v5_stop(struct rproc *rproc)
qproc->mpss_phys, qproc->mpss_size);
WARN_ON(ret);
- reset_control_assert(qproc->mss_restart);
+ q6v5_reset_assert(qproc);
q6v5_disable_irqs(qproc);
if (!qproc->unvoted_flag) {
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 20%]
* [PATCH v5 7/8] remoteproc: qcom: Add support for mss remoteproc on SDM845
2018-05-21 17:27 13% [PATCH v5 0/8] Add support for remoteproc modem-pil on SDM845 SoCs Sibi Sankar
` (5 preceding siblings ...)
2018-05-21 17:27 20% ` [PATCH v5 6/8] remoteproc: qcom: Introduce reset assert/deassert helper functions Sibi Sankar
@ 2018-05-21 17:27 15% ` Sibi Sankar
2018-05-21 17:27 20% ` [PATCH v5 8/8] remoteproc: qcom: Allow defining GLINK edge for mss remoteproc Sibi Sankar
7 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2018-05-21 17:27 UTC (permalink / raw)
To: bjorn.andersson, p.zabel, robh+dt
Cc: linux-remoteproc, linux-kernel, devicetree, sibis, georgi.djakov,
jassisinghbrar, ohad, mark.rutland, kyan, sricharan, akdwived,
linux-arm-msm, tsoni
>From SDM845, the Q6SS reset sequence on software side has been
simplified with the introduction of boot FSM which assists in
bringing the Q6 out of reset.
SDM845 brings a new reset signal ALT_RESET which is a part of
the MSS subsystem hence requires reset clks to be enabled before
assert/deassert. Use the SoC specific reset helper function to
add support for ALT_RESET in SDM845.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
drivers/remoteproc/qcom_q6v5_pil.c | 109 ++++++++++++++++++++++++++++-
1 file changed, 107 insertions(+), 2 deletions(-)
diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
index 552805bc07c1..5e85ce975ef8 100644
--- a/drivers/remoteproc/qcom_q6v5_pil.c
+++ b/drivers/remoteproc/qcom_q6v5_pil.c
@@ -57,6 +57,8 @@
#define RMB_PMI_META_DATA_REG 0x10
#define RMB_PMI_CODE_START_REG 0x14
#define RMB_PMI_CODE_LENGTH_REG 0x18
+#define RMB_MBA_MSS_STATUS 0x40
+#define RMB_MBA_ALT_RESET 0x44
#define RMB_CMD_META_DATA_READY 0x1
#define RMB_CMD_LOAD_READY 0x2
@@ -104,6 +106,13 @@
#define QDSP6SS_XO_CBCR 0x0038
#define QDSP6SS_ACC_OVERRIDE_VAL 0x20
+/* QDSP6v65 parameters */
+#define QDSP6SS_SLEEP 0x3C
+#define QDSP6SS_BOOT_CORE_START 0x400
+#define QDSP6SS_BOOT_CMD 0x404
+#define SLEEP_CHECK_MAX_LOOPS 200
+#define BOOT_FSM_TIMEOUT 10000
+
struct reg_info {
struct regulator *reg;
int uV;
@@ -121,9 +130,11 @@ struct rproc_hexagon_res {
struct qcom_mss_reg_res *proxy_supply;
struct qcom_mss_reg_res *active_supply;
char **proxy_clk_names;
+ char **reset_clk_names;
char **active_clk_names;
int version;
bool need_mem_protection;
+ bool has_alt_reset;
};
struct q6v5 {
@@ -148,8 +159,10 @@ struct q6v5 {
int fatal_irq;
struct clk *active_clks[8];
+ struct clk *reset_clks[4];
struct clk *proxy_clks[4];
int active_clk_count;
+ int reset_clk_count;
int proxy_clk_count;
struct reg_info active_regs[1];
@@ -174,6 +187,7 @@ struct q6v5 {
struct qcom_rproc_ssr ssr_subdev;
struct qcom_sysmon *sysmon;
bool need_mem_protection;
+ bool has_alt_reset;
bool unvoted_flag;
int mpss_perm;
int mba_perm;
@@ -184,6 +198,7 @@ enum {
MSS_MSM8916,
MSS_MSM8974,
MSS_MSM8996,
+ MSS_SDM845,
};
static int q6v5_regulator_init(struct device *dev, struct reg_info *regs,
@@ -354,11 +369,22 @@ static int q6v5_load(struct rproc *rproc, const struct firmware *fw)
static int q6v5_reset_assert(struct q6v5 *qproc)
{
+ if (qproc->has_alt_reset)
+ return reset_control_reset(qproc->mss_restart);
+
return reset_control_assert(qproc->mss_restart);
}
static int q6v5_reset_deassert(struct q6v5 *qproc)
{
+ if (qproc->has_alt_reset) {
+ writel(1, qproc->rmb_base + RMB_MBA_ALT_RESET);
+ reset_control_reset(qproc->mss_restart);
+ writel(0, qproc->rmb_base + RMB_MBA_ALT_RESET);
+
+ return 0;
+ }
+
return reset_control_deassert(qproc->mss_restart);
}
@@ -414,8 +440,35 @@ static int q6v5proc_reset(struct q6v5 *qproc)
int ret;
int i;
+ if (qproc->version == MSS_SDM845) {
+ val = readl(qproc->reg_base + QDSP6SS_SLEEP);
+ val |= 0x1;
+ writel(val, qproc->reg_base + QDSP6SS_SLEEP);
- if (qproc->version == MSS_MSM8996) {
+ ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_SLEEP,
+ val, !(val & BIT(31)), 1,
+ SLEEP_CHECK_MAX_LOOPS);
+ if (ret) {
+ dev_err(qproc->dev, "QDSP6SS Sleep clock timed out\n");
+ return -ETIMEDOUT;
+ }
+
+ /* De-assert QDSP6 stop core */
+ writel(1, qproc->reg_base + QDSP6SS_BOOT_CORE_START);
+ /* Trigger boot FSM */
+ writel(1, qproc->reg_base + QDSP6SS_BOOT_CMD);
+
+ ret = readl_poll_timeout(qproc->rmb_base + RMB_MBA_MSS_STATUS,
+ val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT);
+ if (ret) {
+ dev_err(qproc->dev, "Boot FSM failed to complete.\n");
+ /* Reset the modem so that boot FSM is in reset state */
+ q6v5_reset_deassert(qproc);
+ return ret;
+ }
+
+ goto pbl_wait;
+ } else if (qproc->version == MSS_MSM8996) {
/* Override the ACC value if required */
writel(QDSP6SS_ACC_OVERRIDE_VAL,
qproc->reg_base + QDSP6SS_STRAP_ACC);
@@ -523,6 +576,7 @@ static int q6v5proc_reset(struct q6v5 *qproc)
val &= ~Q6SS_STOP_CORE;
writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
+pbl_wait:
/* Wait for PBL status */
ret = q6v5_rmb_pbl_wait(qproc, 1000);
if (ret == -ETIMEDOUT) {
@@ -777,10 +831,18 @@ static int q6v5_start(struct rproc *rproc)
dev_err(qproc->dev, "failed to enable supplies\n");
goto disable_proxy_clk;
}
+
+ ret = q6v5_clk_enable(qproc->dev, qproc->reset_clks,
+ qproc->reset_clk_count);
+ if (ret) {
+ dev_err(qproc->dev, "failed to enable reset clocks\n");
+ goto disable_vdd;
+ }
+
ret = q6v5_reset_deassert(qproc);
if (ret) {
dev_err(qproc->dev, "failed to deassert mss restart\n");
- goto disable_vdd;
+ goto disable_reset_clks;
}
ret = q6v5_clk_enable(qproc->dev, qproc->active_clks,
@@ -870,6 +932,9 @@ static int q6v5_start(struct rproc *rproc)
assert_reset:
q6v5_reset_assert(qproc);
+disable_reset_clks:
+ q6v5_clk_disable(qproc->dev, qproc->reset_clks,
+ qproc->reset_clk_count);
disable_vdd:
q6v5_regulator_disable(qproc, qproc->active_regs,
qproc->active_reg_count);
@@ -929,6 +994,8 @@ static int q6v5_stop(struct rproc *rproc)
qproc->proxy_reg_count);
}
+ q6v5_clk_disable(qproc->dev, qproc->reset_clks,
+ qproc->reset_clk_count);
q6v5_clk_disable(qproc->dev, qproc->active_clks,
qproc->active_clk_count);
q6v5_regulator_disable(qproc, qproc->active_regs,
@@ -1208,6 +1275,14 @@ static int q6v5_probe(struct platform_device *pdev)
}
qproc->proxy_clk_count = ret;
+ ret = q6v5_init_clocks(&pdev->dev, qproc->reset_clks,
+ desc->reset_clk_names);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "Failed to get reset clocks.\n");
+ goto free_rproc;
+ }
+ qproc->reset_clk_count = ret;
+
ret = q6v5_init_clocks(&pdev->dev, qproc->active_clks,
desc->active_clk_names);
if (ret < 0) {
@@ -1237,6 +1312,7 @@ static int q6v5_probe(struct platform_device *pdev)
goto free_rproc;
qproc->version = desc->version;
+ qproc->has_alt_reset = desc->has_alt_reset;
qproc->need_mem_protection = desc->need_mem_protection;
ret = q6v5_request_irq(qproc, pdev, "wdog", q6v5_wdog_interrupt,
&qproc->wdog_irq);
@@ -1301,6 +1377,31 @@ static int q6v5_remove(struct platform_device *pdev)
return 0;
}
+static const struct rproc_hexagon_res sdm845_mss = {
+ .hexagon_mba_image = "mba.mbn",
+ .proxy_clk_names = (char*[]){
+ "xo",
+ "axis2",
+ "prng",
+ NULL
+ },
+ .reset_clk_names = (char*[]){
+ "iface",
+ "snoc_axi",
+ NULL
+ },
+ .active_clk_names = (char*[]){
+ "bus",
+ "mem",
+ "gpll0_mss",
+ "mnoc_axi",
+ NULL
+ },
+ .need_mem_protection = true,
+ .has_alt_reset = true,
+ .version = MSS_SDM845,
+};
+
static const struct rproc_hexagon_res msm8996_mss = {
.hexagon_mba_image = "mba.mbn",
.proxy_clk_names = (char*[]){
@@ -1316,6 +1417,7 @@ static const struct rproc_hexagon_res msm8996_mss = {
NULL
},
.need_mem_protection = true,
+ .has_alt_reset = false,
.version = MSS_MSM8996,
};
@@ -1347,6 +1449,7 @@ static const struct rproc_hexagon_res msm8916_mss = {
NULL
},
.need_mem_protection = false,
+ .has_alt_reset = false,
.version = MSS_MSM8916,
};
@@ -1386,6 +1489,7 @@ static const struct rproc_hexagon_res msm8974_mss = {
NULL
},
.need_mem_protection = false,
+ .has_alt_reset = false,
.version = MSS_MSM8974,
};
@@ -1394,6 +1498,7 @@ static const struct of_device_id q6v5_of_match[] = {
{ .compatible = "qcom,msm8916-mss-pil", .data = &msm8916_mss},
{ .compatible = "qcom,msm8974-mss-pil", .data = &msm8974_mss},
{ .compatible = "qcom,msm8996-mss-pil", .data = &msm8996_mss},
+ { .compatible = "qcom,sdm845-mss-pil", .data = &sdm845_mss},
{ },
};
MODULE_DEVICE_TABLE(of, q6v5_of_match);
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 15%]
* [PATCH v5 8/8] remoteproc: qcom: Allow defining GLINK edge for mss remoteproc
2018-05-21 17:27 13% [PATCH v5 0/8] Add support for remoteproc modem-pil on SDM845 SoCs Sibi Sankar
` (6 preceding siblings ...)
2018-05-21 17:27 15% ` [PATCH v5 7/8] remoteproc: qcom: Add support for mss remoteproc on SDM845 Sibi Sankar
@ 2018-05-21 17:27 20% ` Sibi Sankar
7 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2018-05-21 17:27 UTC (permalink / raw)
To: bjorn.andersson, p.zabel, robh+dt
Cc: linux-remoteproc, linux-kernel, devicetree, sibis, georgi.djakov,
jassisinghbrar, ohad, mark.rutland, kyan, sricharan, akdwived,
linux-arm-msm, tsoni
Add GLINK subdevice to allow definition of GLINK edge as a
child of modem-pil.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
drivers/remoteproc/qcom_q6v5_pil.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
index 5e85ce975ef8..7656731a6c51 100644
--- a/drivers/remoteproc/qcom_q6v5_pil.c
+++ b/drivers/remoteproc/qcom_q6v5_pil.c
@@ -183,6 +183,7 @@ struct q6v5 {
void *mpss_region;
size_t mpss_size;
+ struct qcom_rproc_glink glink_subdev;
struct qcom_rproc_subdev smd_subdev;
struct qcom_rproc_ssr ssr_subdev;
struct qcom_sysmon *sysmon;
@@ -1347,6 +1348,7 @@ static int q6v5_probe(struct platform_device *pdev)
}
qproc->mpss_perm = BIT(QCOM_SCM_VMID_HLOS);
qproc->mba_perm = BIT(QCOM_SCM_VMID_HLOS);
+ qcom_add_glink_subdev(rproc, &qproc->glink_subdev);
qcom_add_smd_subdev(rproc, &qproc->smd_subdev);
qcom_add_ssr_subdev(rproc, &qproc->ssr_subdev, "mpss");
qproc->sysmon = qcom_add_sysmon_subdev(rproc, "modem", 0x12);
@@ -1370,6 +1372,7 @@ static int q6v5_remove(struct platform_device *pdev)
rproc_del(qproc->rproc);
qcom_remove_sysmon_subdev(qproc->sysmon);
+ qcom_remove_glink_subdev(qproc->rproc, &qproc->glink_subdev);
qcom_remove_smd_subdev(qproc->rproc, &qproc->smd_subdev);
qcom_remove_ssr_subdev(qproc->rproc, &qproc->ssr_subdev);
rproc_free(qproc->rproc);
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 20%]
* [PATCH v2] remoteproc: Introduce prepare/unprepare ops for rproc coredump
@ 2018-05-21 18:45 15% Sibi Sankar
0 siblings, 1 reply; 200+ results
From: Sibi Sankar @ 2018-05-21 18:45 UTC (permalink / raw)
To: bjorn.andersson, ohad
Cc: linux-remoteproc, linux-kernel, linux-arm-msm, Sibi Sankar
In some occasions the remoteproc device might need to
prepare some hardware before the coredump can be performed
and cleanup the state afterwards.
Q6V5 modem requires the mba to be loaded before the
coredump and some cleanup of the resources afterwards.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
This patch depends on the following patches:
https://patchwork.kernel.org/patch/10416047/
https://patchwork.kernel.org/patch/10416031/
drivers/remoteproc/qcom_q6v5_pil.c | 62 ++++++++++++++++++++----
drivers/remoteproc/remoteproc_core.c | 5 ++
drivers/remoteproc/remoteproc_internal.h | 16 ++++++
include/linux/remoteproc.h | 4 ++
4 files changed, 77 insertions(+), 10 deletions(-)
diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
index 7656731a6c51..4a33e50b6aeb 100644
--- a/drivers/remoteproc/qcom_q6v5_pil.c
+++ b/drivers/remoteproc/qcom_q6v5_pil.c
@@ -173,6 +173,7 @@ struct q6v5 {
struct completion start_done;
struct completion stop_done;
bool running;
+ bool coredump_pending;
phys_addr_t mba_phys;
void *mba_region;
@@ -742,6 +743,7 @@ static int q6v5_mpss_load(struct q6v5 *qproc)
}
mpss_reloc = relocate ? min_addr : qproc->mpss_phys;
+ qproc->mpss_reloc = mpss_reloc;
/* Load firmware segments */
for (i = 0; i < ehdr->e_phnum; i++) {
phdr = &phdrs[i];
@@ -816,7 +818,7 @@ static int q6v5_start(struct rproc *rproc)
qproc->proxy_reg_count);
if (ret) {
dev_err(qproc->dev, "failed to enable proxy supplies\n");
- return ret;
+ goto clear_coredump_pending;
}
ret = q6v5_clk_enable(qproc->dev, qproc->proxy_clks,
@@ -880,6 +882,19 @@ static int q6v5_start(struct rproc *rproc)
goto halt_axi_ports;
}
+ if (qproc->coredump_pending) {
+ dev_info(qproc->dev, "MBA booted, skipping mpss for coredump\n");
+ qproc->coredump_pending = false;
+ q6v5_enable_irqs(qproc);
+ xfermemop_ret = q6v5_xfer_mem_ownership(qproc,
+ &qproc->mba_perm, false,
+ qproc->mba_phys,
+ qproc->mba_size);
+ if (xfermemop_ret)
+ dev_err(qproc->dev, "Failed to reclaim mba buffer\n");
+ return 0;
+ }
+
dev_info(qproc->dev, "MBA booted, loading mpss\n");
ret = q6v5_mpss_load(qproc);
@@ -945,6 +960,8 @@ static int q6v5_start(struct rproc *rproc)
disable_proxy_reg:
q6v5_regulator_disable(qproc, qproc->proxy_regs,
qproc->proxy_reg_count);
+clear_coredump_pending:
+ qproc->coredump_pending = false;
return ret;
}
@@ -955,17 +972,19 @@ static int q6v5_stop(struct rproc *rproc)
int ret;
u32 val;
- qproc->running = false;
-
- qcom_smem_state_update_bits(qproc->state,
- BIT(qproc->stop_bit), BIT(qproc->stop_bit));
+ if (qproc->running) {
+ qproc->running = false;
+ qcom_smem_state_update_bits(qproc->state,
+ BIT(qproc->stop_bit), BIT(qproc->stop_bit));
- ret = wait_for_completion_timeout(&qproc->stop_done,
- msecs_to_jiffies(5000));
- if (ret == 0)
- dev_err(qproc->dev, "timed out on wait\n");
+ ret = wait_for_completion_timeout(&qproc->stop_done,
+ msecs_to_jiffies(5000));
+ if (ret == 0)
+ dev_err(qproc->dev, "timed out on wait\n");
- qcom_smem_state_update_bits(qproc->state, BIT(qproc->stop_bit), 0);
+ qcom_smem_state_update_bits(qproc->state,
+ BIT(qproc->stop_bit), 0);
+ }
q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
@@ -1017,10 +1036,31 @@ static void *q6v5_da_to_va(struct rproc *rproc, u64 da, int len)
return qproc->mpss_region + offset;
}
+static int qcom_mpss_register_dump_segments(struct rproc *rproc,
+ const struct firmware *fw_unused)
+{
+ const struct firmware *fw;
+ struct q6v5 *qproc = (struct q6v5 *)rproc->priv;
+ int ret;
+
+ ret = request_firmware(&fw, "modem.mdt", qproc->dev);
+ if (ret < 0) {
+ dev_err(qproc->dev, "unable to load modem.mdt\n");
+ return ret;
+ }
+ ret = qcom_register_dump_segments(rproc, fw);
+
+ release_firmware(fw);
+ return ret;
+}
+
static const struct rproc_ops q6v5_ops = {
.start = q6v5_start,
.stop = q6v5_stop,
.da_to_va = q6v5_da_to_va,
+ .parse_fw = qcom_mpss_register_dump_segments,
+ .prepare_coredump = q6v5_start,
+ .unprepare_coredump = q6v5_stop,
.load = q6v5_load,
};
@@ -1036,6 +1076,7 @@ static irqreturn_t q6v5_wdog_interrupt(int irq, void *dev)
return IRQ_HANDLED;
}
+ qproc->coredump_pending = true;
msg = qcom_smem_get(QCOM_SMEM_HOST_ANY, MPSS_CRASH_REASON_SMEM, &len);
if (!IS_ERR(msg) && len > 0 && msg[0])
dev_err(qproc->dev, "watchdog received: %s\n", msg);
@@ -1053,6 +1094,7 @@ static irqreturn_t q6v5_fatal_interrupt(int irq, void *dev)
size_t len;
char *msg;
+ qproc->coredump_pending = true;
msg = qcom_smem_get(QCOM_SMEM_HOST_ANY, MPSS_CRASH_REASON_SMEM, &len);
if (!IS_ERR(msg) && len > 0 && msg[0])
dev_err(qproc->dev, "fatal error received: %s\n", msg);
diff --git a/drivers/remoteproc/remoteproc_core.c b/drivers/remoteproc/remoteproc_core.c
index a9609d971f7f..8c254d9b5c67 100644
--- a/drivers/remoteproc/remoteproc_core.c
+++ b/drivers/remoteproc/remoteproc_core.c
@@ -1083,6 +1083,9 @@ static void rproc_coredump(struct rproc *rproc)
if (list_empty(&rproc->dump_segments))
return;
+ if (rproc_prepare_coredump(rproc))
+ return;
+
data_size = sizeof(*ehdr);
list_for_each_entry(segment, &rproc->dump_segments, node) {
data_size += sizeof(*phdr) + segment->size;
@@ -1139,6 +1142,8 @@ static void rproc_coredump(struct rproc *rproc)
}
dev_coredumpv(&rproc->dev, data, data_size, GFP_KERNEL);
+
+ rproc_unprepare_coredump(rproc);
}
/**
diff --git a/drivers/remoteproc/remoteproc_internal.h b/drivers/remoteproc/remoteproc_internal.h
index 7570beb035b5..22a1b276e110 100644
--- a/drivers/remoteproc/remoteproc_internal.h
+++ b/drivers/remoteproc/remoteproc_internal.h
@@ -96,6 +96,22 @@ static inline int rproc_parse_fw(struct rproc *rproc, const struct firmware *fw)
return 0;
}
+static inline int rproc_prepare_coredump(struct rproc *rproc)
+{
+ if (rproc->ops->prepare_coredump)
+ return rproc->ops->prepare_coredump(rproc);
+
+ return 0;
+}
+
+static inline int rproc_unprepare_coredump(struct rproc *rproc)
+{
+ if (rproc->ops->unprepare_coredump)
+ return rproc->ops->unprepare_coredump(rproc);
+
+ return 0;
+}
+
static inline
struct resource_table *rproc_find_loaded_rsc_table(struct rproc *rproc,
const struct firmware *fw)
diff --git a/include/linux/remoteproc.h b/include/linux/remoteproc.h
index dfdaede9139e..010819e01279 100644
--- a/include/linux/remoteproc.h
+++ b/include/linux/remoteproc.h
@@ -333,6 +333,8 @@ struct firmware;
* @kick: kick a virtqueue (virtqueue id given as a parameter)
* @da_to_va: optional platform hook to perform address translations
* @load_rsc_table: load resource table from firmware image
+ * @prepare_coredump: prepare function, called before coredump
+ * @unprepare_coredump: unprepare function, called post coredump
* @find_loaded_rsc_table: find the loaded resouce table
* @load: load firmeware to memory, where the remote processor
* expects to find it
@@ -345,6 +347,8 @@ struct rproc_ops {
void (*kick)(struct rproc *rproc, int vqid);
void * (*da_to_va)(struct rproc *rproc, u64 da, int len);
int (*parse_fw)(struct rproc *rproc, const struct firmware *fw);
+ int (*prepare_coredump)(struct rproc *rproc);
+ int (*unprepare_coredump)(struct rproc *rproc);
struct resource_table *(*find_loaded_rsc_table)(
struct rproc *rproc, const struct firmware *fw);
int (*load)(struct rproc *rproc, const struct firmware *fw);
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 15%]
* Re: [PATCH v5 3/8] remoteproc: Move proxy unvote to handover irq handler
2018-05-21 17:27 19% ` [PATCH v5 3/8] remoteproc: Move proxy unvote to handover irq handler Sibi Sankar
@ 2018-05-22 4:35 0% ` Bjorn Andersson
2018-05-22 6:31 6% ` Sibi S
0 siblings, 1 reply; 200+ results
From: Bjorn Andersson @ 2018-05-22 4:35 UTC (permalink / raw)
To: Sibi Sankar
Cc: p.zabel, robh+dt, linux-remoteproc, linux-kernel, devicetree,
georgi.djakov, jassisinghbrar, ohad, mark.rutland, kyan,
sricharan, akdwived, linux-arm-msm, tsoni
On Mon 21 May 10:27 PDT 2018, Sibi Sankar wrote:
> Introduce interrupt handler for smp2p ready interrupt to
> handle start completion. Move the proxy votes for clocks
> and regulators to the handover interrupt context.
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
I added the "synchronization logic" of patch 4 to this one, to make it
functional and after testing on db820c I merged patch 3 through 8 into
rproc-next.
I skipped the remainder of patch 4, as I think the ready_irq should be
included and I wonder if irq management can remove the need for the
"running" variable.
I also moved the enable_irq before we actually start the core, since
it's been shown downstream that the smp2p irq might fire fast enough for
us to miss it (and the smp2p driver does not redeliver interrupts).
Regards,
Bjorn
> ---
> drivers/remoteproc/qcom_q6v5_pil.c | 29 +++++++++++++++++++++++------
> 1 file changed, 23 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
> index 76a0c00aa04a..6333bdcd9448 100644
> --- a/drivers/remoteproc/qcom_q6v5_pil.c
> +++ b/drivers/remoteproc/qcom_q6v5_pil.c
> @@ -809,11 +809,6 @@ static int q6v5_start(struct rproc *rproc)
> "Failed to reclaim mba buffer system may become unstable\n");
> qproc->running = true;
>
> - q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
> - qproc->proxy_clk_count);
> - q6v5_regulator_disable(qproc, qproc->proxy_regs,
> - qproc->proxy_reg_count);
> -
> return 0;
>
> reclaim_mpss:
> @@ -892,6 +887,12 @@ static int q6v5_stop(struct rproc *rproc)
> WARN_ON(ret);
>
> reset_control_assert(qproc->mss_restart);
> +
> + q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
> + qproc->proxy_clk_count);
> + q6v5_regulator_disable(qproc, qproc->proxy_regs,
> + qproc->proxy_reg_count);
> +
> q6v5_clk_disable(qproc->dev, qproc->active_clks,
> qproc->active_clk_count);
> q6v5_regulator_disable(qproc, qproc->active_regs,
> @@ -959,7 +960,7 @@ static irqreturn_t q6v5_fatal_interrupt(int irq, void *dev)
> return IRQ_HANDLED;
> }
>
> -static irqreturn_t q6v5_handover_interrupt(int irq, void *dev)
> +static irqreturn_t q6v5_ready_interrupt(int irq, void *dev)
> {
> struct q6v5 *qproc = dev;
>
> @@ -967,6 +968,18 @@ static irqreturn_t q6v5_handover_interrupt(int irq, void *dev)
> return IRQ_HANDLED;
> }
>
> +static irqreturn_t q6v5_handover_interrupt(int irq, void *dev)
> +{
> + struct q6v5 *qproc = dev;
> +
> + q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
> + qproc->proxy_clk_count);
> + q6v5_regulator_disable(qproc, qproc->proxy_regs,
> + qproc->proxy_reg_count);
> +
> + return IRQ_HANDLED;
> +}
> +
> static irqreturn_t q6v5_stop_ack_interrupt(int irq, void *dev)
> {
> struct q6v5 *qproc = dev;
> @@ -1194,6 +1207,10 @@ static int q6v5_probe(struct platform_device *pdev)
> if (ret < 0)
> goto free_rproc;
>
> + ret = q6v5_request_irq(qproc, pdev, "ready", q6v5_ready_interrupt);
> + if (ret < 0)
> + goto free_rproc;
> +
> ret = q6v5_request_irq(qproc, pdev, "handover", q6v5_handover_interrupt);
> if (ret < 0)
> goto free_rproc;
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
^ permalink raw reply [relevance 0%]
* Re: [PATCH v5 3/8] remoteproc: Move proxy unvote to handover irq handler
2018-05-22 4:35 0% ` Bjorn Andersson
@ 2018-05-22 6:31 6% ` Sibi S
0 siblings, 0 replies; 200+ results
From: Sibi S @ 2018-05-22 6:31 UTC (permalink / raw)
To: Bjorn Andersson
Cc: p.zabel, robh+dt, linux-remoteproc, linux-kernel, devicetree,
georgi.djakov, jassisinghbrar, ohad, mark.rutland, kyan,
sricharan, akdwived, linux-arm-msm, tsoni
Hi Bjorn,
Thanks for the review.
On 05/22/2018 10:05 AM, Bjorn Andersson wrote:
> On Mon 21 May 10:27 PDT 2018, Sibi Sankar wrote:
>
>> Introduce interrupt handler for smp2p ready interrupt to
>> handle start completion. Move the proxy votes for clocks
>> and regulators to the handover interrupt context.
>>
>> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
>
> I added the "synchronization logic" of patch 4 to this one, to make it
> functional and after testing on db820c I merged patch 3 through 8 into
> rproc-next.
>
making the q6v5_request_irq return the irq number seems more elegant
unlike the approach I took earlier.
> I skipped the remainder of patch 4, as I think the ready_irq should be
> included and I wonder if irq management can remove the need for the
> "running" variable.
>
will include the ready_irq as well. I think we may need to keep
"running" for coredump but will check if it can substituted with
irq management.
> I also moved the enable_irq before we actually start the core, since
> it's been shown downstream that the smp2p irq might fire fast enough for
> us to miss it (and the smp2p driver does not redeliver interrupts).
>
> Regards,
> Bjorn
>
>> ---
>> drivers/remoteproc/qcom_q6v5_pil.c | 29 +++++++++++++++++++++++------
>> 1 file changed, 23 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
>> index 76a0c00aa04a..6333bdcd9448 100644
>> --- a/drivers/remoteproc/qcom_q6v5_pil.c
>> +++ b/drivers/remoteproc/qcom_q6v5_pil.c
>> @@ -809,11 +809,6 @@ static int q6v5_start(struct rproc *rproc)
>> "Failed to reclaim mba buffer system may become unstable\n");
>> qproc->running = true;
>>
>> - q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
>> - qproc->proxy_clk_count);
>> - q6v5_regulator_disable(qproc, qproc->proxy_regs,
>> - qproc->proxy_reg_count);
>> -
>> return 0;
>>
>> reclaim_mpss:
>> @@ -892,6 +887,12 @@ static int q6v5_stop(struct rproc *rproc)
>> WARN_ON(ret);
>>
>> reset_control_assert(qproc->mss_restart);
>> +
>> + q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
>> + qproc->proxy_clk_count);
>> + q6v5_regulator_disable(qproc, qproc->proxy_regs,
>> + qproc->proxy_reg_count);
>> +
>> q6v5_clk_disable(qproc->dev, qproc->active_clks,
>> qproc->active_clk_count);
>> q6v5_regulator_disable(qproc, qproc->active_regs,
>> @@ -959,7 +960,7 @@ static irqreturn_t q6v5_fatal_interrupt(int irq, void *dev)
>> return IRQ_HANDLED;
>> }
>>
>> -static irqreturn_t q6v5_handover_interrupt(int irq, void *dev)
>> +static irqreturn_t q6v5_ready_interrupt(int irq, void *dev)
>> {
>> struct q6v5 *qproc = dev;
>>
>> @@ -967,6 +968,18 @@ static irqreturn_t q6v5_handover_interrupt(int irq, void *dev)
>> return IRQ_HANDLED;
>> }
>>
>> +static irqreturn_t q6v5_handover_interrupt(int irq, void *dev)
>> +{
>> + struct q6v5 *qproc = dev;
>> +
>> + q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
>> + qproc->proxy_clk_count);
>> + q6v5_regulator_disable(qproc, qproc->proxy_regs,
>> + qproc->proxy_reg_count);
>> +
>> + return IRQ_HANDLED;
>> +}
>> +
>> static irqreturn_t q6v5_stop_ack_interrupt(int irq, void *dev)
>> {
>> struct q6v5 *qproc = dev;
>> @@ -1194,6 +1207,10 @@ static int q6v5_probe(struct platform_device *pdev)
>> if (ret < 0)
>> goto free_rproc;
>>
>> + ret = q6v5_request_irq(qproc, pdev, "ready", q6v5_ready_interrupt);
>> + if (ret < 0)
>> + goto free_rproc;
>> +
>> ret = q6v5_request_irq(qproc, pdev, "handover", q6v5_handover_interrupt);
>> if (ret < 0)
>> goto free_rproc;
>> --
>> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
>> a Linux Foundation Collaborative Project
>>
>
--
Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc, is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [relevance 6%]
* Re: [PATCH v5 5/8] dt-bindings: remoteproc: Add Q6v5 Modem PIL binding for SDM845
2018-05-21 17:27 21% ` [PATCH v5 5/8] dt-bindings: remoteproc: Add Q6v5 Modem PIL binding for SDM845 Sibi Sankar
@ 2018-05-22 15:56 0% ` Rob Herring
2018-05-29 14:37 6% ` Sibi S
0 siblings, 1 reply; 200+ results
From: Rob Herring @ 2018-05-22 15:56 UTC (permalink / raw)
To: Sibi Sankar
Cc: bjorn.andersson, p.zabel, linux-remoteproc, linux-kernel,
devicetree, georgi.djakov, jassisinghbrar, ohad, mark.rutland,
kyan, sricharan, akdwived, linux-arm-msm, tsoni
On Mon, May 21, 2018 at 10:57:11PM +0530, Sibi Sankar wrote:
> Add new compatible string for Qualcomm SDM845 SoCs
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
> Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt | 1 +
> 1 file changed, 1 insertion(+)
Please add acks/reviewed-bys when posting new versions.
Rob
^ permalink raw reply [relevance 0%]
* Re: [PATCH v5 1/8] dt-bindings: reset: Add AOSS reset bindings for SDM845 SoCs
2018-05-21 17:27 19% ` [PATCH v5 1/8] dt-bindings: reset: Add AOSS reset bindings for " Sibi Sankar
@ 2018-05-22 16:17 0% ` Rob Herring
2018-06-23 0:44 0% ` Bjorn Andersson
1 sibling, 0 replies; 200+ results
From: Rob Herring @ 2018-05-22 16:17 UTC (permalink / raw)
To: Sibi Sankar
Cc: bjorn.andersson, p.zabel, linux-remoteproc, linux-kernel,
devicetree, georgi.djakov, jassisinghbrar, ohad, mark.rutland,
kyan, sricharan, akdwived, linux-arm-msm, tsoni
On Mon, May 21, 2018 at 10:57:07PM +0530, Sibi Sankar wrote:
> Add SDM845 AOSS (always on subsystem) reset controller binding
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
> .../bindings/reset/qcom,aoss-reset.txt | 52 +++++++++++++++++++
> include/dt-bindings/reset/qcom,sdm845-aoss.h | 17 ++++++
> 2 files changed, 69 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
> create mode 100644 include/dt-bindings/reset/qcom,sdm845-aoss.h
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [relevance 0%]
* Re: [PATCH v2] remoteproc: Introduce prepare/unprepare ops for rproc coredump
@ 2018-05-29 14:06 6% ` Sibi S
0 siblings, 0 replies; 200+ results
From: Sibi S @ 2018-05-29 14:06 UTC (permalink / raw)
To: Bjorn Andersson; +Cc: ohad, linux-remoteproc, linux-kernel, linux-arm-msm
Hi Bjorn,
Thanks for the review.
On 05/29/2018 10:35 AM, Bjorn Andersson wrote:
> On Mon 21 May 11:45 PDT 2018, Sibi Sankar wrote:
>
>> In some occasions the remoteproc device might need to
>> prepare some hardware before the coredump can be performed
>> and cleanup the state afterwards.
>>
>> Q6V5 modem requires the mba to be loaded before the
>> coredump and some cleanup of the resources afterwards.
>>
>
> This describes two different changes, so please put it in two+ patches.
>
The second change just describes an example of a remoteproc device
that requires remoteproc coredump prepare and unprepare but sure
with restructuring required in msa it definitely will require 2+
patches.
> [..]
>> diff --git a/include/linux/remoteproc.h b/include/linux/remoteproc.h
>> index dfdaede9139e..010819e01279 100644
>> --- a/include/linux/remoteproc.h
>> +++ b/include/linux/remoteproc.h
>> @@ -333,6 +333,8 @@ struct firmware;
>> * @kick: kick a virtqueue (virtqueue id given as a parameter)
>> * @da_to_va: optional platform hook to perform address translations
>> * @load_rsc_table: load resource table from firmware image
>> + * @prepare_coredump: prepare function, called before coredump
>> + * @unprepare_coredump: unprepare function, called post coredump
>
> I believe there will be other cases where we will need driver-specific
> logic to extract the memory content of the segments, e.g. through custom
> hardware sequences or non-mmio reads.
>
> To support this I think we should extend the struct rproc_dump_segment
> to carry an optional "dump" function that if specified will be used
> instead of the memcpy in rproc_coredump(). Drivers can then for each
> segment specify this function, if needed.
>
In q6 modem mba needs to unlocked just once for all the segments to
be dumped but as you say other remote processors may need it for each
segment. This logic should be internal to the dump function anyway. So
will use the dump function approach. What about the cleanup path, can we
still reserve it till the coredump is done?
> Through some restructuring in the msa driver and your patch you should
> be able to implement this using such a mechanism instead - and it would
> be useful to these other cases as well.
>
>
> PS. I hope we can get away from some of the conditionals in your patch
> through some restructuring of the code.
>
Thought you might preferred the conditionals with the least amount of
code addition/change but having prepare and unprepare coredump again
calling q6v5_start/stop respectively seemed a little hacky anyway.
Sure will restructure msa as needed :)
> Regards,
> Bjorn
>
--
Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc, is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [relevance 6%]
* [PATCH v4 0/3] Cleanup excessive DSI host controller version checks
@ 2018-05-29 14:20 14% Sibi Sankar
2018-05-29 14:20 20% ` [PATCH v4 1/3] drm/msm/dsi: add dsi host helper functions support Sibi Sankar
` (2 more replies)
0 siblings, 3 replies; 200+ results
From: Sibi Sankar @ 2018-05-29 14:20 UTC (permalink / raw)
To: architt, robdclark, jcrouse
Cc: dri-devel, linux-arm-msm, linux-kernel, Sibi Sankar
This patch series aims to create and bind dsi host controller helper
functions to functionalities that vary across DSI v2, DSI 6G 1.x and
DSI 6G v2.0+ controllers. These functionalities are currently under
excessive version checks which is now replaced with the corresponding
helper function.
V4:
None (seems like the unbalanced mutex unlock is already
fixed now)
V3:
Removed redundant mode checks in calc_clk_rate_6g/v2
Removed dev->struct_mutex unlock in tx_buf_alloc_6g
Use msm_gem_kernel_new in tx_buf_alloc_6g
Modified author to first name/last name format
Reviewed-by: Archit Taneja <architt@codeaurora.org>
V2:
Removes command broadcast support for DSI 6G v2.0+ controllers from
the patch series and incorporates all the suggested corrections
Sibi Sankar (3):
drm/msm/dsi: add dsi host helper functions support
drm/msm/dsi: add implementation for helper functions
drm/msm/dsi: replace version checks with helper functions
drivers/gpu/drm/msm/dsi/dsi.h | 16 ++
drivers/gpu/drm/msm/dsi/dsi_cfg.c | 56 ++++-
drivers/gpu/drm/msm/dsi/dsi_cfg.h | 12 +
drivers/gpu/drm/msm/dsi/dsi_host.c | 355 ++++++++++++++++-------------
4 files changed, 268 insertions(+), 171 deletions(-)
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [relevance 14%]
* [PATCH v4 1/3] drm/msm/dsi: add dsi host helper functions support
2018-05-29 14:20 14% [PATCH v4 0/3] Cleanup excessive DSI host controller version checks Sibi Sankar
@ 2018-05-29 14:20 20% ` Sibi Sankar
2018-05-29 14:20 13% ` [PATCH v4 2/3] drm/msm/dsi: add implementation for helper functions Sibi Sankar
2018-05-29 14:20 12% ` [PATCH v4 3/3] drm/msm/dsi: replace version checks with " Sibi Sankar
2 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2018-05-29 14:20 UTC (permalink / raw)
To: architt, robdclark, jcrouse
Cc: dri-devel, linux-arm-msm, linux-kernel, Sibi Sankar
Add dsi host helper functions support for DSI v2 and DSI 6G 1.x
controllers that are under version checks
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
drivers/gpu/drm/msm/dsi/dsi.h | 1 +
drivers/gpu/drm/msm/dsi/dsi_cfg.h | 12 ++++++++++++
2 files changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
index 70d9a9a47acd..80be83e8fdec 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.h
@@ -149,6 +149,7 @@ static inline int msm_dsi_pll_set_usecase(struct msm_dsi_pll *pll,
#endif
/* dsi host */
+struct msm_dsi_host;
int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host,
const struct mipi_dsi_msg *msg);
void msm_dsi_host_xfer_restore(struct mipi_dsi_host *host,
diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
index 9cfdcf1c95d5..a795a062b779 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h
+++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
@@ -40,10 +40,22 @@ struct msm_dsi_config {
const int num_dsi;
};
+struct msm_dsi_host_cfg_ops {
+ int (*link_clk_enable)(struct msm_dsi_host *msm_host);
+ void (*link_clk_disable)(struct msm_dsi_host *msm_host);
+ int (*clk_init_ver)(struct msm_dsi_host *msm_host);
+ int (*tx_buf_alloc)(struct msm_dsi_host *msm_host, int size);
+ void* (*tx_buf_get)(struct msm_dsi_host *msm_host);
+ void (*tx_buf_put)(struct msm_dsi_host *msm_host);
+ int (*dma_base_get)(struct msm_dsi_host *msm_host, uint64_t *iova);
+ int (*calc_clk_rate)(struct msm_dsi_host *msm_host);
+};
+
struct msm_dsi_cfg_handler {
u32 major;
u32 minor;
const struct msm_dsi_config *cfg;
+ const struct msm_dsi_host_cfg_ops *ops;
};
const struct msm_dsi_cfg_handler *msm_dsi_cfg_get(u32 major, u32 minor);
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 20%]
* [PATCH v4 2/3] drm/msm/dsi: add implementation for helper functions
2018-05-29 14:20 14% [PATCH v4 0/3] Cleanup excessive DSI host controller version checks Sibi Sankar
2018-05-29 14:20 20% ` [PATCH v4 1/3] drm/msm/dsi: add dsi host helper functions support Sibi Sankar
@ 2018-05-29 14:20 13% ` Sibi Sankar
2018-05-29 14:20 12% ` [PATCH v4 3/3] drm/msm/dsi: replace version checks with " Sibi Sankar
2 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2018-05-29 14:20 UTC (permalink / raw)
To: architt, robdclark, jcrouse
Cc: dri-devel, linux-arm-msm, linux-kernel, Sibi Sankar
Add dsi host helper function implementation for DSI v2
DSI 6G 1.x and DSI 6G v2.0+ controllers
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
drivers/gpu/drm/msm/dsi/dsi.h | 15 ++
drivers/gpu/drm/msm/dsi/dsi_cfg.c | 56 ++++++--
drivers/gpu/drm/msm/dsi/dsi_host.c | 218 ++++++++++++++++++++++++++++-
3 files changed, 278 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
index 80be83e8fdec..dfa049d876bd 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.h
@@ -183,6 +183,21 @@ int msm_dsi_host_modeset_init(struct mipi_dsi_host *host,
int msm_dsi_host_init(struct msm_dsi *msm_dsi);
int msm_dsi_runtime_suspend(struct device *dev);
int msm_dsi_runtime_resume(struct device *dev);
+int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host);
+int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host);
+void dsi_link_clk_disable_6g(struct msm_dsi_host *msm_host);
+void dsi_link_clk_disable_v2(struct msm_dsi_host *msm_host);
+int dsi_tx_buf_alloc_6g(struct msm_dsi_host *msm_host, int size);
+int dsi_tx_buf_alloc_v2(struct msm_dsi_host *msm_host, int size);
+void *dsi_tx_buf_get_6g(struct msm_dsi_host *msm_host);
+void *dsi_tx_buf_get_v2(struct msm_dsi_host *msm_host);
+void dsi_tx_buf_put_6g(struct msm_dsi_host *msm_host);
+int dsi_dma_base_get_6g(struct msm_dsi_host *msm_host, uint64_t *iova);
+int dsi_dma_base_get_v2(struct msm_dsi_host *msm_host, uint64_t *iova);
+int dsi_clk_init_v2(struct msm_dsi_host *msm_host);
+int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host);
+int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host);
+int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host);
/* dsi phy */
struct msm_dsi_phy;
diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
index 0327bb54b01b..dcdfb1bb54f9 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
@@ -136,20 +136,58 @@ static const struct msm_dsi_config sdm845_dsi_cfg = {
.num_dsi = 2,
};
+const static struct msm_dsi_host_cfg_ops msm_dsi_v2_host_ops = {
+ .link_clk_enable = dsi_link_clk_enable_v2,
+ .link_clk_disable = dsi_link_clk_disable_v2,
+ .clk_init_ver = dsi_clk_init_v2,
+ .tx_buf_alloc = dsi_tx_buf_alloc_v2,
+ .tx_buf_get = dsi_tx_buf_get_v2,
+ .tx_buf_put = NULL,
+ .dma_base_get = dsi_dma_base_get_v2,
+ .calc_clk_rate = dsi_calc_clk_rate_v2,
+};
+
+const static struct msm_dsi_host_cfg_ops msm_dsi_6g_host_ops = {
+ .link_clk_enable = dsi_link_clk_enable_6g,
+ .link_clk_disable = dsi_link_clk_disable_6g,
+ .clk_init_ver = NULL,
+ .tx_buf_alloc = dsi_tx_buf_alloc_6g,
+ .tx_buf_get = dsi_tx_buf_get_6g,
+ .tx_buf_put = dsi_tx_buf_put_6g,
+ .dma_base_get = dsi_dma_base_get_6g,
+ .calc_clk_rate = dsi_calc_clk_rate_6g,
+};
+
+const static struct msm_dsi_host_cfg_ops msm_dsi_6g_v2_host_ops = {
+ .link_clk_enable = dsi_link_clk_enable_6g,
+ .link_clk_disable = dsi_link_clk_disable_6g,
+ .clk_init_ver = dsi_clk_init_6g_v2,
+ .tx_buf_alloc = dsi_tx_buf_alloc_6g,
+ .tx_buf_get = dsi_tx_buf_get_6g,
+ .tx_buf_put = dsi_tx_buf_put_6g,
+ .dma_base_get = dsi_dma_base_get_6g,
+ .calc_clk_rate = dsi_calc_clk_rate_6g,
+};
+
static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = {
- {MSM_DSI_VER_MAJOR_V2, MSM_DSI_V2_VER_MINOR_8064, &apq8064_dsi_cfg},
+ {MSM_DSI_VER_MAJOR_V2, MSM_DSI_V2_VER_MINOR_8064,
+ &apq8064_dsi_cfg, &msm_dsi_v2_host_ops},
{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_0,
- &msm8974_apq8084_dsi_cfg},
+ &msm8974_apq8084_dsi_cfg, &msm_dsi_6g_host_ops},
{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_1,
- &msm8974_apq8084_dsi_cfg},
+ &msm8974_apq8084_dsi_cfg, &msm_dsi_6g_host_ops},
{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_1_1,
- &msm8974_apq8084_dsi_cfg},
+ &msm8974_apq8084_dsi_cfg, &msm_dsi_6g_host_ops},
{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_2,
- &msm8974_apq8084_dsi_cfg},
- {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_3, &msm8994_dsi_cfg},
- {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_3_1, &msm8916_dsi_cfg},
- {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_4_1, &msm8996_dsi_cfg},
- {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_2_1, &sdm845_dsi_cfg},
+ &msm8974_apq8084_dsi_cfg, &msm_dsi_6g_host_ops},
+ {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_3,
+ &msm8994_dsi_cfg, &msm_dsi_6g_host_ops},
+ {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_3_1,
+ &msm8916_dsi_cfg, &msm_dsi_6g_host_ops},
+ {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_4_1,
+ &msm8996_dsi_cfg, &msm_dsi_6g_host_ops},
+ {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_2_1,
+ &sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops},
};
const struct msm_dsi_cfg_handler *msm_dsi_cfg_get(u32 major, u32 minor)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
index b916f464f4ec..1f42c891142f 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -332,6 +332,54 @@ static int dsi_regulator_init(struct msm_dsi_host *msm_host)
return 0;
}
+int dsi_clk_init_v2(struct msm_dsi_host *msm_host)
+{
+ struct platform_device *pdev = msm_host->pdev;
+ int ret = 0;
+
+ msm_host->src_clk = msm_clk_get(pdev, "src");
+
+ if (IS_ERR(msm_host->src_clk)) {
+ ret = PTR_ERR(msm_host->src_clk);
+ pr_err("%s: can't find src clock. ret=%d\n",
+ __func__, ret);
+ msm_host->src_clk = NULL;
+ return ret;
+ }
+
+ msm_host->esc_clk_src = clk_get_parent(msm_host->esc_clk);
+ if (!msm_host->esc_clk_src) {
+ ret = -ENODEV;
+ pr_err("%s: can't get esc clock parent. ret=%d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ msm_host->dsi_clk_src = clk_get_parent(msm_host->src_clk);
+ if (!msm_host->dsi_clk_src) {
+ ret = -ENODEV;
+ pr_err("%s: can't get src clock parent. ret=%d\n",
+ __func__, ret);
+ }
+
+ return ret;
+}
+
+int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host)
+{
+ struct platform_device *pdev = msm_host->pdev;
+ int ret = 0;
+
+ msm_host->byte_intf_clk = msm_clk_get(pdev, "byte_intf");
+ if (IS_ERR(msm_host->byte_intf_clk)) {
+ ret = PTR_ERR(msm_host->byte_intf_clk);
+ pr_err("%s: can't find byte_intf clock. ret=%d\n",
+ __func__, ret);
+ }
+
+ return ret;
+}
+
static int dsi_clk_init(struct msm_dsi_host *msm_host)
{
struct platform_device *pdev = msm_host->pdev;
@@ -498,7 +546,7 @@ int msm_dsi_runtime_resume(struct device *dev)
return dsi_bus_clk_enable(msm_host);
}
-static int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host)
+int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host)
{
int ret;
@@ -566,7 +614,7 @@ static int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host)
return ret;
}
-static int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host)
+int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host)
{
int ret;
@@ -644,6 +692,23 @@ static int dsi_link_clk_enable(struct msm_dsi_host *msm_host)
return dsi_link_clk_enable_v2(msm_host);
}
+void dsi_link_clk_disable_6g(struct msm_dsi_host *msm_host)
+{
+ clk_disable_unprepare(msm_host->esc_clk);
+ clk_disable_unprepare(msm_host->pixel_clk);
+ if (msm_host->byte_intf_clk)
+ clk_disable_unprepare(msm_host->byte_intf_clk);
+ clk_disable_unprepare(msm_host->byte_clk);
+}
+
+void dsi_link_clk_disable_v2(struct msm_dsi_host *msm_host)
+{
+ clk_disable_unprepare(msm_host->pixel_clk);
+ clk_disable_unprepare(msm_host->src_clk);
+ clk_disable_unprepare(msm_host->esc_clk);
+ clk_disable_unprepare(msm_host->byte_clk);
+}
+
static void dsi_link_clk_disable(struct msm_dsi_host *msm_host)
{
const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
@@ -662,6 +727,84 @@ static void dsi_link_clk_disable(struct msm_dsi_host *msm_host)
}
}
+int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host)
+{
+ struct drm_display_mode *mode = msm_host->mode;
+ u8 lanes = msm_host->lanes;
+ u32 bpp = dsi_get_bpp(msm_host->format);
+ u32 pclk_rate;
+
+ pclk_rate = mode->clock * 1000;
+ if (lanes > 0) {
+ msm_host->byte_clk_rate = (pclk_rate * bpp) / (8 * lanes);
+ } else {
+ pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__);
+ msm_host->byte_clk_rate = (pclk_rate * bpp) / 8;
+ }
+
+ DBG("pclk=%d, bclk=%d", pclk_rate, msm_host->byte_clk_rate);
+
+ msm_host->esc_clk_rate = clk_get_rate(msm_host->esc_clk);
+
+ return 0;
+}
+
+int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host)
+{
+ struct drm_display_mode *mode = msm_host->mode;
+ u8 lanes = msm_host->lanes;
+ u32 bpp = dsi_get_bpp(msm_host->format);
+ u32 pclk_rate;
+ unsigned int esc_mhz, esc_div;
+ unsigned long byte_mhz;
+
+ pclk_rate = mode->clock * 1000;
+ if (lanes > 0) {
+ msm_host->byte_clk_rate = (pclk_rate * bpp) / (8 * lanes);
+ } else {
+ pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__);
+ msm_host->byte_clk_rate = (pclk_rate * bpp) / 8;
+ }
+
+ DBG("pclk=%d, bclk=%d", pclk_rate, msm_host->byte_clk_rate);
+
+ msm_host->src_clk_rate = (pclk_rate * bpp) / 8;
+
+ /*
+ * esc clock is byte clock followed by a 4 bit divider,
+ * we need to find an escape clock frequency within the
+ * mipi DSI spec range within the maximum divider limit
+ * We iterate here between an escape clock frequencey
+ * between 20 Mhz to 5 Mhz and pick up the first one
+ * that can be supported by our divider
+ */
+
+ byte_mhz = msm_host->byte_clk_rate / 1000000;
+
+ for (esc_mhz = 20; esc_mhz >= 5; esc_mhz--) {
+ esc_div = DIV_ROUND_UP(byte_mhz, esc_mhz);
+
+ /*
+ * TODO: Ideally, we shouldn't know what sort of divider
+ * is available in mmss_cc, we're just assuming that
+ * it'll always be a 4 bit divider. Need to come up with
+ * a better way here.
+ */
+ if (esc_div >= 1 && esc_div <= 16)
+ break;
+ }
+
+ if (esc_mhz < 5)
+ return -EINVAL;
+
+ msm_host->esc_clk_rate = msm_host->byte_clk_rate / esc_div;
+
+ DBG("esc=%d, src=%d", msm_host->esc_clk_rate,
+ msm_host->src_clk_rate);
+
+ return 0;
+}
+
static int dsi_calc_clk_rate(struct msm_dsi_host *msm_host)
{
struct drm_display_mode *mode = msm_host->mode;
@@ -1015,6 +1158,41 @@ static void dsi_wait4video_eng_busy(struct msm_dsi_host *msm_host)
}
}
+int dsi_tx_buf_alloc_6g(struct msm_dsi_host *msm_host, int size)
+{
+ struct drm_device *dev = msm_host->dev;
+ struct msm_drm_private *priv = dev->dev_private;
+ uint64_t iova;
+ u8 *data;
+
+ data = msm_gem_kernel_new(dev, size, MSM_BO_UNCACHED,
+ priv->kms->aspace,
+ &msm_host->tx_gem_obj, &iova);
+
+ if (IS_ERR(data)) {
+ msm_host->tx_gem_obj = NULL;
+ return PTR_ERR(data);
+ }
+
+ msm_host->tx_size = msm_host->tx_gem_obj->size;
+
+ return 0;
+}
+
+int dsi_tx_buf_alloc_v2(struct msm_dsi_host *msm_host, int size)
+{
+ struct drm_device *dev = msm_host->dev;
+
+ msm_host->tx_buf = dma_alloc_coherent(dev->dev, size,
+ &msm_host->tx_buf_paddr, GFP_KERNEL);
+ if (!msm_host->tx_buf)
+ return -ENOMEM;
+
+ msm_host->tx_size = size;
+
+ return 0;
+}
+
/* dsi_cmd */
static int dsi_tx_buf_alloc(struct msm_dsi_host *msm_host, int size)
{
@@ -1079,6 +1257,21 @@ static void dsi_tx_buf_free(struct msm_dsi_host *msm_host)
msm_host->tx_buf_paddr);
}
+void *dsi_tx_buf_get_6g(struct msm_dsi_host *msm_host)
+{
+ return msm_gem_get_vaddr(msm_host->tx_gem_obj);
+}
+
+void *dsi_tx_buf_get_v2(struct msm_dsi_host *msm_host)
+{
+ return msm_host->tx_buf;
+}
+
+void dsi_tx_buf_put_6g(struct msm_dsi_host *msm_host)
+{
+ msm_gem_put_vaddr(msm_host->tx_gem_obj);
+}
+
/*
* prepare cmd buffer to be txed
*/
@@ -1180,6 +1373,27 @@ static int dsi_long_read_resp(u8 *buf, const struct mipi_dsi_msg *msg)
return msg->rx_len;
}
+int dsi_dma_base_get_6g(struct msm_dsi_host *msm_host, uint64_t *dma_base)
+{
+ struct drm_device *dev = msm_host->dev;
+ struct msm_drm_private *priv = dev->dev_private;
+
+ if (!dma_base)
+ return -EINVAL;
+
+ return msm_gem_get_iova(msm_host->tx_gem_obj,
+ priv->kms->aspace, dma_base);
+}
+
+int dsi_dma_base_get_v2(struct msm_dsi_host *msm_host, uint64_t *dma_base)
+{
+ if (!dma_base)
+ return -EINVAL;
+
+ *dma_base = msm_host->tx_buf_paddr;
+ return 0;
+}
+
static int dsi_cmd_dma_tx(struct msm_dsi_host *msm_host, int len)
{
const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 13%]
* [PATCH v4 3/3] drm/msm/dsi: replace version checks with helper functions
2018-05-29 14:20 14% [PATCH v4 0/3] Cleanup excessive DSI host controller version checks Sibi Sankar
2018-05-29 14:20 20% ` [PATCH v4 1/3] drm/msm/dsi: add dsi host helper functions support Sibi Sankar
2018-05-29 14:20 13% ` [PATCH v4 2/3] drm/msm/dsi: add implementation for helper functions Sibi Sankar
@ 2018-05-29 14:20 12% ` Sibi Sankar
2 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2018-05-29 14:20 UTC (permalink / raw)
To: architt, robdclark, jcrouse
Cc: dri-devel, linux-arm-msm, linux-kernel, Sibi Sankar
Replace version checks with the helper functions bound to
cfg_handler for DSI v2, DSI 6G 1.x and DSI 6G v2.0+ controllers
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 241 ++++-------------------------
1 file changed, 29 insertions(+), 212 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 1f42c891142f..a351f2243ff8 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -427,19 +427,6 @@ static int dsi_clk_init(struct msm_dsi_host *msm_host)
goto exit;
}
- if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G &&
- cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V2_2_1) {
- msm_host->byte_intf_clk = msm_clk_get(pdev, "byte_intf");
- if (IS_ERR(msm_host->byte_intf_clk)) {
- ret = PTR_ERR(msm_host->byte_intf_clk);
- pr_err("%s: can't find byte_intf clock. ret=%d\n",
- __func__, ret);
- goto exit;
- }
- } else {
- msm_host->byte_intf_clk = NULL;
- }
-
msm_host->byte_clk_src = clk_get_parent(msm_host->byte_clk);
if (!msm_host->byte_clk_src) {
ret = -ENODEV;
@@ -454,31 +441,8 @@ static int dsi_clk_init(struct msm_dsi_host *msm_host)
goto exit;
}
- if (cfg_hnd->major == MSM_DSI_VER_MAJOR_V2) {
- msm_host->src_clk = msm_clk_get(pdev, "src");
- if (IS_ERR(msm_host->src_clk)) {
- ret = PTR_ERR(msm_host->src_clk);
- pr_err("%s: can't find src clock. ret=%d\n",
- __func__, ret);
- msm_host->src_clk = NULL;
- goto exit;
- }
-
- msm_host->esc_clk_src = clk_get_parent(msm_host->esc_clk);
- if (!msm_host->esc_clk_src) {
- ret = -ENODEV;
- pr_err("%s: can't get esc clock parent. ret=%d\n",
- __func__, ret);
- goto exit;
- }
-
- msm_host->dsi_clk_src = clk_get_parent(msm_host->src_clk);
- if (!msm_host->dsi_clk_src) {
- ret = -ENODEV;
- pr_err("%s: can't get src clock parent. ret=%d\n",
- __func__, ret);
- }
- }
+ if (cfg_hnd->ops->clk_init_ver)
+ ret = cfg_hnd->ops->clk_init_ver(msm_host);
exit:
return ret;
}
@@ -682,16 +646,6 @@ int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host)
return ret;
}
-static int dsi_link_clk_enable(struct msm_dsi_host *msm_host)
-{
- const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
-
- if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G)
- return dsi_link_clk_enable_6g(msm_host);
- else
- return dsi_link_clk_enable_v2(msm_host);
-}
-
void dsi_link_clk_disable_6g(struct msm_dsi_host *msm_host)
{
clk_disable_unprepare(msm_host->esc_clk);
@@ -709,24 +663,6 @@ void dsi_link_clk_disable_v2(struct msm_dsi_host *msm_host)
clk_disable_unprepare(msm_host->byte_clk);
}
-static void dsi_link_clk_disable(struct msm_dsi_host *msm_host)
-{
- const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
-
- if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) {
- clk_disable_unprepare(msm_host->esc_clk);
- clk_disable_unprepare(msm_host->pixel_clk);
- if (msm_host->byte_intf_clk)
- clk_disable_unprepare(msm_host->byte_intf_clk);
- clk_disable_unprepare(msm_host->byte_clk);
- } else {
- clk_disable_unprepare(msm_host->pixel_clk);
- clk_disable_unprepare(msm_host->src_clk);
- clk_disable_unprepare(msm_host->esc_clk);
- clk_disable_unprepare(msm_host->byte_clk);
- }
-}
-
int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host)
{
struct drm_display_mode *mode = msm_host->mode;
@@ -805,73 +741,6 @@ int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host)
return 0;
}
-static int dsi_calc_clk_rate(struct msm_dsi_host *msm_host)
-{
- struct drm_display_mode *mode = msm_host->mode;
- const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
- u8 lanes = msm_host->lanes;
- u32 bpp = dsi_get_bpp(msm_host->format);
- u32 pclk_rate;
-
- if (!mode) {
- pr_err("%s: mode not set\n", __func__);
- return -EINVAL;
- }
-
- pclk_rate = mode->clock * 1000;
- if (lanes > 0) {
- msm_host->byte_clk_rate = (pclk_rate * bpp) / (8 * lanes);
- } else {
- pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__);
- msm_host->byte_clk_rate = (pclk_rate * bpp) / 8;
- }
-
- DBG("pclk=%d, bclk=%d", pclk_rate, msm_host->byte_clk_rate);
-
- msm_host->esc_clk_rate = clk_get_rate(msm_host->esc_clk);
-
- if (cfg_hnd->major == MSM_DSI_VER_MAJOR_V2) {
- unsigned int esc_mhz, esc_div;
- unsigned long byte_mhz;
-
- msm_host->src_clk_rate = (pclk_rate * bpp) / 8;
-
- /*
- * esc clock is byte clock followed by a 4 bit divider,
- * we need to find an escape clock frequency within the
- * mipi DSI spec range within the maximum divider limit
- * We iterate here between an escape clock frequencey
- * between 20 Mhz to 5 Mhz and pick up the first one
- * that can be supported by our divider
- */
-
- byte_mhz = msm_host->byte_clk_rate / 1000000;
-
- for (esc_mhz = 20; esc_mhz >= 5; esc_mhz--) {
- esc_div = DIV_ROUND_UP(byte_mhz, esc_mhz);
-
- /*
- * TODO: Ideally, we shouldn't know what sort of divider
- * is available in mmss_cc, we're just assuming that
- * it'll always be a 4 bit divider. Need to come up with
- * a better way here.
- */
- if (esc_div >= 1 && esc_div <= 16)
- break;
- }
-
- if (esc_mhz < 5)
- return -EINVAL;
-
- msm_host->esc_clk_rate = msm_host->byte_clk_rate / esc_div;
-
- DBG("esc=%d, src=%d", msm_host->esc_clk_rate,
- msm_host->src_clk_rate);
- }
-
- return 0;
-}
-
static void dsi_intr_ctrl(struct msm_dsi_host *msm_host, u32 mask, int enable)
{
u32 intr;
@@ -1193,54 +1062,6 @@ int dsi_tx_buf_alloc_v2(struct msm_dsi_host *msm_host, int size)
return 0;
}
-/* dsi_cmd */
-static int dsi_tx_buf_alloc(struct msm_dsi_host *msm_host, int size)
-{
- struct drm_device *dev = msm_host->dev;
- struct msm_drm_private *priv = dev->dev_private;
- const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
- int ret;
- uint64_t iova;
-
- if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) {
- msm_host->tx_gem_obj = msm_gem_new(dev, size, MSM_BO_UNCACHED);
- if (IS_ERR(msm_host->tx_gem_obj)) {
- ret = PTR_ERR(msm_host->tx_gem_obj);
- pr_err("%s: failed to allocate gem, %d\n",
- __func__, ret);
- msm_host->tx_gem_obj = NULL;
- return ret;
- }
-
- ret = msm_gem_get_iova(msm_host->tx_gem_obj,
- priv->kms->aspace, &iova);
- if (ret) {
- pr_err("%s: failed to get iova, %d\n", __func__, ret);
- return ret;
- }
-
- if (iova & 0x07) {
- pr_err("%s: buf NOT 8 bytes aligned\n", __func__);
- return -EINVAL;
- }
-
- msm_host->tx_size = msm_host->tx_gem_obj->size;
- } else {
- msm_host->tx_buf = dma_alloc_coherent(dev->dev, size,
- &msm_host->tx_buf_paddr, GFP_KERNEL);
- if (!msm_host->tx_buf) {
- ret = -ENOMEM;
- pr_err("%s: failed to allocate tx buf, %d\n",
- __func__, ret);
- return ret;
- }
-
- msm_host->tx_size = size;
- }
-
- return 0;
-}
-
static void dsi_tx_buf_free(struct msm_dsi_host *msm_host)
{
struct drm_device *dev = msm_host->dev;
@@ -1296,15 +1117,11 @@ static int dsi_cmd_dma_add(struct msm_dsi_host *msm_host,
return -EINVAL;
}
- if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) {
- data = msm_gem_get_vaddr(msm_host->tx_gem_obj);
- if (IS_ERR(data)) {
- ret = PTR_ERR(data);
- pr_err("%s: get vaddr failed, %d\n", __func__, ret);
- return ret;
- }
- } else {
- data = msm_host->tx_buf;
+ data = cfg_hnd->ops->tx_buf_get(msm_host);
+ if (IS_ERR(data)) {
+ ret = PTR_ERR(data);
+ pr_err("%s: get vaddr failed, %d\n", __func__, ret);
+ return ret;
}
/* MSM specific command format in memory */
@@ -1325,8 +1142,8 @@ static int dsi_cmd_dma_add(struct msm_dsi_host *msm_host,
if (packet.size < len)
memset(data + packet.size, 0xff, len - packet.size);
- if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G)
- msm_gem_put_vaddr(msm_host->tx_gem_obj);
+ if (cfg_hnd->ops->tx_buf_put)
+ cfg_hnd->ops->tx_buf_put(msm_host);
return len;
}
@@ -1397,21 +1214,14 @@ int dsi_dma_base_get_v2(struct msm_dsi_host *msm_host, uint64_t *dma_base)
static int dsi_cmd_dma_tx(struct msm_dsi_host *msm_host, int len)
{
const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
- struct drm_device *dev = msm_host->dev;
- struct msm_drm_private *priv = dev->dev_private;
int ret;
uint64_t dma_base;
bool triggered;
- if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) {
- ret = msm_gem_get_iova(msm_host->tx_gem_obj,
- priv->kms->aspace, &dma_base);
- if (ret) {
- pr_err("%s: failed to get iova: %d\n", __func__, ret);
- return ret;
- }
- } else {
- dma_base = msm_host->tx_buf_paddr;
+ ret = cfg_hnd->ops->dma_base_get(msm_host, &dma_base);
+ if (ret) {
+ pr_err("%s: failed to get iova: %d\n", __func__, ret);
+ return ret;
}
reinit_completion(&msm_host->dma_comp);
@@ -2049,6 +1859,7 @@ int msm_dsi_host_modeset_init(struct mipi_dsi_host *host,
struct drm_device *dev)
{
struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
+ const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
struct platform_device *pdev = msm_host->pdev;
int ret;
@@ -2069,7 +1880,7 @@ int msm_dsi_host_modeset_init(struct mipi_dsi_host *host,
}
msm_host->dev = dev;
- ret = dsi_tx_buf_alloc(msm_host, SZ_4K);
+ ret = cfg_hnd->ops->tx_buf_alloc(msm_host, SZ_4K);
if (ret) {
pr_err("%s: alloc tx gem obj failed, %d\n", __func__, ret);
return ret;
@@ -2127,6 +1938,7 @@ int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host,
const struct mipi_dsi_msg *msg)
{
struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
+ const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
/* TODO: make sure dsi_cmd_mdp is idle.
* Since DSI6G v1.2.0, we can set DSI_TRIG_CTRL.BLOCK_DMA_WITHIN_FRAME
@@ -2139,7 +1951,7 @@ int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host,
* mdp clock need to be enabled to receive dsi interrupt
*/
pm_runtime_get_sync(&msm_host->pdev->dev);
- dsi_link_clk_enable(msm_host);
+ cfg_hnd->ops->link_clk_enable(msm_host);
/* TODO: vote for bus bandwidth */
@@ -2160,6 +1972,7 @@ void msm_dsi_host_xfer_restore(struct mipi_dsi_host *host,
const struct mipi_dsi_msg *msg)
{
struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
+ const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 0);
dsi_write(msm_host, REG_DSI_CTRL, msm_host->dma_cmd_ctrl_restore);
@@ -2169,7 +1982,7 @@ void msm_dsi_host_xfer_restore(struct mipi_dsi_host *host,
/* TODO: unvote for bus bandwidth */
- dsi_link_clk_disable(msm_host);
+ cfg_hnd->ops->link_clk_disable(msm_host);
pm_runtime_put_autosuspend(&msm_host->pdev->dev);
}
@@ -2333,7 +2146,6 @@ int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host,
struct msm_dsi_pll *src_pll)
{
struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
- const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
struct clk *byte_clk_provider, *pixel_clk_provider;
int ret;
@@ -2359,14 +2171,16 @@ int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host,
goto exit;
}
- if (cfg_hnd->major == MSM_DSI_VER_MAJOR_V2) {
+ if (msm_host->dsi_clk_src) {
ret = clk_set_parent(msm_host->dsi_clk_src, pixel_clk_provider);
if (ret) {
pr_err("%s: can't set parent to dsi_clk_src. ret=%d\n",
__func__, ret);
goto exit;
}
+ }
+ if (msm_host->esc_clk_src) {
ret = clk_set_parent(msm_host->esc_clk_src, byte_clk_provider);
if (ret) {
pr_err("%s: can't set parent to esc_clk_src. ret=%d\n",
@@ -2396,9 +2210,10 @@ void msm_dsi_host_get_phy_clk_req(struct mipi_dsi_host *host,
struct msm_dsi_phy_clk_request *clk_req)
{
struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
+ const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
int ret;
- ret = dsi_calc_clk_rate(msm_host);
+ ret = cfg_hnd->ops->calc_clk_rate(msm_host);
if (ret) {
pr_err("%s: unable to calc clk rate, %d\n", __func__, ret);
return;
@@ -2463,6 +2278,7 @@ int msm_dsi_host_power_on(struct mipi_dsi_host *host,
struct msm_dsi_phy_shared_timings *phy_shared_timings)
{
struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
+ const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
int ret = 0;
mutex_lock(&msm_host->dev_mutex);
@@ -2481,7 +2297,7 @@ int msm_dsi_host_power_on(struct mipi_dsi_host *host,
}
pm_runtime_get_sync(&msm_host->pdev->dev);
- ret = dsi_link_clk_enable(msm_host);
+ ret = cfg_hnd->ops->link_clk_enable(msm_host);
if (ret) {
pr_err("%s: failed to enable link clocks. ret=%d\n",
__func__, ret);
@@ -2508,7 +2324,7 @@ int msm_dsi_host_power_on(struct mipi_dsi_host *host,
return 0;
fail_disable_clk:
- dsi_link_clk_disable(msm_host);
+ cfg_hnd->ops->link_clk_disable(msm_host);
pm_runtime_put_autosuspend(&msm_host->pdev->dev);
fail_disable_reg:
dsi_host_regulator_disable(msm_host);
@@ -2520,6 +2336,7 @@ int msm_dsi_host_power_on(struct mipi_dsi_host *host,
int msm_dsi_host_power_off(struct mipi_dsi_host *host)
{
struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
+ const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
mutex_lock(&msm_host->dev_mutex);
if (!msm_host->power_on) {
@@ -2534,7 +2351,7 @@ int msm_dsi_host_power_off(struct mipi_dsi_host *host)
pinctrl_pm_select_sleep_state(&msm_host->pdev->dev);
- dsi_link_clk_disable(msm_host);
+ cfg_hnd->ops->link_clk_disable(msm_host);
pm_runtime_put_autosuspend(&msm_host->pdev->dev);
dsi_host_regulator_disable(msm_host);
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 12%]
* Re: [PATCH v5 5/8] dt-bindings: remoteproc: Add Q6v5 Modem PIL binding for SDM845
2018-05-22 15:56 0% ` Rob Herring
@ 2018-05-29 14:37 6% ` Sibi S
2018-05-29 15:45 6% ` Rob Herring
0 siblings, 1 reply; 200+ results
From: Sibi S @ 2018-05-29 14:37 UTC (permalink / raw)
To: Rob Herring
Cc: bjorn.andersson, p.zabel, linux-remoteproc, linux-kernel,
devicetree, georgi.djakov, jassisinghbrar, ohad, mark.rutland,
kyan, sricharan, akdwived, linux-arm-msm, tsoni
Hi Rob,
Will send it out again.
On 05/22/2018 09:26 PM, Rob Herring wrote:
> On Mon, May 21, 2018 at 10:57:11PM +0530, Sibi Sankar wrote:
>> Add new compatible string for Qualcomm SDM845 SoCs
>>
>> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
>> ---
>> Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt | 1 +
>> 1 file changed, 1 insertion(+)
>
> Please add acks/reviewed-bys when posting new versions.
>
> Rob
>
--
Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc, is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [relevance 6%]
* [PATCH v5 5/8] dt-bindings: remoteproc: Add Q6v5 Modem PIL binding for SDM845
@ 2018-05-29 14:41 21% Sibi Sankar
0 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2018-05-29 14:41 UTC (permalink / raw)
To: robh+dt
Cc: bjorn.andersson, linux-remoteproc, linux-kernel, devicetree,
p.zabel, ohad, mark.rutland, kyan, sricharan, akdwived,
linux-arm-msm, tsoni, Sibi Sankar
Add new compatible string for Qualcomm SDM845 SoCs
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
index 00d3d58a102f..d90182425450 100644
--- a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
+++ b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
@@ -11,6 +11,7 @@ on the Qualcomm Hexagon core.
"qcom,msm8916-mss-pil",
"qcom,msm8974-mss-pil"
"qcom,msm8996-mss-pil"
+ "qcom,sdm845-mss-pil"
- reg:
Usage: required
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 21%]
* Re: [PATCH v5 5/8] dt-bindings: remoteproc: Add Q6v5 Modem PIL binding for SDM845
2018-05-29 14:37 6% ` Sibi S
@ 2018-05-29 15:45 6% ` Rob Herring
0 siblings, 0 replies; 200+ results
From: Rob Herring @ 2018-05-29 15:45 UTC (permalink / raw)
To: Sibi S
Cc: Bjorn Andersson, Philipp Zabel,
open list:REMOTE PROCESSOR (REMOTEPROC) SUBSYSTEM, linux-kernel,
devicetree, Georgi Djakov, Jassi Brar, Ohad Ben-Cohen,
Mark Rutland, Kyle Yan, Sricharan, Avaneesh Kumar Dwivedi,
linux-arm-msm, Trilok Soni
On Tue, May 29, 2018 at 9:37 AM, Sibi S <sibis@codeaurora.org> wrote:
> Hi Rob,
> Will send it out again.
Please don't top post on mail lists.
You don't need to resend *just* to add tags. A new version just needs
them because maintainers aren't going to go search through your prior
versions for you to add them. But my mentioning it should be enough.
Rob
^ permalink raw reply [relevance 6%]
* Re: [RFC PATCH 2/5] remoteproc: q6v5: Extract common resource handling
@ 2018-06-01 15:18 6% ` Sibi S
0 siblings, 0 replies; 200+ results
From: Sibi S @ 2018-06-01 15:18 UTC (permalink / raw)
To: Sricharan R, Bjorn Andersson, Ohad Ben-Cohen, Rohit kumar
Cc: Andy Gross, linux-kernel, linux-remoteproc, linux-arm-msm
Hi Sricharan,
On 06/01/2018 11:46 AM, Sricharan R wrote:
> Hi Bjorn,
> Thanks for this much needed consolidation.
>
> On 5/23/2018 10:50 AM, Bjorn Andersson wrote:
>> Shared between all Hexagon V5 based remoteprocs is the handling of the 5
>> interrupts and the SMP2P stop request, so break this out into a separate
>> function in order to allow these drivers to be cleaned up.
>>
>> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
>> ---
>> drivers/remoteproc/Kconfig | 5 +
>> drivers/remoteproc/Makefile | 1 +
>> drivers/remoteproc/qcom_q6v5.c | 243 +++++++++++++++++++++++++++++++++
>> drivers/remoteproc/qcom_q6v5.h | 46 +++++++
>> 4 files changed, 295 insertions(+)
>> create mode 100644 drivers/remoteproc/qcom_q6v5.c
>> create mode 100644 drivers/remoteproc/qcom_q6v5.h
>>
>> diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig
>> index cd1c168fd188..63b79ea91a21 100644
>> --- a/drivers/remoteproc/Kconfig
>> +++ b/drivers/remoteproc/Kconfig
>> @@ -102,6 +102,11 @@ config QCOM_ADSP_PIL
>> config QCOM_RPROC_COMMON
>> tristate
>>
>> +config QCOM_Q6V5_COMMON
>> + tristate
>> + depends on ARCH_QCOM
>> + depends on QCOM_SMEM
>> +
>> config QCOM_Q6V5_PIL
>> tristate "Qualcomm Hexagon V5 Peripherial Image Loader"
>> depends on OF && ARCH_QCOM
>> diff --git a/drivers/remoteproc/Makefile b/drivers/remoteproc/Makefile
>> index 02627ede8d4a..5dd0249cf76a 100644
>> --- a/drivers/remoteproc/Makefile
>> +++ b/drivers/remoteproc/Makefile
>> @@ -16,6 +16,7 @@ obj-$(CONFIG_DA8XX_REMOTEPROC) += da8xx_remoteproc.o
>> obj-$(CONFIG_KEYSTONE_REMOTEPROC) += keystone_remoteproc.o
>> obj-$(CONFIG_QCOM_ADSP_PIL) += qcom_adsp_pil.o
>> obj-$(CONFIG_QCOM_RPROC_COMMON) += qcom_common.o
>> +obj-$(CONFIG_QCOM_Q6V5_COMMON) += qcom_q6v5.o
>> obj-$(CONFIG_QCOM_Q6V5_PIL) += qcom_q6v5_pil.o
>> obj-$(CONFIG_QCOM_SYSMON) += qcom_sysmon.o
>> obj-$(CONFIG_QCOM_WCNSS_PIL) += qcom_wcnss_pil.o
>> diff --git a/drivers/remoteproc/qcom_q6v5.c b/drivers/remoteproc/qcom_q6v5.c
>> new file mode 100644
>> index 000000000000..9076537a1671
>> --- /dev/null
>> +++ b/drivers/remoteproc/qcom_q6v5.c
>> @@ -0,0 +1,243 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Qualcomm Peripheral Image Loader for Q6V5 WCSS
>> + *
>
> Probably just Q6V5, QCSS not needed.
>
>> + * Copyright (C) 2016-2018 Linaro Ltd.
>> + * Copyright (C) 2014 Sony Mobile Communications AB
>> + * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
>> + */
>> +#include <linux/kernel.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/interrupt.h>
>> +#include <linux/soc/qcom/smem.h>
>> +#include <linux/soc/qcom/smem_state.h>
>> +#include <linux/remoteproc.h>
>> +#include "qcom_q6v5.h"
>> +
>> +/**
>> + * qcom_q6v5_prepare() - reinitialize the qcom_q6v5 context before start
>> + * @q6v5: reference to qcom_q6v5 context to be reinitialized
>> + *
>> + * Return: 0 on success, negative errno on failure
>> + */
>> +int qcom_q6v5_prepare(struct qcom_q6v5 *q6v5)
>> +{
>> + reinit_completion(&q6v5->start_done);
>> + reinit_completion(&q6v5->stop_done);
>> +
>> + q6v5->running = true;
>> + q6v5->handover_issued = false;
>> +
>> + enable_irq(q6v5->handover_irq);
>> +
>> + return 0;
>> +}
>> +
>> +/**
>> + * qcom_q6v5_unprepare() - unprepare the qcom_q6v5 context after stop
>> + * @q6v5: reference to qcom_q6v5 context to be unprepared
>> + *
>> + * Return: 0 on success, 1 if handover hasn't yet been called
>> + */
>> +int qcom_q6v5_unprepare(struct qcom_q6v5 *q6v5)
>> +{
>> + disable_irq(q6v5->handover_irq);
>> +
>> + return !q6v5->handover_issued;
>> +}
>> +
>> +static irqreturn_t q6v5_wdog_interrupt(int irq, void *data)
>> +{
>> + struct qcom_q6v5 *q6v5 = data;
>> + size_t len;
>> + char *msg;
>> +
>> + /* Sometimes the stop triggers a watchdog rather than a stop-ack */
>> + if (!q6v5->running) {
>> + complete(&q6v5->stop_done);
>> + return IRQ_HANDLED;
>> + }
>> +
>
> Does this change the behavior for adsp pil, which was unconditionally
> doing a rproc_report_crash before, but now checks for the running flag
> or probably this is the correct sequence ?
>
>> + msg = qcom_smem_get(QCOM_SMEM_HOST_ANY, q6v5->crash_reason, &len);
>> + if (!IS_ERR(msg) && len > 0 && msg[0])
>> + dev_err(q6v5->dev, "watchdog received: %s\n", msg);
>> + else
>> + dev_err(q6v5->dev, "watchdog without message\n");
>> +
>> + rproc_report_crash(q6v5->rproc, RPROC_FATAL_ERROR);
>> +
>
> Should be rproc_report_crash(q6v5->rproc, RPROC_WATCHDOG);
>
>> + return IRQ_HANDLED;
>> +}
>> +
>> +static irqreturn_t q6v5_fatal_interrupt(int irq, void *data)
>> +{
>> + struct qcom_q6v5 *q6v5 = data;
>> + size_t len;
>> + char *msg;
>> +
>> + msg = qcom_smem_get(QCOM_SMEM_HOST_ANY, q6v5->crash_reason, &len);
>> + if (!IS_ERR(msg) && len > 0 && msg[0])
>> + dev_err(q6v5->dev, "fatal error received: %s\n", msg);
>> + else
>> + dev_err(q6v5->dev, "fatal error without message\n");
>> +
>> + rproc_report_crash(q6v5->rproc, RPROC_FATAL_ERROR);
>> +
>> + return IRQ_HANDLED;
>> +}
>> +
>> +static irqreturn_t q6v5_ready_interrupt(int irq, void *data)
>> +{
>> + struct qcom_q6v5 *q6v5 = data;
>> +
>> + complete(&q6v5->start_done);
>> +
>> + return IRQ_HANDLED;
>> +}
>
> For adsp, previously start_done completion was done as a part of
> handover interrupt, now its done in ready. Does it mean that the
> entries in DT should be changed etc ?
ready interrupt has always been a part dt entry however a corresponding
interrupt handler was never registered. The trigger condition for
the handover interrupt in the remote processor seem to vary across SoCs
but we can always rely on the ready interrupt to declare the rproc
device is running.
>> +
>> +/**
>> + * qcom_q6v5_wait_for_start() - wait for remote processor start signal
>> + * @q6v5: reference to qcom_q6v5 context
>> + * @timeout: timeout to wait for the event, in jiffies
>> + *
>> + * qcom_q6v5_unprepare() should not be called when this function fails.
>> + *
>> + * Return: 0 on success, -ETIMEDOUT on timeout
>> + */
>> +int qcom_q6v5_wait_for_start(struct qcom_q6v5 *q6v5, int timeout)
>> +{
>> + int ret;
>> +
>> + ret = wait_for_completion_timeout(&q6v5->start_done, timeout);
>> + if (!ret)
>> + disable_irq(q6v5->handover_irq);
>> +
>> + return !ret ? -ETIMEDOUT : 0;
>> +}
>> +
>> +static irqreturn_t q6v5_handover_interrupt(int irq, void *data)
>> +{
>> + struct qcom_q6v5 *q6v5 = data;
>> +
>> + if (q6v5->handover)
>> + q6v5->handover(q6v5);
>> +
>> + q6v5->handover_issued = true;
>> +
>> + return IRQ_HANDLED;
>> +}
>> +
>> +static irqreturn_t q6v5_stop_interrupt(int irq, void *data)
>> +{
>> + struct qcom_q6v5 *q6v5 = data;
>> +
>> + complete(&q6v5->stop_done);
>> +
>> + return IRQ_HANDLED;
>> +}
>> +
>> +/**
>> + * qcom_q6v5_request_stop() - request the remote processor to stop
>> + * @q6v5: reference to qcom_q6v5 context
>> + *
>> + * Return: 0 on success, negative errno on failure
>> + */
>> +int qcom_q6v5_request_stop(struct qcom_q6v5 *q6v5)
>> +{
>> + int ret;
>> +
>> + q6v5->running = false;
>> +
>> + qcom_smem_state_update_bits(q6v5->state,
>> + BIT(q6v5->stop_bit), BIT(q6v5->stop_bit));
>> +
>> + ret = wait_for_completion_timeout(&q6v5->stop_done, 5 * HZ);
>> +
>> + qcom_smem_state_update_bits(q6v5->state, BIT(q6v5->stop_bit), 0);
>> +
>> + return ret == 0 ? -ETIMEDOUT : 0;
>> +}
>> +
>> +/**
>> + * qcom_q6v5_init() - initializer of the q6v5 common struct
>> + * @q6v5: handle to be initialized
>> + * @pdev: platform_device reference for acquiring resources
>> + * @rproc: associated remoteproc instance
>> + * @crash_reason: SMEM id for crash reason string, or 0 if none
>> + * @handover: function to be called when proxy resources should be released
>> + *
>> + * Return: 0 on success, negative errno on failure
>> + */
>> +int qcom_q6v5_init(struct qcom_q6v5 *q6v5, struct platform_device *pdev,
>> + struct rproc *rproc, int crash_reason,
>> + void (*handover)(struct qcom_q6v5 *q6v5))
>> +{
>> + int ret;
>> +
>> + q6v5->rproc = rproc;
>> + q6v5->dev = &pdev->dev;
>> + q6v5->crash_reason = crash_reason;
>> + q6v5->handover = handover;
>> +
>> + init_completion(&q6v5->start_done);
>> + init_completion(&q6v5->stop_done);
>> +
>> + q6v5->wdog_irq = platform_get_irq_byname(pdev, "wdog");
>> + ret = devm_request_threaded_irq(&pdev->dev, q6v5->wdog_irq,
>> + NULL, q6v5_wdog_interrupt,
>> + IRQF_TRIGGER_RISING | IRQF_ONESHOT,
>> + "q6v5 wdog", q6v5);
>> + if (ret) {
>> + dev_err(&pdev->dev, "failed to acquire wdog IRQ\n");
>> + return ret;
>> + }
>> +
>> + q6v5->fatal_irq = platform_get_irq_byname(pdev, "fatal");
>> + ret = devm_request_threaded_irq(&pdev->dev, q6v5->fatal_irq,
>> + NULL, q6v5_fatal_interrupt,
>> + IRQF_TRIGGER_RISING | IRQF_ONESHOT,
>> + "q6v5 fatal", q6v5);
>> + if (ret) {
>> + dev_err(&pdev->dev, "failed to acquire fatal IRQ\n");
>> + return ret;
>> + }
>> +
>> + q6v5->ready_irq = platform_get_irq_byname(pdev, "ready");
>> + ret = devm_request_threaded_irq(&pdev->dev, q6v5->ready_irq,
>> + NULL, q6v5_ready_interrupt,
>> + IRQF_TRIGGER_RISING | IRQF_ONESHOT,
>> + "q6v5 ready", q6v5);
>> + if (ret) {
>> + dev_err(&pdev->dev, "failed to acquire ready IRQ\n");
>> + return ret;
>> + }
>> +
>> + q6v5->handover_irq = platform_get_irq_byname(pdev, "handover");
>> + ret = devm_request_threaded_irq(&pdev->dev, q6v5->handover_irq,
>> + NULL, q6v5_handover_interrupt,
>> + IRQF_TRIGGER_RISING | IRQF_ONESHOT,
>> + "q6v5 handover", q6v5);
>> + if (ret) {
>> + dev_err(&pdev->dev, "failed to acquire handover IRQ\n");
>> + return ret;
>> + }
>> + disable_irq(q6v5->handover_irq);
>> +
>> + q6v5->stop_irq = platform_get_irq_byname(pdev, "stop-ack");
>> + ret = devm_request_threaded_irq(&pdev->dev, q6v5->stop_irq,
>> + NULL, q6v5_stop_interrupt,
>> + IRQF_TRIGGER_RISING | IRQF_ONESHOT,
>> + "q6v5 stop", q6v5);
>> + if (ret) {
>> + dev_err(&pdev->dev, "failed to acquire stop-ack IRQ\n");
>> + return ret;
>> + }
>> +
>> + q6v5->state = qcom_smem_state_get(&pdev->dev, "stop", &q6v5->stop_bit);
>> + if (IS_ERR(q6v5->state)) {
>> + dev_err(&pdev->dev, "failed to acquire stop state\n");
>> + return PTR_ERR(q6v5->state);
>> + }
>> +
>> + return 0;
>> +}
>> diff --git a/drivers/remoteproc/qcom_q6v5.h b/drivers/remoteproc/qcom_q6v5.h
>> new file mode 100644
>> index 000000000000..7ac92c1e0f49
>> --- /dev/null
>> +++ b/drivers/remoteproc/qcom_q6v5.h
>> @@ -0,0 +1,46 @@
>> +/* SPDX-License-Identifier: GPL-2.0 */
>> +
>> +#ifndef __QCOM_Q6V5_H__
>> +#define __QCOM_Q6V5_H__
>> +
>> +#include <linux/kernel.h>
>> +#include <linux/completion.h>
>> +
>> +struct rproc;
>> +struct qcom_smem_state;
>> +
>> +struct qcom_q6v5 {
>> + struct device *dev;
>> + struct rproc *rproc;
>> +
>> + struct qcom_smem_state *state;
>> + unsigned stop_bit;
>> +
>> + int wdog_irq;
>> + int fatal_irq;
>> + int ready_irq;
>> + int handover_irq;
>> + int stop_irq;
>> +
>> + bool handover_issued;
>> +
>> + struct completion start_done;
>> + struct completion stop_done;
>> +
>> + int crash_reason;
>> +
>> + bool running;
>> +
>> + void (*handover)(struct qcom_q6v5 *q6v5);
>> +};
>> +
>> +int qcom_q6v5_init(struct qcom_q6v5 *q6v5, struct platform_device *pdev,
>> + struct rproc *rproc, int crash_reason,
>> + void (*handover)(struct qcom_q6v5 *q6v5));
>> +
>> +int qcom_q6v5_prepare(struct qcom_q6v5 *q6v5);
>> +int qcom_q6v5_unprepare(struct qcom_q6v5 *q6v5);
>> +int qcom_q6v5_request_stop(struct qcom_q6v5 *q6v5);
>> +int qcom_q6v5_wait_for_start(struct qcom_q6v5 *q6v5, int timeout);
>> +
>> +#endif
>>
>
> Regards,
> Sricharan
>
--
Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc, is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [relevance 6%]
* Re: [PATCH v5 1/8] dt-bindings: reset: Add AOSS reset bindings for SDM845 SoCs
2018-05-21 17:27 19% ` [PATCH v5 1/8] dt-bindings: reset: Add AOSS reset bindings for " Sibi Sankar
2018-05-22 16:17 0% ` Rob Herring
@ 2018-06-23 0:44 0% ` Bjorn Andersson
2018-06-27 14:24 6% ` Sibi S
1 sibling, 1 reply; 200+ results
From: Bjorn Andersson @ 2018-06-23 0:44 UTC (permalink / raw)
To: Sibi Sankar, Stephen Boyd
Cc: p.zabel, robh+dt, linux-remoteproc, linux-kernel, devicetree,
georgi.djakov, jassisinghbrar, ohad, mark.rutland, kyan,
sricharan, akdwived, linux-arm-msm, tsoni
On Mon 21 May 10:27 PDT 2018, Sibi Sankar wrote:
> Add SDM845 AOSS (always on subsystem) reset controller binding
>
I think it would be better if you made the binding represent the entire
clock controller, rather than only the reset-related portion of it.
As I can't find anything in the downstream kernel that references the
clock part of the hardware block I think the driver can be kept as is
(with updated compatible and adjust the offsets of the registers)
This makes the DT better represents the hardware and it makes it
possible to control the clocks in the future, without breaking backwards
compatibility with existing DTBs.
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
> .../bindings/reset/qcom,aoss-reset.txt | 52 +++++++++++++++++++
> include/dt-bindings/reset/qcom,sdm845-aoss.h | 17 ++++++
> 2 files changed, 69 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
> create mode 100644 include/dt-bindings/reset/qcom,sdm845-aoss.h
>
> diff --git a/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
> new file mode 100644
> index 000000000000..cd5dcafb4ed7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
> @@ -0,0 +1,52 @@
> +Qualcomm AOSS Reset Controller
> +======================================
> +
> +This binding describes a reset-controller found on AOSS (always on subsystem)
> +for Qualcomm SDM845 SoCs.
> +
> +Required properties:
> +- compatible:
> + Usage: required
> + Value type: <string>
> + Definition: must be:
> + "qcom,sdm845-aoss-reset"
qcom,sdm845-aoss-cc
> +
> +- reg:
> + Usage: required
> + Value type: <prop-encoded-array>
> + Definition: must specify the base address and size of the register
> + space.
> +
> +- #reset-cells:
> + Usage: required
> + Value type: <uint>
> + Definition: must be 1; cell entry represents the reset index.
> +
> +Example:
> +
> +aoss_reset: reset-controller@c2b0000 {
> + compatible = "qcom,sdm845-aoss-reset";
> + reg = <0xc2b0000 0x21000>;
reg = <0xc2a0000 0x31000>;
> + #reset-cells = <1>;
> +};
> +
Apart from this the binding looks good!
Regards,
Bjorn
^ permalink raw reply [relevance 0%]
* Re: [PATCH v5 2/8] reset: qcom: AOSS (always on subsystem) reset controller
2018-05-21 17:27 16% ` [PATCH v5 2/8] reset: qcom: AOSS (always on subsystem) reset controller Sibi Sankar
@ 2018-06-23 0:46 0% ` Bjorn Andersson
0 siblings, 0 replies; 200+ results
From: Bjorn Andersson @ 2018-06-23 0:46 UTC (permalink / raw)
To: Sibi Sankar, Stephen Boyd
Cc: p.zabel, robh+dt, linux-remoteproc, linux-kernel, devicetree,
georgi.djakov, jassisinghbrar, ohad, mark.rutland, kyan,
sricharan, akdwived, linux-arm-msm, tsoni
On Mon 21 May 10:27 PDT 2018, Sibi Sankar wrote:
> Add reset controller driver for Qualcomm SDM845 SoC to
> control reset signals provided by AOSS for Modem, Venus
> ADSP, GPU, Camera, Wireless, Display subsystem
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
With the adaptions discussed in the DT binding patch (compatible and
register offsets) you have my:
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Regards,
Bjorn
> ---
> drivers/reset/Kconfig | 9 +++
> drivers/reset/Makefile | 1 +
> drivers/reset/reset-qcom-aoss.c | 133 ++++++++++++++++++++++++++++++++
> 3 files changed, 143 insertions(+)
> create mode 100644 drivers/reset/reset-qcom-aoss.c
>
> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
> index c0b292be1b72..756ad2b27d0f 100644
> --- a/drivers/reset/Kconfig
> +++ b/drivers/reset/Kconfig
> @@ -82,6 +82,15 @@ config RESET_PISTACHIO
> help
> This enables the reset driver for ImgTec Pistachio SoCs.
>
> +config RESET_QCOM_AOSS
> + bool "Qcom AOSS Reset Driver"
> + depends on ARCH_QCOM || COMPILE_TEST
> + help
> + This enables the AOSS (always on subsystem) reset driver
> + for Qualcomm SDM845 SoCs. Say Y if you want to control
> + reset signals provided by AOSS for Modem, Venus, ADSP,
> + GPU, Camera, Wireless, Display subsystem. Otherwise, say N.
> +
> config RESET_SIMPLE
> bool "Simple Reset Controller Driver" if COMPILE_TEST
> default ARCH_SOCFPGA || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED
> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
> index c1261dcfe9ad..6881e4d287f0 100644
> --- a/drivers/reset/Makefile
> +++ b/drivers/reset/Makefile
> @@ -14,6 +14,7 @@ obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
> obj-$(CONFIG_RESET_MESON) += reset-meson.o
> obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
> obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o
> +obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o
> obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
> obj-$(CONFIG_RESET_STM32MP157) += reset-stm32mp1.o
> obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
> diff --git a/drivers/reset/reset-qcom-aoss.c b/drivers/reset/reset-qcom-aoss.c
> new file mode 100644
> index 000000000000..d9ca7339c434
> --- /dev/null
> +++ b/drivers/reset/reset-qcom-aoss.c
> @@ -0,0 +1,133 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2018 The Linux Foundation. All rights reserved.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/reset-controller.h>
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +#include <linux/of_device.h>
> +#include <dt-bindings/reset/qcom,sdm845-aoss.h>
> +
> +struct qcom_aoss_reset_map {
> + unsigned int reg;
> +};
> +
> +struct qcom_aoss_desc {
> + const struct qcom_aoss_reset_map *resets;
> + size_t num_resets;
> +};
> +
> +struct qcom_aoss_reset_data {
> + struct reset_controller_dev rcdev;
> + void __iomem *base;
> + const struct qcom_aoss_desc *desc;
> +};
> +
> +static const struct qcom_aoss_reset_map sdm845_aoss_resets[] = {
> + [AOSS_CC_MSS_RESTART] = {0x0},
> + [AOSS_CC_CAMSS_RESTART] = {0x1000},
> + [AOSS_CC_VENUS_RESTART] = {0x2000},
> + [AOSS_CC_GPU_RESTART] = {0x3000},
> + [AOSS_CC_DISPSS_RESTART] = {0x4000},
> + [AOSS_CC_WCSS_RESTART] = {0x10000},
> + [AOSS_CC_LPASS_RESTART] = {0x20000},
> +};
> +
> +static const struct qcom_aoss_desc sdm845_aoss_desc = {
> + .resets = sdm845_aoss_resets,
> + .num_resets = ARRAY_SIZE(sdm845_aoss_resets),
> +};
> +
> +static inline struct qcom_aoss_reset_data *to_qcom_aoss_reset_data(
> + struct reset_controller_dev *rcdev)
> +{
> + return container_of(rcdev, struct qcom_aoss_reset_data, rcdev);
> +}
> +
> +static int qcom_aoss_control_assert(struct reset_controller_dev *rcdev,
> + unsigned long idx)
> +{
> + struct qcom_aoss_reset_data *data = to_qcom_aoss_reset_data(rcdev);
> + const struct qcom_aoss_reset_map *map = &data->desc->resets[idx];
> +
> + writel(1, data->base + map->reg);
> + /* Wait 6 32kHz sleep cycles for reset */
> + usleep_range(200, 300);
> + return 0;
> +}
> +
> +static int qcom_aoss_control_deassert(struct reset_controller_dev *rcdev,
> + unsigned long idx)
> +{
> + struct qcom_aoss_reset_data *data = to_qcom_aoss_reset_data(rcdev);
> + const struct qcom_aoss_reset_map *map = &data->desc->resets[idx];
> +
> + writel(0, data->base + map->reg);
> + /* Wait 6 32kHz sleep cycles for reset */
> + usleep_range(200, 300);
> + return 0;
> +}
> +
> +static int qcom_aoss_control_reset(struct reset_controller_dev *rcdev,
> + unsigned long idx)
> +{
> + qcom_aoss_control_assert(rcdev, idx);
> +
> + return qcom_aoss_control_deassert(rcdev, idx);
> +}
> +
> +static const struct reset_control_ops qcom_aoss_reset_ops = {
> + .reset = qcom_aoss_control_reset,
> + .assert = qcom_aoss_control_assert,
> + .deassert = qcom_aoss_control_deassert,
> +};
> +
> +static int qcom_aoss_reset_probe(struct platform_device *pdev)
> +{
> + struct qcom_aoss_reset_data *data;
> + struct device *dev = &pdev->dev;
> + const struct qcom_aoss_desc *desc;
> + struct resource *res;
> +
> + desc = of_device_get_match_data(dev);
> + if (!desc)
> + return -EINVAL;
> +
> + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
> + if (!data)
> + return -ENOMEM;
> +
> + data->desc = desc;
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + data->base = devm_ioremap_resource(dev, res);
> + if (IS_ERR(data->base))
> + return PTR_ERR(data->base);
> +
> + data->rcdev.owner = THIS_MODULE;
> + data->rcdev.ops = &qcom_aoss_reset_ops;
> + data->rcdev.nr_resets = desc->num_resets;
> + data->rcdev.of_node = dev->of_node;
> +
> + return devm_reset_controller_register(dev, &data->rcdev);
> +}
> +
> +static const struct of_device_id qcom_aoss_reset_of_match[] = {
> + { .compatible = "qcom,sdm845-aoss-reset", .data = &sdm845_aoss_desc },
> + {}
> +};
> +
> +static struct platform_driver qcom_aoss_reset_driver = {
> + .probe = qcom_aoss_reset_probe,
> + .driver = {
> + .name = "qcom_aoss_reset",
> + .of_match_table = qcom_aoss_reset_of_match,
> + },
> +};
> +
> +builtin_platform_driver(qcom_aoss_reset_driver);
> +
> +MODULE_DESCRIPTION("Qualcomm AOSS Reset Driver");
> +MODULE_LICENSE("GPL v2");
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
^ permalink raw reply [relevance 0%]
* Re: [PATCH v5 1/8] dt-bindings: reset: Add AOSS reset bindings for SDM845 SoCs
2018-06-23 0:44 0% ` Bjorn Andersson
@ 2018-06-27 14:24 6% ` Sibi S
0 siblings, 0 replies; 200+ results
From: Sibi S @ 2018-06-27 14:24 UTC (permalink / raw)
To: Bjorn Andersson, Stephen Boyd
Cc: p.zabel, robh+dt, linux-remoteproc, linux-kernel, devicetree,
georgi.djakov, jassisinghbrar, ohad, mark.rutland, kyan,
sricharan, akdwived, linux-arm-msm, tsoni
Hi Bjorn,
Thanks for the review will address the comments in the next respin.
On 06/23/2018 06:14 AM, Bjorn Andersson wrote:
> On Mon 21 May 10:27 PDT 2018, Sibi Sankar wrote:
>
>> Add SDM845 AOSS (always on subsystem) reset controller binding
>>
>
> I think it would be better if you made the binding represent the entire
> clock controller, rather than only the reset-related portion of it.
>
> As I can't find anything in the downstream kernel that references the
> clock part of the hardware block I think the driver can be kept as is
> (with updated compatible and adjust the offsets of the registers)
>
>
> This makes the DT better represents the hardware and it makes it
> possible to control the clocks in the future, without breaking backwards
> compatibility with existing DTBs.
>
yup makes sense.
>> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
>> ---
>> .../bindings/reset/qcom,aoss-reset.txt | 52 +++++++++++++++++++
>> include/dt-bindings/reset/qcom,sdm845-aoss.h | 17 ++++++
>> 2 files changed, 69 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
>> create mode 100644 include/dt-bindings/reset/qcom,sdm845-aoss.h
>>
>> diff --git a/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
>> new file mode 100644
>> index 000000000000..cd5dcafb4ed7
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
>> @@ -0,0 +1,52 @@
>> +Qualcomm AOSS Reset Controller
>> +======================================
>> +
>> +This binding describes a reset-controller found on AOSS (always on subsystem)
>> +for Qualcomm SDM845 SoCs.
>> +
>> +Required properties:
>> +- compatible:
>> + Usage: required
>> + Value type: <string>
>> + Definition: must be:
>> + "qcom,sdm845-aoss-reset"
>
> qcom,sdm845-aoss-cc
>
>> +
>> +- reg:
>> + Usage: required
>> + Value type: <prop-encoded-array>
>> + Definition: must specify the base address and size of the register
>> + space.
>> +
>> +- #reset-cells:
>> + Usage: required
>> + Value type: <uint>
>> + Definition: must be 1; cell entry represents the reset index.
>> +
>> +Example:
>> +
>> +aoss_reset: reset-controller@c2b0000 {
>> + compatible = "qcom,sdm845-aoss-reset";
>> + reg = <0xc2b0000 0x21000>;
>
> reg = <0xc2a0000 0x31000>;
>
>> + #reset-cells = <1>;
>> +};
>> +
>
> Apart from this the binding looks good!
>
> Regards,
> Bjorn
>
--
Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc, is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [relevance 6%]
* [PATCH v6 1/8] dt-bindings: reset: Add AOSS reset bindings for SDM845 SoCs
@ 2018-06-27 14:24 19% Sibi Sankar
2018-06-27 14:24 17% ` [PATCH v6 2/8] reset: qcom: AOSS (always on subsystem) reset controller Sibi Sankar
` (3 more replies)
0 siblings, 4 replies; 200+ results
From: Sibi Sankar @ 2018-06-27 14:24 UTC (permalink / raw)
To: p.zabel, robh+dt
Cc: bjorn.andersson, linux-kernel, devicetree, mark.rutland, kyan,
akdwived, linux-arm-msm, tsoni, Sibi Sankar
Add SDM845 AOSS (always on subsystem) reset controller binding
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
Not including Rob's earlier Reviewed-by due to change in compatible
.../bindings/reset/qcom,aoss-reset.txt | 52 +++++++++++++++++++
include/dt-bindings/reset/qcom,sdm845-aoss.h | 17 ++++++
2 files changed, 69 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
create mode 100644 include/dt-bindings/reset/qcom,sdm845-aoss.h
diff --git a/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
new file mode 100644
index 000000000000..510c748656ec
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
@@ -0,0 +1,52 @@
+Qualcomm AOSS Reset Controller
+======================================
+
+This binding describes a reset-controller found on AOSS-CC (always on subsystem)
+for Qualcomm SDM845 SoCs.
+
+Required properties:
+- compatible:
+ Usage: required
+ Value type: <string>
+ Definition: must be:
+ "qcom,sdm845-aoss-cc"
+
+- reg:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: must specify the base address and size of the register
+ space.
+
+- #reset-cells:
+ Usage: required
+ Value type: <uint>
+ Definition: must be 1; cell entry represents the reset index.
+
+Example:
+
+aoss_reset: reset-controller@c2a0000 {
+ compatible = "qcom,sdm845-aoss-cc";
+ reg = <0xc2a0000 0x31000>;
+ #reset-cells = <1>;
+};
+
+Specifying reset lines connected to IP modules
+==============================================
+
+Device nodes that need access to reset lines should
+specify them as a reset phandle in their corresponding node as
+specified in reset.txt.
+
+For list of all valid reset indicies see
+<dt-bindings/reset/qcom,sdm845-aoss.h>
+
+Example:
+
+modem-pil@4080000 {
+ ...
+
+ resets = <&aoss_reset AOSS_CC_MSS_RESTART>;
+ reset-names = "mss_restart";
+
+ ...
+};
diff --git a/include/dt-bindings/reset/qcom,sdm845-aoss.h b/include/dt-bindings/reset/qcom,sdm845-aoss.h
new file mode 100644
index 000000000000..476c5fc873b6
--- /dev/null
+++ b/include/dt-bindings/reset/qcom,sdm845-aoss.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_RESET_AOSS_SDM_845_H
+#define _DT_BINDINGS_RESET_AOSS_SDM_845_H
+
+#define AOSS_CC_MSS_RESTART 0
+#define AOSS_CC_CAMSS_RESTART 1
+#define AOSS_CC_VENUS_RESTART 2
+#define AOSS_CC_GPU_RESTART 3
+#define AOSS_CC_DISPSS_RESTART 4
+#define AOSS_CC_WCSS_RESTART 5
+#define AOSS_CC_LPASS_RESTART 6
+
+#endif
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 19%]
* [PATCH v6 2/8] reset: qcom: AOSS (always on subsystem) reset controller
2018-06-27 14:24 19% [PATCH v6 1/8] dt-bindings: reset: Add AOSS reset bindings for SDM845 SoCs Sibi Sankar
@ 2018-06-27 14:24 17% ` Sibi Sankar
2018-06-27 16:47 0% ` [PATCH v6 1/8] dt-bindings: reset: Add AOSS reset bindings for SDM845 SoCs Bjorn Andersson
` (2 subsequent siblings)
3 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2018-06-27 14:24 UTC (permalink / raw)
To: p.zabel, robh+dt
Cc: bjorn.andersson, linux-kernel, devicetree, mark.rutland, kyan,
akdwived, linux-arm-msm, tsoni, Sibi Sankar
Add reset controller driver for Qualcomm SDM845 SoC to
control reset signals provided by AOSS for Modem, Venus
ADSP, GPU, Camera, Wireless, Display subsystem
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
drivers/reset/Kconfig | 9 +++
drivers/reset/Makefile | 1 +
drivers/reset/reset-qcom-aoss.c | 133 ++++++++++++++++++++++++++++++++
3 files changed, 143 insertions(+)
create mode 100644 drivers/reset/reset-qcom-aoss.c
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index c0b292be1b72..756ad2b27d0f 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -82,6 +82,15 @@ config RESET_PISTACHIO
help
This enables the reset driver for ImgTec Pistachio SoCs.
+config RESET_QCOM_AOSS
+ bool "Qcom AOSS Reset Driver"
+ depends on ARCH_QCOM || COMPILE_TEST
+ help
+ This enables the AOSS (always on subsystem) reset driver
+ for Qualcomm SDM845 SoCs. Say Y if you want to control
+ reset signals provided by AOSS for Modem, Venus, ADSP,
+ GPU, Camera, Wireless, Display subsystem. Otherwise, say N.
+
config RESET_SIMPLE
bool "Simple Reset Controller Driver" if COMPILE_TEST
default ARCH_SOCFPGA || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index c1261dcfe9ad..6881e4d287f0 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
obj-$(CONFIG_RESET_MESON) += reset-meson.o
obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o
+obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o
obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
obj-$(CONFIG_RESET_STM32MP157) += reset-stm32mp1.o
obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
diff --git a/drivers/reset/reset-qcom-aoss.c b/drivers/reset/reset-qcom-aoss.c
new file mode 100644
index 000000000000..36db96750450
--- /dev/null
+++ b/drivers/reset/reset-qcom-aoss.c
@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/of_device.h>
+#include <dt-bindings/reset/qcom,sdm845-aoss.h>
+
+struct qcom_aoss_reset_map {
+ unsigned int reg;
+};
+
+struct qcom_aoss_desc {
+ const struct qcom_aoss_reset_map *resets;
+ size_t num_resets;
+};
+
+struct qcom_aoss_reset_data {
+ struct reset_controller_dev rcdev;
+ void __iomem *base;
+ const struct qcom_aoss_desc *desc;
+};
+
+static const struct qcom_aoss_reset_map sdm845_aoss_resets[] = {
+ [AOSS_CC_MSS_RESTART] = {0x10000},
+ [AOSS_CC_CAMSS_RESTART] = {0x11000},
+ [AOSS_CC_VENUS_RESTART] = {0x12000},
+ [AOSS_CC_GPU_RESTART] = {0x13000},
+ [AOSS_CC_DISPSS_RESTART] = {0x14000},
+ [AOSS_CC_WCSS_RESTART] = {0x20000},
+ [AOSS_CC_LPASS_RESTART] = {0x30000},
+};
+
+static const struct qcom_aoss_desc sdm845_aoss_desc = {
+ .resets = sdm845_aoss_resets,
+ .num_resets = ARRAY_SIZE(sdm845_aoss_resets),
+};
+
+static inline struct qcom_aoss_reset_data *to_qcom_aoss_reset_data(
+ struct reset_controller_dev *rcdev)
+{
+ return container_of(rcdev, struct qcom_aoss_reset_data, rcdev);
+}
+
+static int qcom_aoss_control_assert(struct reset_controller_dev *rcdev,
+ unsigned long idx)
+{
+ struct qcom_aoss_reset_data *data = to_qcom_aoss_reset_data(rcdev);
+ const struct qcom_aoss_reset_map *map = &data->desc->resets[idx];
+
+ writel(1, data->base + map->reg);
+ /* Wait 6 32kHz sleep cycles for reset */
+ usleep_range(200, 300);
+ return 0;
+}
+
+static int qcom_aoss_control_deassert(struct reset_controller_dev *rcdev,
+ unsigned long idx)
+{
+ struct qcom_aoss_reset_data *data = to_qcom_aoss_reset_data(rcdev);
+ const struct qcom_aoss_reset_map *map = &data->desc->resets[idx];
+
+ writel(0, data->base + map->reg);
+ /* Wait 6 32kHz sleep cycles for reset */
+ usleep_range(200, 300);
+ return 0;
+}
+
+static int qcom_aoss_control_reset(struct reset_controller_dev *rcdev,
+ unsigned long idx)
+{
+ qcom_aoss_control_assert(rcdev, idx);
+
+ return qcom_aoss_control_deassert(rcdev, idx);
+}
+
+static const struct reset_control_ops qcom_aoss_reset_ops = {
+ .reset = qcom_aoss_control_reset,
+ .assert = qcom_aoss_control_assert,
+ .deassert = qcom_aoss_control_deassert,
+};
+
+static int qcom_aoss_reset_probe(struct platform_device *pdev)
+{
+ struct qcom_aoss_reset_data *data;
+ struct device *dev = &pdev->dev;
+ const struct qcom_aoss_desc *desc;
+ struct resource *res;
+
+ desc = of_device_get_match_data(dev);
+ if (!desc)
+ return -EINVAL;
+
+ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ data->desc = desc;
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ data->base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(data->base))
+ return PTR_ERR(data->base);
+
+ data->rcdev.owner = THIS_MODULE;
+ data->rcdev.ops = &qcom_aoss_reset_ops;
+ data->rcdev.nr_resets = desc->num_resets;
+ data->rcdev.of_node = dev->of_node;
+
+ return devm_reset_controller_register(dev, &data->rcdev);
+}
+
+static const struct of_device_id qcom_aoss_reset_of_match[] = {
+ { .compatible = "qcom,sdm845-aoss-cc", .data = &sdm845_aoss_desc },
+ {}
+};
+
+static struct platform_driver qcom_aoss_reset_driver = {
+ .probe = qcom_aoss_reset_probe,
+ .driver = {
+ .name = "qcom_aoss_reset",
+ .of_match_table = qcom_aoss_reset_of_match,
+ },
+};
+
+builtin_platform_driver(qcom_aoss_reset_driver);
+
+MODULE_DESCRIPTION("Qualcomm AOSS Reset Driver");
+MODULE_LICENSE("GPL v2");
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 17%]
* Re: [PATCH v6 1/8] dt-bindings: reset: Add AOSS reset bindings for SDM845 SoCs
2018-06-27 14:24 19% [PATCH v6 1/8] dt-bindings: reset: Add AOSS reset bindings for SDM845 SoCs Sibi Sankar
2018-06-27 14:24 17% ` [PATCH v6 2/8] reset: qcom: AOSS (always on subsystem) reset controller Sibi Sankar
@ 2018-06-27 16:47 0% ` Bjorn Andersson
2018-07-03 2:32 0% ` Rob Herring
2018-07-16 10:19 0% ` Philipp Zabel
3 siblings, 0 replies; 200+ results
From: Bjorn Andersson @ 2018-06-27 16:47 UTC (permalink / raw)
To: Sibi Sankar
Cc: p.zabel, robh+dt, linux-kernel, devicetree, mark.rutland, kyan,
akdwived, linux-arm-msm, tsoni
On Wed 27 Jun 07:24 PDT 2018, Sibi Sankar wrote:
> Add SDM845 AOSS (always on subsystem) reset controller binding
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Regards,
Bjorn
> ---
>
> Not including Rob's earlier Reviewed-by due to change in compatible
>
> .../bindings/reset/qcom,aoss-reset.txt | 52 +++++++++++++++++++
> include/dt-bindings/reset/qcom,sdm845-aoss.h | 17 ++++++
> 2 files changed, 69 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
> create mode 100644 include/dt-bindings/reset/qcom,sdm845-aoss.h
>
> diff --git a/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
> new file mode 100644
> index 000000000000..510c748656ec
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
> @@ -0,0 +1,52 @@
> +Qualcomm AOSS Reset Controller
> +======================================
> +
> +This binding describes a reset-controller found on AOSS-CC (always on subsystem)
> +for Qualcomm SDM845 SoCs.
> +
> +Required properties:
> +- compatible:
> + Usage: required
> + Value type: <string>
> + Definition: must be:
> + "qcom,sdm845-aoss-cc"
> +
> +- reg:
> + Usage: required
> + Value type: <prop-encoded-array>
> + Definition: must specify the base address and size of the register
> + space.
> +
> +- #reset-cells:
> + Usage: required
> + Value type: <uint>
> + Definition: must be 1; cell entry represents the reset index.
> +
> +Example:
> +
> +aoss_reset: reset-controller@c2a0000 {
> + compatible = "qcom,sdm845-aoss-cc";
> + reg = <0xc2a0000 0x31000>;
> + #reset-cells = <1>;
> +};
> +
> +Specifying reset lines connected to IP modules
> +==============================================
> +
> +Device nodes that need access to reset lines should
> +specify them as a reset phandle in their corresponding node as
> +specified in reset.txt.
> +
> +For list of all valid reset indicies see
> +<dt-bindings/reset/qcom,sdm845-aoss.h>
> +
> +Example:
> +
> +modem-pil@4080000 {
> + ...
> +
> + resets = <&aoss_reset AOSS_CC_MSS_RESTART>;
> + reset-names = "mss_restart";
> +
> + ...
> +};
> diff --git a/include/dt-bindings/reset/qcom,sdm845-aoss.h b/include/dt-bindings/reset/qcom,sdm845-aoss.h
> new file mode 100644
> index 000000000000..476c5fc873b6
> --- /dev/null
> +++ b/include/dt-bindings/reset/qcom,sdm845-aoss.h
> @@ -0,0 +1,17 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2018 The Linux Foundation. All rights reserved.
> + */
> +
> +#ifndef _DT_BINDINGS_RESET_AOSS_SDM_845_H
> +#define _DT_BINDINGS_RESET_AOSS_SDM_845_H
> +
> +#define AOSS_CC_MSS_RESTART 0
> +#define AOSS_CC_CAMSS_RESTART 1
> +#define AOSS_CC_VENUS_RESTART 2
> +#define AOSS_CC_GPU_RESTART 3
> +#define AOSS_CC_DISPSS_RESTART 4
> +#define AOSS_CC_WCSS_RESTART 5
> +#define AOSS_CC_LPASS_RESTART 6
> +
> +#endif
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
^ permalink raw reply [relevance 0%]
* [PATCH 4.17 000/220] 4.17.4-stable review
@ 2018-07-01 16:20 2% Greg Kroah-Hartman
2018-07-01 16:23 8% ` [PATCH 4.17 165/220] remoteproc: Prevent incorrect rproc state on xfer mem ownership failure Greg Kroah-Hartman
0 siblings, 1 reply; 200+ results
From: Greg Kroah-Hartman @ 2018-07-01 16:20 UTC (permalink / raw)
To: linux-kernel
Cc: Greg Kroah-Hartman, torvalds, akpm, linux, shuah, patches,
ben.hutchings, lkft-triage, stable
This is the start of the stable review cycle for the 4.17.4 release.
There are 220 patches in this series, all will be posted as a response
to this one. If anyone has any issues with these being applied, please
let me know.
Responses should be made by Tue Jul 3 16:08:27 UTC 2018.
Anything received after that time might be too late.
The whole patch series can be found in one patch at:
https://www.kernel.org/pub/linux/kernel/v4.x/stable-review/patch-4.17.4-rc1.gz
or in the git tree and branch at:
git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable-rc.git linux-4.17.y
and the diffstat can be found below.
thanks,
greg k-h
-------------
Pseudo-Shortlog of commits:
Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Linux 4.17.4-rc1
Wenwen Wang <wang6495@umn.edu>
virt: vbox: Only copy_from_user the request-header once
Mike Snitzer <snitzer@redhat.com>
dm thin: handle running out of data space vs concurrent discard
Bart Van Assche <bart.vanassche@wdc.com>
dm zoned: avoid triggering reclaim from inside dmz_map()
Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
x86/efi: Fix efi_call_phys_epilog() with CONFIG_X86_5LEVEL=y
Andy Lutomirski <luto@kernel.org>
x86/entry/64/compat: Fix "x86/entry/64/compat: Preserve r8-r11 in int $0x80"
Jann Horn <jannh@google.com>
selinux: move user accesses in selinuxfs out of locked regions
Naoya Horiguchi <n-horiguchi@ah.jp.nec.com>
x86/e820: put !E820_TYPE_RAM regions into memblock.reserved
Bart Van Assche <bart.vanassche@wdc.com>
block: Fix cloning of requests with a special payload
Keith Busch <keith.busch@intel.com>
block: Fix transfer when chunk sectors exceeds max
Ross Zwisler <ross.zwisler@linux.intel.com>
pmem: only set QUEUE_FLAG_DAX for fsdax mode
Mike Snitzer <snitzer@redhat.com>
dm: use bio_split() when splitting out the already processed bio
Jason A. Donenfeld <Jason@zx2c4.com>
kasan: depend on CONFIG_SLUB_DEBUG
Mikulas Patocka <mpatocka@redhat.com>
slub: fix failure when we delete and create a slab cache
Wolfram Sang <wsa+renesas@sang-engineering.com>
i2c: gpio: initialize SCL to HIGH again
Wolfram Sang <wsa+renesas@sang-engineering.com>
Revert "i2c: algo-bit: init the bus to a known state"
Hui Wang <hui.wang@canonical.com>
ALSA: hda/realtek - Fix the problem of two front mics on more machines
Takashi Iwai <tiwai@suse.de>
ALSA: hda/realtek - Add a quirk for FSC ESPRIMO U9210
Takashi Iwai <tiwai@suse.de>
ALSA: hda/realtek - Fix pop noise on Lenovo P50 & co
Takashi Iwai <tiwai@suse.de>
ALSA: hda - Force to link down at runtime suspend on ATI/AMD HDMI
Takashi Iwai <tiwai@suse.de>
ALSA: timer: Fix UBSAN warning at SNDRV_TIMER_IOCTL_NEXT_DEVICE ioctl
??? <kt.liao@emc.com.tw>
Input: elantech - fix V4 report decoding for module with middle key
Aaron Ma <aaron.ma@canonical.com>
Input: elantech - enable middle button of touchpads on ThinkPad P52
Ben Hutchings <ben.hutchings@codethink.co.uk>
Input: elan_i2c_smbus - fix more potential stack buffer overflows
Dmitry Torokhov <dmitry.torokhov@gmail.com>
Input: psmouse - fix button reporting for basic protocols
Enno Boland <gottox@voidlinux.eu>
Input: xpad - fix GPD Win 2 controller name
Jan Kara <jack@suse.cz>
udf: Detect incorrect directory size
Bartosz Golaszewski <bgolaszewski@baylibre.com>
net: ethernet: fix suspend/resume in davinci_emac
Boris Ostrovsky <boris.ostrovsky@oracle.com>
xen: Remove unnecessary BUG_ON from __unbind_from_irq()
Steven Rostedt (VMware) <rostedt@goodmis.org>
tracing: Check for no filter when processing event filters
Dan Williams <dan.j.williams@intel.com>
mm: fix devmem_is_allowed() for sub-page System RAM intersections
Jia He <jia.he@hxt-semitech.com>
mm/ksm.c: ignore STABLE_FLAG of rmap_item->address in rmap_walk_ksm()
Dongsheng Yang <dongsheng.yang@easystack.cn>
rbd: flush rbd_dev->watch_dwork after watch is unregistered
Hans de Goede <hdegoede@redhat.com>
pwm: lpss: platform: Save/restore the ctrl register over a suspend/resume
Alexandr Savca <alexandr.savca@saltedge.com>
Input: elan_i2c - add ELAN0618 (Lenovo v330 15IKB) ACPI ID
Hans de Goede <hdegoede@redhat.com>
Input: silead - add MSSL0002 ACPI HID
Hans de Goede <hdegoede@redhat.com>
ACPI / LPSS: Add missing prv_offset setting for byt/cht PWM devices
Kees Cook <keescook@chromium.org>
video: uvesafb: Fix integer overflow in allocation
Trond Myklebust <trond.myklebust@hammerspace.com>
NFSv4: Fix a typo in nfs41_sequence_process
Trond Myklebust <trond.myklebust@hammerspace.com>
NFSv4: Revert commit 5f83d86cf531d ("NFSv4.x: Fix wraparound issues..")
Dave Wysochanski <dwysocha@redhat.com>
NFSv4: Fix possible 1-byte stack overflow in nfs_idmap_read_and_verify_message
Scott Mayhew <smayhew@redhat.com>
nfsd: restrict rd_maxcount to svc_max_payload in nfsd_encode_readdir
Mauro Carvalho Chehab <mchehab@kernel.org>
media: dvb_frontend: fix locking issues at dvb_frontend_get_event()
Sean Young <sean@mess.org>
media: rc: mce_kbd decoder: fix stuck keys
Kai-Heng Feng <kai.heng.feng@canonical.com>
media: cx231xx: Add support for AverMedia DVD EZMaker 7
Mauro Carvalho Chehab <mchehab@kernel.org>
media: v4l2-compat-ioctl32: prevent go past max size
Brad Love <brad@nextdimension.cc>
media: cx231xx: Ignore an i2c mux adapter
ming_qian <ming_qian@realsil.com.cn>
media: uvcvideo: Support realtek's UVC 1.5 device
Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
media: vsp1: Release buffers for each video node
Adrian Hunter <adrian.hunter@intel.com>
perf intel-pt: Fix packet decoding of CYC packets
Adrian Hunter <adrian.hunter@intel.com>
perf intel-pt: Fix "Unexpected indirect branch" error
Adrian Hunter <adrian.hunter@intel.com>
perf intel-pt: Fix MTC timing after overflow
Adrian Hunter <adrian.hunter@intel.com>
perf intel-pt: Fix decoding to accept CBR between FUP and corresponding TIP
Adrian Hunter <adrian.hunter@intel.com>
perf intel-pt: Fix sync_switch INTEL_PT_SS_NOT_TRACING
Adrian Hunter <adrian.hunter@intel.com>
perf tools: Fix symbol and object code resolution for vdso32 and vdsox32
Sean Wang <sean.wang@mediatek.com>
arm: dts: mt7623: fix invalid memory node being generated
Sibi Sankar <sibis@codeaurora.org>
remoteproc: Prevent incorrect rproc state on xfer mem ownership failure
Jarkko Nikula <jarkko.nikula@linux.intel.com>
mfd: intel-lpss: Fix Intel Cannon Lake LPSS I2C input clock
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
mfd: intel-lpss: Program REMAP register in PIO mode
Peter Ujfalusi <peter.ujfalusi@ti.com>
mfd: twl-core: Fix clock initialization
Anton Ivanov <anton.ivanov@cambridgegreys.com>
um: Fix raw interface options
Anton Ivanov <anton.ivanov@cambridgegreys.com>
um: Fix initialization of vector queues
Chao Yu <yuchao0@huawei.com>
f2fs: don't use GFP_ZERO for page caches
Linus Torvalds <torvalds@linux-foundation.org>
Revert "iommu/amd_iommu: Use CONFIG_DMA_DIRECT_OPS=y and dma_direct_{alloc,free}()"
Johan Hovold <johan@kernel.org>
backlight: tps65217_bl: Fix Device Tree node lookup
Johan Hovold <johan@kernel.org>
backlight: max8925_bl: Fix Device Tree node lookup
Johan Hovold <johan@kernel.org>
backlight: as3711_bl: Fix Device Tree node lookup
Silvio Cesare <silvio.cesare@gmail.com>
UBIFS: Fix potential integer overflow in allocation
Richard Weinberger <richard@nod.at>
ubi: fastmap: Correctly handle interrupted erasures in EBA
Richard Weinberger <richard@nod.at>
ubi: fastmap: Cancel work upon detach
Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
rpmsg: smd: do not use mananged resources for endpoints and channels
NeilBrown <neilb@suse.com>
md: fix two problems with setting the "re-add" device state.
Michael Trimarchi <michael@amarulasolutions.com>
rtc: sun6i: Fix bit_idx value for clk_register_gate
Marcin Ziemianowicz <marcin@ziemianowicz.com>
clk: at91: PLL recalc_rate() now using cached MUL and DIV values
Martin Blumenstingl <martin.blumenstingl@googlemail.com>
clk: meson: meson8b: mark fclk_div2 gate clocks as CLK_IS_CRITICAL
Ross Zwisler <ross.zwisler@linux.intel.com>
libnvdimm, pmem: Unconditionally deep flush on *sync
Robert Elliott <elliott@hpe.com>
linvdimm, pmem: Preserve read-only setting for pmem devices
Steffen Maier <maier@linux.ibm.com>
scsi: zfcp: fix missing REC trigger trace on enqueue without ERP thread
Steffen Maier <maier@linux.ibm.com>
scsi: zfcp: fix missing REC trigger trace for all objects in ERP_FAILED
Steffen Maier <maier@linux.ibm.com>
scsi: zfcp: fix missing REC trigger trace on terminate_rport_io for ERP_FAILED
Steffen Maier <maier@linux.ibm.com>
scsi: zfcp: fix missing REC trigger trace on terminate_rport_io early return
Steffen Maier <maier@linux.ibm.com>
scsi: zfcp: fix misleading REC trigger trace where erp_action setup failed
Steffen Maier <maier@linux.ibm.com>
scsi: zfcp: fix missing SCSI trace for retry of abort / scsi_eh TMF
Steffen Maier <maier@linux.ibm.com>
scsi: zfcp: fix missing SCSI trace for result of eh_host_reset_handler
Mikhail Malygin <m.malygin@yadro.com>
scsi: qla2xxx: Spinlock recursion in qla_target
Anil Gurumurthy <anil.gurumurthy@cavium.com>
scsi: qla2xxx: Mask off Scope bits in retry delay
Himanshu Madhani <himanshu.madhani@cavium.com>
scsi: qla2xxx: Fix setting lower transfer speed if GPSC fails
Quinn Tran <quinn.tran@cavium.com>
scsi: qla2xxx: Delete session for nport id change
Sinan Kaya <okaya@codeaurora.org>
scsi: hpsa: disable device during shutdown
Luis Henriques <lhenriques@suse.com>
scsi: scsi_debug: Fix memory leak on module unload
Dan Williams <dan.j.williams@intel.com>
mm: fix __gup_device_huge vs unmap
Christophe JAILLET <christophe.jaillet@wanadoo.fr>
iio: sca3000: Fix an error handling path in 'sca3000_probe()'
Alexandru Ardelean <alexandru.ardelean@analog.com>
iio: adc: ad7791: remove sample freq sysfs attributes
Filipe Manana <fdmanana@suse.com>
Btrfs: fix return value on rename exchange failure
Maciej S. Szmigiero <mail@maciej.szmigiero.name>
X.509: unpack RSA signatureValue field from BIT STRING
Waiman Long <longman@redhat.com>
locking/rwsem: Fix up_read_non_owner() warning with DEBUG_RWSEMS
Yang Yingliang <yangyingliang@huawei.com>
irqchip/gic-v3-its: Don't bind LPI to unavailable NUMA node
Geert Uytterhoeven <geert@linux-m68k.org>
time: Make sure jiffies_to_msecs() preserves non-zero time periods
Huacai Chen <chenhc@lemote.com>
MIPS: io: Add barrier after register read in inX()
Linus Walleij <linus.walleij@linaro.org>
MIPS: pb44: Fix i2c-gpio GPIO descriptor table
Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
cpufreq: intel_pstate: Fix scaling max/min limits with Turbo 3.0
Fabio Estevam <fabio.estevam@nxp.com>
pinctrl: devicetree: Fix pctldev pointer overwrite
Paweł Chmiel <pawel.mikolaj.chmiel@gmail.com>
pinctrl: samsung: Correct EINTG banks order
Terry Zhou <bjzhou@marvell.com>
pinctrl: armada-37xx: Fix spurious irq management
Randy Dunlap <rdunlap@infradead.org>
auxdisplay: fix broken menu
Mika Westerberg <mika.westerberg@linux.intel.com>
PCI: Account for all bridges on bus when distributing bus numbers
Mika Westerberg <mika.westerberg@linux.intel.com>
PCI: pciehp: Clear Presence Detect and Data Link Layer Status Changed on resume
Mika Westerberg <mika.westerberg@linux.intel.com>
PCI: Add ACS quirk for Intel 300 series
Alex Williamson <alex.williamson@redhat.com>
PCI: Add ACS quirk for Intel 7th & 8th Gen mobile
Sridhar Pitchai <Sridhar.Pitchai@microsoft.com>
PCI: hv: Make sure the bus domain is really unique
Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
clk:aspeed: Fix reset bits for PCI/VGA and PECI
Tokunori Ikegami <ikegami@allied-telesis.co.jp>
MIPS: BCM47XX: Enable 74K Core ExternalSync for PCIe erratum
Joakim Tjernlund <joakim.tjernlund@infinera.com>
mtd: cfi_cmdset_0002: Avoid walking all chips when unlocking.
Joakim Tjernlund <joakim.tjernlund@infinera.com>
mtd: cfi_cmdset_0002: Fix unlocking requests crossing a chip boudary
Joakim Tjernlund <joakim.tjernlund@infinera.com>
mtd: cfi_cmdset_0002: fix SEGV unlocking multiple chips
Joakim Tjernlund <joakim.tjernlund@infinera.com>
mtd: cfi_cmdset_0002: Use right chip in do_ppb_xxlock()
Mason Yang <masonccyang@mxic.com.tw>
mtd: rawnand: All AC chips have a broken GET_FEATURES(TIMINGS).
Chris Packham <chris.packham@alliedtelesis.co.nz>
mtd: rawnand: micron: add ONFI_FEATURE_ON_DIE_ECC to supported features
Martin Kaiser <martin@kaiser.cx>
mtd: rawnand: mxc: set spare area size register explicitly
Abhishek Sahu <absahu@codeaurora.org>
mtd: rawnand: fix return value check for bad block status
Masahiro Yamada <yamada.masahiro@socionext.com>
mtd: rawnand: denali_dt: set clk_x_rate to 200 MHz unconditionally
Tokunori Ikegami <ikegami@allied-telesis.co.jp>
mtd: cfi_cmdset_0002: Change write buffer to check correct value
Boris Brezillon <boris.brezillon@bootlin.com>
mtd: rawnand: Do not check FAIL bit when executing a SET_FEATURES op
Bharat Potnuri <bharat@chelsio.com>
RDMA/core: Save kernel caller name when creating CQ using ib_create_cq()
Chuck Lever <chuck.lever@oracle.com>
xprtrdma: Return -ENOBUFS when no pages are available
Leon Romanovsky <leon@kernel.org>
RDMA/mlx4: Discard unknown SQP work requests
Jason Gunthorpe <jgg@ziepe.ca>
IB/uverbs: Fix ordering of ucontext check in ib_uverbs_write
Mike Marciniszyn <mike.marciniszyn@intel.com>
IB/hfi1: Fix user context tail allocation for DMA_RTAIL
Sebastian Sanchez <sebastian.sanchez@intel.com>
IB/hfi1: Optimize kthread pointer locking when queuing CQ entries
Michael J. Ruhl <michael.j.ruhl@intel.com>
IB/hfi1: Reorder incorrect send context disable
Mike Marciniszyn <mike.marciniszyn@intel.com>
IB/hfi1: Fix fault injection init/exit issues
Max Gurtovoy <maxg@mellanox.com>
IB/isert: fix T10-pi check mask setting
Alex Estrin <alex.estrin@intel.com>
IB/isert: Fix for lib/dma_debug check_sync warning
Erez Shitrit <erezsh@mellanox.com>
IB/mlx5: Fetch soft WQE's on fatal error state
Jack Morgenstein <jackm@dev.mellanox.co.il>
IB/core: Make testing MR flags for writability a static inline function
Jack Morgenstein <jackm@dev.mellanox.co.il>
IB/mlx4: Mark user MR as writable if actual virtual memory is writable
Alex Estrin <alex.estrin@intel.com>
IB/{hfi1, qib}: Add handling of kernel restart
Mike Marciniszyn <mike.marciniszyn@intel.com>
IB/qib: Fix DMA api warning with debug kernel
Hans de Goede <hdegoede@redhat.com>
efi/libstub/tpm: Initialize efi_physical_addr_t vars to zero for mixed mode
Tadeusz Struk <tadeusz.struk@intel.com>
tpm: fix race condition in tpm_common_write()
Tadeusz Struk <tadeusz.struk@intel.com>
tpm: fix use after free in tpm2_load_context()
Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
of: platform: stop accessing invalid dev in of_platform_device_destroy
Stefan M Schaeckeler <sschaeck@cisco.com>
of: unittest: for strings, account for trailing \0 in property length field
Frank Rowand <frank.rowand@sony.com>
of: overlay: validate offset from property fixups
Kevin Hilman <khilman@baylibre.com>
ARM64: dts: meson-gx: fix ATF reserved memory region
Jerome Brunet <jbrunet@baylibre.com>
ARM64: dts: meson: disable sd-uhs modes on the libretech-cc
Thor Thayer <thor.thayer@linux.intel.com>
arm64: dts: stratix10: Fix SPI nodes for Stratix10
Miquel Raynal <miquel.raynal@bootlin.com>
arm64: dts: marvell: fix CP110 ICU node size
Will Deacon <will.deacon@arm.com>
arm64: mm: Ensure writes to swapper are ordered wrt subsequent cache maintenance
Will Deacon <will.deacon@arm.com>
arm64: kpti: Use early_param for kpti= command-line option
Jia He <hejianet@gmail.com>
crypto: arm64/aes-blk - fix and move skcipher_walk_done out of kernel_neon_begin, _end
Dave Martin <Dave.Martin@arm.com>
arm64: Fix syscall restarting around signal suppressed by tracer
Joel Fernandes (Google) <joel@joelfernandes.org>
softirq: Reorder trace_softirqs_on to prevent lockdep splat
Michael Buesch <m@bues.ch>
hwrng: core - Always drop the RNG in hwrng_unregister()
Dinh Nguyen <dinguyen@kernel.org>
ARM: dts: socfpga: Fix NAND controller node compatible for Arria10
Marek Vasut <marex@denx.de>
ARM: dts: socfpga: Fix NAND controller clock supply
Marek Vasut <marex@denx.de>
ARM: dts: socfpga: Fix NAND controller node compatible
Thor Thayer <thor.thayer@linux.intel.com>
ARM: dts: Fix SPI node for Arria10
Chen-Yu Tsai <wens@csie.org>
ARM: dts: sun8i: h3: fix ALL-H3-CC H3 ver VCC-1V2 regulator voltage
Icenowy Zheng <icenowy@aosc.io>
ARM: dts: sun8i: h3: fix ALL-H3-CC H3 ver VDD-CPUX voltage
David Rivshin <DRivshin@allworx.com>
ARM: 8764/1: kgdb: fix NUMREGBYTES so that gdb_regs[] is the correct size
Vaibhav Jain <vaibhav@linux.ibm.com>
cxl: Disable prefault_mode in Radix mode
Vaibhav Jain <vaibhav@linux.vnet.ibm.com>
cxl: Configure PSL to not use APC virtual machines
Michael Ellerman <mpe@ellerman.id.au>
powerpc/64s: Fix DT CPU features Power9 DD2.1 logic
Michael Jeanson <mjeanson@efficios.com>
powerpc/e500mc: Set assembler machine type to e500mc
Nicholas Piggin <npiggin@gmail.com>
powerpc/64s/radix: Fix radix_kvm_prefetch_workaround paca access of not possible CPU
Finley Xiao <finley.xiao@rock-chips.com>
soc: rockchip: power-domain: Fix wrong value when power up pd with writemask
Ross Zwisler <ross.zwisler@linux.intel.com>
libnvdimm, pmem: Do not flush power-fail protected CPU caches
Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
powerpc/fadump: Unregister fadump on kexec down path.
Gautham R. Shenoy <ego@linux.vnet.ibm.com>
cpuidle: powernv: Fix promotion from snooze if next state disabled
Akshay Adiga <akshay.adiga@linux.vnet.ibm.com>
powerpc/powernv/cpuidle: Init all present cpus for deep states
Haren Myneni <haren@us.ibm.com>
powerpc/powernv: copy/paste - Mask SO bit in CR
Alexey Kardashevskiy <aik@ozlabs.ru>
powerpc/powernv/ioda2: Remove redundant free of TCE pages
Michael Neuling <mikey@neuling.org>
powerpc/ptrace: Fix enforcement of DAWR constraints
Anju T Sudhakar <anju@linux.vnet.ibm.com>
powerpc/perf: Fix memory allocation for core-imc based on num_possible_cpus()
Michael Neuling <mikey@neuling.org>
powerpc/ptrace: Fix setting 512B aligned breakpoints with PTRACE_SET_DEBUGREG
Ram Pai <linuxram@us.ibm.com>
powerpc/pkeys: Detach execute_only key on !PROT_EXEC
Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
powerpc/mm/hash: Add missing isync prior to kernel stack SLB switch
Miklos Szeredi <mszeredi@redhat.com>
fuse: fix control dir setup and teardown
Tetsuo Handa <penguin-kernel@I-love.SAKURA.ne.jp>
fuse: don't keep dead fuse_conn at fuse_fill_super().
Miklos Szeredi <mszeredi@redhat.com>
fuse: atomic_o_trunc should truncate pagecache
Tejun Heo <tj@kernel.org>
fuse: fix congested state leak on aborted connections
Tetsuo Handa <penguin-kernel@I-love.SAKURA.ne.jp>
printk: fix possible reuse of va_list variable
Amit Pundir <amit.pundir@linaro.org>
Bluetooth: hci_qca: Avoid missing rampatch failure with userspace fw loader
Corey Minyard <cminyard@mvista.com>
ipmi:bt: Set the timeout before doing a capabilities check
Mikulas Patocka <mpatocka@redhat.com>
branch-check: fix long->int truncation when profiling branches
Matthias Schiffer <mschiffer@universe-factory.net>
mips: ftrace: fix static function graph tracing
Steven Rostedt (VMware) <rostedt@goodmis.org>
ftrace/selftest: Have the reset_trigger code be a bit more careful
Geert Uytterhoeven <geert+renesas@glider.be>
lib/vsprintf: Remove atomic-unsafe support for %pCr
Geert Uytterhoeven <geert+renesas@glider.be>
clk: renesas: cpg-mssr: Stop using printk format %pCr
Geert Uytterhoeven <geert+renesas@glider.be>
thermal: bcm2835: Stop using printk format %pCr
Alexander Sverdlin <alexander.sverdlin@gmail.com>
ASoC: cirrus: i2s: Fix {TX|RX}LinCtrlData setup
Alexander Sverdlin <alexander.sverdlin@gmail.com>
ASoC: cirrus: i2s: Fix LRCLK configuration
Kai Chieh Chuang <kaichieh.chuang@mediatek.com>
ASoC: mediatek: preallocate pages use platform device
Paul Handrigan <Paul.Handrigan@cirrus.com>
ASoC: cs35l35: Add use_single_rw to regmap config
Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
ASoC: dapm: delete dapm_kcontrol_data paths list before freeing it
Ingo Flaschberger <ingo.flaschberger@gmail.com>
1wire: family module autoload fails because of upper/lower case mismatch.
Maxim Moseychuk <franchesko.salias.hudro.pedros@gmail.com>
usb: do not reset if a low-speed or full-speed device timed out
Wolfram Sang <wsa+renesas@sang-engineering.com>
mmc: renesas_sdhi: really fix WP logic regressions
Waldemar Rymarkiewicz <waldemar.rymarkiewicz@gmail.com>
PM / OPP: Update voltage in case freq == old_freq
Rafael J. Wysocki <rafael.j.wysocki@intel.com>
PM / core: Fix supplier device runtime PM usage counter imbalance
Rafael J. Wysocki <rafael.j.wysocki@intel.com>
ACPI / LPSS: Avoid PM quirks on suspend and resume from S3
Rafael J. Wysocki <rafael.j.wysocki@intel.com>
PCI / PM: Do not clear state_saved for devices that remain suspended
Ulf Hansson <ulf.hansson@linaro.org>
PM / Domains: Fix error path during attach in genpd
Eric W. Biederman <ebiederm@xmission.com>
signal/xtensa: Consistenly use SIGBUS in do_unaligned_user
Daniel Wagner <daniel.wagner@siemens.com>
serial: sh-sci: Use spin_{try}lock_irqsave instead of open coding version
Mika Westerberg <mika.westerberg@linux.intel.com>
mtd: spi-nor: intel-spi: Fix atomic sequence handling
Guenter Roeck <linux@roeck-us.net>
hwmon: (k10temp) Add support for Stoney Ridge and Bristol Ridge CPUs
Dmitry Torokhov <dmitry.torokhov@gmail.com>
platform/chrome: cros_ec_lpc: do not try DMI match when ACPI device found
Finn Thain <fthain@telegraphics.com.au>
m68k/mac: Fix SWIM memory resource end address
Michael Schmitz <schmitzmic@gmail.com>
m68k/mm: Adjust VM area to be unmapped by gap size for __iounmap()
Siarhei Liakh <Siarhei.Liakh@concurrent-rt.com>
x86: Call fixup_exception() before notify_die() in math_error()
Borislav Petkov <bp@suse.de>
x86/mce: Do not overwrite MCi_STATUS in mce_no_way_out()
Tony Luck <tony.luck@intel.com>
x86/mce: Fix incorrect "Machine check from unknown source" message
Tony Luck <tony.luck@intel.com>
x86/mce: Check for alternate indication of machine check recovery on Skylake
Tony Luck <tony.luck@intel.com>
x86/mce: Improve error message when kernel cannot recover
mike.travis@hpe.com <mike.travis@hpe.com>
x86/platform/UV: Add kernel parameter to set memory block size
mike.travis@hpe.com <mike.travis@hpe.com>
x86/platform/UV: Use new set memory block size function
mike.travis@hpe.com <mike.travis@hpe.com>
x86/platform/UV: Add adjustable set memory block size function
Juergen Gross <jgross@suse.com>
x86/xen: Add call of speculative_store_bypass_ht_init() to PV paths
Dan Williams <dan.j.williams@intel.com>
x86/spectre_v1: Disable compiler optimizations over array_index_mask_nospec()
-------------
Diffstat:
Documentation/ABI/testing/sysfs-class-cxl | 4 +-
Documentation/core-api/printk-formats.rst | 3 +-
Makefile | 4 +-
arch/arm/boot/dts/mt7623.dtsi | 3 +-
arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts | 1 +
arch/arm/boot/dts/mt7623n-rfb.dtsi | 1 +
arch/arm/boot/dts/socfpga.dtsi | 4 +-
arch/arm/boot/dts/socfpga_arria10.dtsi | 5 +-
arch/arm/boot/dts/sun8i-h3-libretech-all-h3-cc.dts | 8 +-
arch/arm/include/asm/kgdb.h | 2 +-
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 6 +-
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 6 +
.../dts/amlogic/meson-gxl-s905x-libretech-cc.dts | 3 -
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 8 --
arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 2 +-
arch/arm64/crypto/aes-glue.c | 2 +-
arch/arm64/kernel/cpufeature.c | 2 +-
arch/arm64/kernel/signal.c | 5 +-
arch/arm64/mm/proc.S | 5 +-
arch/m68k/mac/config.c | 2 +-
arch/m68k/mm/kmap.c | 3 +-
arch/mips/ath79/mach-pb44.c | 2 +-
arch/mips/bcm47xx/setup.c | 6 +
arch/mips/include/asm/io.h | 2 +
arch/mips/include/asm/mipsregs.h | 3 +
arch/mips/kernel/mcount.S | 27 ++---
arch/powerpc/Makefile | 1 +
arch/powerpc/kernel/dt_cpu_ftrs.c | 3 +-
arch/powerpc/kernel/entry_64.S | 1 +
arch/powerpc/kernel/fadump.c | 3 +
arch/powerpc/kernel/hw_breakpoint.c | 4 +-
arch/powerpc/kernel/ptrace.c | 1 +
arch/powerpc/mm/pkeys.c | 4 +-
arch/powerpc/mm/tlb-radix.c | 2 +
arch/powerpc/perf/imc-pmu.c | 4 +-
arch/powerpc/platforms/powernv/copy-paste.h | 3 +-
arch/powerpc/platforms/powernv/idle.c | 4 +-
arch/powerpc/platforms/powernv/pci-ioda.c | 1 -
arch/um/drivers/vector_kern.c | 20 +++-
arch/x86/entry/entry_64_compat.S | 16 +--
arch/x86/include/asm/barrier.h | 2 +-
arch/x86/kernel/apic/x2apic_uv_x.c | 60 +++++++++-
arch/x86/kernel/cpu/mcheck/mce-severity.c | 5 +
arch/x86/kernel/cpu/mcheck/mce.c | 44 +++++---
arch/x86/kernel/e820.c | 15 ++-
arch/x86/kernel/quirks.c | 11 +-
arch/x86/kernel/traps.c | 14 ++-
arch/x86/mm/init.c | 4 +-
arch/x86/mm/init_64.c | 20 +++-
arch/x86/platform/efi/efi_64.c | 4 +-
arch/x86/xen/smp_pv.c | 5 +
arch/xtensa/kernel/traps.c | 2 +-
block/blk-core.c | 4 +
crypto/asymmetric_keys/x509_cert_parser.c | 9 ++
drivers/acpi/acpi_lpss.c | 20 ++--
drivers/auxdisplay/Kconfig | 10 +-
drivers/base/core.c | 15 ++-
drivers/base/power/domain.c | 3 +
drivers/block/rbd.c | 2 +-
drivers/bluetooth/hci_qca.c | 6 +
drivers/char/hw_random/core.c | 11 +-
drivers/char/ipmi/ipmi_bt_sm.c | 3 +-
drivers/char/tpm/tpm-dev-common.c | 40 +++----
drivers/char/tpm/tpm-dev.h | 2 +-
drivers/char/tpm/tpm2-space.c | 3 +-
drivers/clk/at91/clk-pll.c | 13 +--
drivers/clk/clk-aspeed.c | 4 +-
drivers/clk/meson/meson8b.c | 7 ++
drivers/clk/renesas/renesas-cpg-mssr.c | 9 +-
drivers/cpufreq/intel_pstate.c | 27 ++++-
drivers/cpuidle/cpuidle-powernv.c | 32 +++++-
drivers/firmware/efi/libstub/tpm.c | 2 +-
drivers/hwmon/k10temp.c | 5 +
drivers/i2c/algos/i2c-algo-bit.c | 5 -
drivers/i2c/busses/i2c-gpio.c | 4 +-
drivers/iio/accel/sca3000.c | 9 +-
drivers/iio/adc/ad7791.c | 49 --------
drivers/infiniband/core/umem.c | 11 +-
drivers/infiniband/core/uverbs_main.c | 14 ++-
drivers/infiniband/core/verbs.c | 14 ++-
drivers/infiniband/hw/hfi1/chip.c | 8 +-
drivers/infiniband/hw/hfi1/debugfs.c | 8 +-
drivers/infiniband/hw/hfi1/file_ops.c | 4 +-
drivers/infiniband/hw/hfi1/hfi.h | 1 +
drivers/infiniband/hw/hfi1/init.c | 22 +++-
drivers/infiniband/hw/hfi1/pio.c | 44 ++++++--
drivers/infiniband/hw/mlx4/mad.c | 1 -
drivers/infiniband/hw/mlx4/mr.c | 50 +++++++--
drivers/infiniband/hw/mlx5/cq.c | 15 ++-
drivers/infiniband/hw/qib/qib.h | 4 +-
drivers/infiniband/hw/qib/qib_file_ops.c | 10 +-
drivers/infiniband/hw/qib/qib_init.c | 13 +++
drivers/infiniband/hw/qib/qib_user_pages.c | 20 ++--
drivers/infiniband/sw/rdmavt/cq.c | 31 ++++--
drivers/infiniband/ulp/isert/ib_isert.c | 28 +++--
drivers/input/joystick/xpad.c | 2 +-
drivers/input/mouse/elan_i2c.h | 2 +
drivers/input/mouse/elan_i2c_core.c | 3 +-
drivers/input/mouse/elan_i2c_smbus.c | 10 +-
drivers/input/mouse/elantech.c | 11 +-
drivers/input/mouse/psmouse-base.c | 12 +-
drivers/input/touchscreen/silead.c | 1 +
drivers/iommu/Kconfig | 1 -
drivers/iommu/amd_iommu.c | 68 ++++++++----
drivers/irqchip/irq-gic-v3-its.c | 9 +-
drivers/md/dm-thin.c | 11 +-
drivers/md/dm-zoned-target.c | 2 +-
drivers/md/dm.c | 5 +-
drivers/md/md.c | 4 +-
drivers/media/dvb-core/dvb_frontend.c | 23 ++--
drivers/media/platform/vsp1/vsp1_video.c | 21 ++--
drivers/media/rc/ir-mce_kbd-decoder.c | 2 +
drivers/media/usb/cx231xx/cx231xx-cards.c | 3 +
drivers/media/usb/cx231xx/cx231xx-dvb.c | 2 +-
drivers/media/usb/uvc/uvc_video.c | 24 +++-
drivers/media/v4l2-core/v4l2-compat-ioctl32.c | 2 +-
drivers/mfd/intel-lpss-pci.c | 25 +++--
drivers/mfd/intel-lpss.c | 4 +-
drivers/mfd/twl-core.c | 2 +-
drivers/misc/cxl/pci.c | 4 +-
drivers/misc/cxl/sysfs.c | 16 ++-
drivers/mmc/host/renesas_sdhi_core.c | 5 +
drivers/mmc/host/renesas_sdhi_internal_dmac.c | 1 +
drivers/mmc/host/renesas_sdhi_sys_dmac.c | 3 +
drivers/mtd/chips/cfi_cmdset_0002.c | 21 ++--
drivers/mtd/nand/raw/denali_dt.c | 6 +-
drivers/mtd/nand/raw/mxc_nand.c | 5 +-
drivers/mtd/nand/raw/nand_base.c | 29 ++---
drivers/mtd/nand/raw/nand_macronix.c | 48 ++++++--
drivers/mtd/nand/raw/nand_micron.c | 2 +
drivers/mtd/spi-nor/intel-spi.c | 76 +++++++++++--
drivers/mtd/ubi/build.c | 3 +
drivers/mtd/ubi/eba.c | 90 ++++++++++++++-
drivers/mtd/ubi/wl.c | 4 +-
drivers/net/ethernet/ti/davinci_emac.c | 15 ++-
drivers/nvdimm/bus.c | 14 ++-
drivers/nvdimm/pmem.c | 10 +-
drivers/nvdimm/region_devs.c | 3 +-
drivers/of/platform.c | 5 +-
drivers/of/resolver.c | 5 +
drivers/of/unittest.c | 8 +-
drivers/opp/core.c | 2 +-
drivers/pci/host/pci-hyperv.c | 11 --
drivers/pci/hotplug/pciehp.h | 2 +-
drivers/pci/hotplug/pciehp_core.c | 2 +-
drivers/pci/hotplug/pciehp_hpc.c | 13 ++-
drivers/pci/pci-driver.c | 5 +-
drivers/pci/probe.c | 15 ++-
drivers/pci/quirks.c | 20 ++++
drivers/pinctrl/devicetree.c | 7 +-
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 3 +-
drivers/pinctrl/samsung/pinctrl-exynos-arm.c | 4 +-
drivers/platform/chrome/cros_ec_lpc.c | 13 ++-
drivers/pwm/pwm-lpss-platform.c | 5 +
drivers/pwm/pwm-lpss.c | 30 +++++
drivers/pwm/pwm-lpss.h | 2 +
drivers/remoteproc/qcom_q6v5_pil.c | 10 +-
drivers/rpmsg/qcom_smd.c | 18 +--
drivers/rtc/rtc-sun6i.c | 4 +-
drivers/s390/scsi/zfcp_dbf.c | 40 +++++++
drivers/s390/scsi/zfcp_erp.c | 123 ++++++++++++++++-----
drivers/s390/scsi/zfcp_ext.h | 5 +
drivers/s390/scsi/zfcp_scsi.c | 18 ++-
drivers/scsi/hpsa.c | 10 +-
drivers/scsi/qla2xxx/qla_gs.c | 4 +-
drivers/scsi/qla2xxx/qla_init.c | 3 +-
drivers/scsi/qla2xxx/qla_isr.c | 8 +-
drivers/scsi/qla2xxx/qla_target.c | 7 +-
drivers/scsi/scsi_debug.c | 2 +-
drivers/soc/rockchip/pm_domains.c | 2 +-
drivers/thermal/broadcom/bcm2835_thermal.c | 4 +-
drivers/tty/serial/sh-sci.c | 8 +-
drivers/usb/core/hub.c | 4 +-
drivers/video/backlight/as3711_bl.c | 33 ++++--
drivers/video/backlight/max8925_bl.c | 4 +-
drivers/video/backlight/tps65217_bl.c | 4 +-
drivers/video/fbdev/uvesafb.c | 3 +-
drivers/virt/vboxguest/vboxguest_linux.c | 4 +-
drivers/w1/w1.c | 2 +-
drivers/xen/events/events_base.c | 2 -
fs/btrfs/inode.c | 4 +-
fs/f2fs/checkpoint.c | 4 +-
fs/f2fs/inode.c | 4 +-
fs/f2fs/segment.c | 3 +
fs/f2fs/segment.h | 1 +
fs/fuse/control.c | 13 ++-
fs/fuse/dev.c | 3 +-
fs/fuse/dir.c | 13 ++-
fs/fuse/inode.c | 1 +
fs/nfs/callback_proc.c | 7 +-
fs/nfs/nfs4idmap.c | 5 +-
fs/nfs/nfs4proc.c | 2 +-
fs/nfsd/nfs4xdr.c | 5 +-
fs/ubifs/journal.c | 5 +-
fs/udf/directory.c | 3 +
include/dt-bindings/clock/aspeed-clock.h | 2 +-
include/linux/blkdev.h | 4 +-
include/linux/compiler.h | 2 +-
include/linux/memory.h | 1 +
include/linux/slub_def.h | 4 +
include/rdma/ib_verbs.h | 27 ++++-
include/rdma/rdma_vt.h | 2 +-
kernel/locking/rwsem.c | 1 +
kernel/printk/printk_safe.c | 5 +-
kernel/softirq.c | 6 +-
kernel/time/time.c | 6 +-
kernel/trace/trace_events_filter.c | 10 +-
lib/Kconfig.kasan | 1 +
lib/vsprintf.c | 3 -
mm/gup.c | 36 ++++--
mm/ksm.c | 14 ++-
mm/slab_common.c | 4 +
mm/slub.c | 7 +-
net/sunrpc/xprtrdma/rpc_rdma.c | 2 +-
security/selinux/selinuxfs.c | 78 ++++++-------
sound/core/timer.c | 2 +-
sound/pci/hda/hda_codec.c | 5 +-
sound/pci/hda/hda_codec.h | 1 +
sound/pci/hda/patch_hdmi.c | 5 +
sound/pci/hda/patch_realtek.c | 20 +++-
sound/soc/cirrus/edb93xx.c | 2 +-
sound/soc/cirrus/ep93xx-i2s.c | 26 +++--
sound/soc/cirrus/snappercl15.c | 2 +-
sound/soc/codecs/cs35l35.c | 1 +
.../soc/mediatek/common/mtk-afe-platform-driver.c | 4 +-
sound/soc/soc-dapm.c | 2 +
tools/perf/util/dso.c | 2 +
.../perf/util/intel-pt-decoder/intel-pt-decoder.c | 23 +++-
.../perf/util/intel-pt-decoder/intel-pt-decoder.h | 9 ++
.../util/intel-pt-decoder/intel-pt-pkt-decoder.c | 2 +-
tools/perf/util/intel-pt.c | 5 +
tools/testing/selftests/ftrace/test.d/functions | 21 +++-
232 files changed, 1706 insertions(+), 756 deletions(-)
^ permalink raw reply [relevance 2%]
* [PATCH 4.17 165/220] remoteproc: Prevent incorrect rproc state on xfer mem ownership failure
2018-07-01 16:20 2% [PATCH 4.17 000/220] 4.17.4-stable review Greg Kroah-Hartman
@ 2018-07-01 16:23 8% ` Greg Kroah-Hartman
0 siblings, 0 replies; 200+ results
From: Greg Kroah-Hartman @ 2018-07-01 16:23 UTC (permalink / raw)
To: linux-kernel; +Cc: Greg Kroah-Hartman, stable, Sibi Sankar, Bjorn Andersson
4.17-stable review patch. If anyone has any objections, please let me know.
------------------
From: Sibi Sankar <sibis@codeaurora.org>
commit 2724807f7f70a6a3e67b3f6bf921cc77ed39c8a1 upstream.
Any failure in the secure call for transferring mem ownership of mba
region to Q6 would result in reporting that the remoteproc device
is running. This is because the previous q6v5_clk_enable would have
been a success. Prevent this by updating variable 'ret' accordingly.
Cc: stable@vger.kernel.org
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
drivers/remoteproc/qcom_q6v5_pil.c | 10 ++++------
1 file changed, 4 insertions(+), 6 deletions(-)
--- a/drivers/remoteproc/qcom_q6v5_pil.c
+++ b/drivers/remoteproc/qcom_q6v5_pil.c
@@ -761,13 +761,11 @@ static int q6v5_start(struct rproc *rpro
}
/* Assign MBA image access in DDR to q6 */
- xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true,
- qproc->mba_phys,
- qproc->mba_size);
- if (xfermemop_ret) {
+ ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true,
+ qproc->mba_phys, qproc->mba_size);
+ if (ret) {
dev_err(qproc->dev,
- "assigning Q6 access to mba memory failed: %d\n",
- xfermemop_ret);
+ "assigning Q6 access to mba memory failed: %d\n", ret);
goto disable_active_clks;
}
^ permalink raw reply [relevance 8%]
* Re: [PATCH v6 1/8] dt-bindings: reset: Add AOSS reset bindings for SDM845 SoCs
2018-06-27 14:24 19% [PATCH v6 1/8] dt-bindings: reset: Add AOSS reset bindings for SDM845 SoCs Sibi Sankar
2018-06-27 14:24 17% ` [PATCH v6 2/8] reset: qcom: AOSS (always on subsystem) reset controller Sibi Sankar
2018-06-27 16:47 0% ` [PATCH v6 1/8] dt-bindings: reset: Add AOSS reset bindings for SDM845 SoCs Bjorn Andersson
@ 2018-07-03 2:32 0% ` Rob Herring
2018-07-16 10:19 0% ` Philipp Zabel
3 siblings, 0 replies; 200+ results
From: Rob Herring @ 2018-07-03 2:32 UTC (permalink / raw)
To: Sibi Sankar
Cc: p.zabel, bjorn.andersson, linux-kernel, devicetree, mark.rutland,
kyan, akdwived, linux-arm-msm, tsoni
On Wed, Jun 27, 2018 at 07:54:42PM +0530, Sibi Sankar wrote:
> Add SDM845 AOSS (always on subsystem) reset controller binding
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
>
> Not including Rob's earlier Reviewed-by due to change in compatible
>
> .../bindings/reset/qcom,aoss-reset.txt | 52 +++++++++++++++++++
> include/dt-bindings/reset/qcom,sdm845-aoss.h | 17 ++++++
> 2 files changed, 69 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
> create mode 100644 include/dt-bindings/reset/qcom,sdm845-aoss.h
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [relevance 0%]
* [PATCH] remoteproc: qcom: q6v5-pil: fix modem hang on SDM845 after axis2 clk unvote
@ 2018-07-09 15:12 20% Sibi Sankar
2018-07-10 21:09 0% ` Bjorn Andersson
0 siblings, 1 reply; 200+ results
From: Sibi Sankar @ 2018-07-09 15:12 UTC (permalink / raw)
To: bjorn.andersson
Cc: linux-remoteproc, linux-kernel, ohad, kyan, sricharan, akdwived,
linux-arm-msm, tsoni, Sibi Sankar
GCC_MSS_AXIS2 clock is used for disabling boot IMEM (a part of
AP boot up). With Boot IMEM disable now a part TZ/ATF, AXIS2
clock is no longer required post AP boot up and expected to
remain untouched. However if the clock is turned ON after Q6
is brought out of reset and later turned off, it results in
modem hang. When Q6 attempts a power collapse the internal
handshaking to check if AXIS2 is idle never goes through since
it is turned off preventing the RSC from getting triggered,
leaving modem in a funky state. Hence removing AXIS2 clk
enable/disable from the driver.
[bjorn: identified unvoting axis2 clk caused modem hang]
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
drivers/remoteproc/qcom_q6v5_pil.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
index e04319573c91..d7a4b9eca5d2 100644
--- a/drivers/remoteproc/qcom_q6v5_pil.c
+++ b/drivers/remoteproc/qcom_q6v5_pil.c
@@ -1243,7 +1243,6 @@ static const struct rproc_hexagon_res sdm845_mss = {
.hexagon_mba_image = "mba.mbn",
.proxy_clk_names = (char*[]){
"xo",
- "axis2",
"prng",
NULL
},
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 20%]
* Re: [PATCH] remoteproc: qcom: q6v5-pil: fix modem hang on SDM845 after axis2 clk unvote
2018-07-09 15:12 20% [PATCH] remoteproc: qcom: q6v5-pil: fix modem hang on SDM845 after axis2 clk unvote Sibi Sankar
@ 2018-07-10 21:09 0% ` Bjorn Andersson
0 siblings, 0 replies; 200+ results
From: Bjorn Andersson @ 2018-07-10 21:09 UTC (permalink / raw)
To: Sibi Sankar
Cc: linux-remoteproc, linux-kernel, ohad, kyan, sricharan, akdwived,
linux-arm-msm, tsoni
On Mon 09 Jul 08:12 PDT 2018, Sibi Sankar wrote:
> GCC_MSS_AXIS2 clock is used for disabling boot IMEM (a part of
> AP boot up). With Boot IMEM disable now a part TZ/ATF, AXIS2
> clock is no longer required post AP boot up and expected to
> remain untouched. However if the clock is turned ON after Q6
> is brought out of reset and later turned off, it results in
> modem hang. When Q6 attempts a power collapse the internal
> handshaking to check if AXIS2 is idle never goes through since
> it is turned off preventing the RSC from getting triggered,
> leaving modem in a funky state. Hence removing AXIS2 clk
> enable/disable from the driver.
>
> [bjorn: identified unvoting axis2 clk caused modem hang]
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Thanks Sibi
Regards,
Bjorn
> ---
> drivers/remoteproc/qcom_q6v5_pil.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
> index e04319573c91..d7a4b9eca5d2 100644
> --- a/drivers/remoteproc/qcom_q6v5_pil.c
> +++ b/drivers/remoteproc/qcom_q6v5_pil.c
> @@ -1243,7 +1243,6 @@ static const struct rproc_hexagon_res sdm845_mss = {
> .hexagon_mba_image = "mba.mbn",
> .proxy_clk_names = (char*[]){
> "xo",
> - "axis2",
> "prng",
> NULL
> },
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
^ permalink raw reply [relevance 0%]
* Re: [PATCH v6 1/8] dt-bindings: reset: Add AOSS reset bindings for SDM845 SoCs
2018-06-27 14:24 19% [PATCH v6 1/8] dt-bindings: reset: Add AOSS reset bindings for SDM845 SoCs Sibi Sankar
` (2 preceding siblings ...)
2018-07-03 2:32 0% ` Rob Herring
@ 2018-07-16 10:19 0% ` Philipp Zabel
3 siblings, 0 replies; 200+ results
From: Philipp Zabel @ 2018-07-16 10:19 UTC (permalink / raw)
To: Sibi Sankar, robh+dt
Cc: bjorn.andersson, linux-kernel, devicetree, mark.rutland, kyan,
akdwived, linux-arm-msm, tsoni
Hi Sibi,
On Wed, 2018-06-27 at 19:54 +0530, Sibi Sankar wrote:
> Add SDM845 AOSS (always on subsystem) reset controller binding
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
>
> Not including Rob's earlier Reviewed-by due to change in compatible
Thank you, patches 1 and 2 applied to reset/next.
regards
Philipp
^ permalink raw reply [relevance 0%]
* [PATCH v3 0/6] Add coredump support for Q6v5 Modem remoteproc
@ 2018-07-27 15:19 14% Sibi Sankar
2018-07-27 15:19 20% ` [PATCH v3 1/6] remoteproc: Introduce custom dump function for each remoteproc segment Sibi Sankar
` (5 more replies)
0 siblings, 6 replies; 200+ results
From: Sibi Sankar @ 2018-07-27 15:19 UTC (permalink / raw)
To: bjorn.andersson
Cc: linux-remoteproc, linux-kernel, ohad, kyan, sricharan, akdwived,
linux-arm-msm, tsoni, Sibi Sankar
This patch series add coredump support for modem on SDM845, MSM8996
and MSM8916 SoCs. Modem requires the mba to be loaded before a
coredump can be performed and this is achieved using a custom per
segment dump function.
V3:
[bjorn]:replace prepare/unprepare ops with a more generalised per segment
dump function
V2:
Introduce prepare/unprepare ops for rproc coredump
Sibi Sankar (6):
remoteproc: Introduce custom dump function for each remoteproc segment
remoteproc: Add mechanism for custom dump function assignment
remoteproc: qcom: q6v5-pil: Refactor mba load/unload sequence
remoteproc: qcom: q6v5-pil: Add custom dump function for modem
remoteproc: qcom: q6v5-pil: Register segments/dumpfn for coredump
remoteproc: qcom: q6v5-pil: Assign the relocated address
drivers/remoteproc/qcom_q6v5_pil.c | 307 ++++++++++++++++++---------
drivers/remoteproc/remoteproc_core.c | 52 ++++-
include/linux/remoteproc.h | 8 +
3 files changed, 264 insertions(+), 103 deletions(-)
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [relevance 14%]
* [PATCH v3 1/6] remoteproc: Introduce custom dump function for each remoteproc segment
2018-07-27 15:19 14% [PATCH v3 0/6] Add coredump support for Q6v5 Modem remoteproc Sibi Sankar
@ 2018-07-27 15:19 20% ` Sibi Sankar
2018-08-07 6:15 0% ` Vinod
2018-10-08 6:23 0% ` Bjorn Andersson
2018-07-27 15:19 19% ` [PATCH v3 2/6] remoteproc: Add mechanism for custom dump function assignment Sibi Sankar
` (4 subsequent siblings)
5 siblings, 2 replies; 200+ results
From: Sibi Sankar @ 2018-07-27 15:19 UTC (permalink / raw)
To: bjorn.andersson
Cc: linux-remoteproc, linux-kernel, ohad, kyan, sricharan, akdwived,
linux-arm-msm, tsoni, Sibi Sankar
Introduce custom dump function per remoteproc segment. It is responsible
for filling the device memory segment associated with coredump
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
drivers/remoteproc/remoteproc_core.c | 15 ++++++++++-----
include/linux/remoteproc.h | 3 +++
2 files changed, 13 insertions(+), 5 deletions(-)
diff --git a/drivers/remoteproc/remoteproc_core.c b/drivers/remoteproc/remoteproc_core.c
index 283b258f5e0f..ec56cd822b26 100644
--- a/drivers/remoteproc/remoteproc_core.c
+++ b/drivers/remoteproc/remoteproc_core.c
@@ -1183,13 +1183,18 @@ static void rproc_coredump(struct rproc *rproc)
phdr->p_align = 0;
ptr = rproc_da_to_va(rproc, segment->da, segment->size);
- if (!ptr) {
- dev_err(&rproc->dev,
+
+ if (segment->dump) {
+ segment->dump(rproc, ptr, segment->size, data + offset);
+ } else {
+ if (!ptr) {
+ dev_err(&rproc->dev,
"invalid coredump segment (%pad, %zu)\n",
&segment->da, segment->size);
- memset(data + offset, 0xff, segment->size);
- } else {
- memcpy(data + offset, ptr, segment->size);
+ memset(data + offset, 0xff, segment->size);
+ } else {
+ memcpy(data + offset, ptr, segment->size);
+ }
}
offset += phdr->p_filesz;
diff --git a/include/linux/remoteproc.h b/include/linux/remoteproc.h
index e3c5d856b6da..0fbb01a9955c 100644
--- a/include/linux/remoteproc.h
+++ b/include/linux/remoteproc.h
@@ -399,6 +399,8 @@ enum rproc_crash_type {
* @node: list node related to the rproc segment list
* @da: device address of the segment
* @size: size of the segment
+ * @dump: custom dump function to fill device memory segment associated
+ * with coredump
*/
struct rproc_dump_segment {
struct list_head node;
@@ -406,6 +408,7 @@ struct rproc_dump_segment {
dma_addr_t da;
size_t size;
+ void (*dump)(struct rproc *rproc, void *ptr, size_t len, void *priv);
loff_t offset;
};
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 20%]
* [PATCH v3 2/6] remoteproc: Add mechanism for custom dump function assignment
2018-07-27 15:19 14% [PATCH v3 0/6] Add coredump support for Q6v5 Modem remoteproc Sibi Sankar
2018-07-27 15:19 20% ` [PATCH v3 1/6] remoteproc: Introduce custom dump function for each remoteproc segment Sibi Sankar
@ 2018-07-27 15:19 19% ` Sibi Sankar
2018-07-27 15:20 15% ` [PATCH v3 3/6] remoteproc: qcom: q6v5-pil: Refactor mba load/unload sequence Sibi Sankar
` (3 subsequent siblings)
5 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2018-07-27 15:19 UTC (permalink / raw)
To: bjorn.andersson
Cc: linux-remoteproc, linux-kernel, ohad, kyan, sricharan, akdwived,
linux-arm-msm, tsoni, Sibi Sankar
This patch adds a mechanism for assigning each rproc segment with
a custom dump function. It is to be called for each rproc segment
during coredump if assigned.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
drivers/remoteproc/remoteproc_core.c | 37 ++++++++++++++++++++++++++++
include/linux/remoteproc.h | 5 ++++
2 files changed, 42 insertions(+)
diff --git a/drivers/remoteproc/remoteproc_core.c b/drivers/remoteproc/remoteproc_core.c
index ec56cd822b26..3d70b7dd1f18 100644
--- a/drivers/remoteproc/remoteproc_core.c
+++ b/drivers/remoteproc/remoteproc_core.c
@@ -1120,6 +1120,43 @@ int rproc_coredump_add_segment(struct rproc *rproc, dma_addr_t da, size_t size)
}
EXPORT_SYMBOL(rproc_coredump_add_segment);
+/**
+ * rproc_coredump_add_custom_segment() - add segment of device memory to
+ * coredump and extend it with custom
+ * dump function
+ * @rproc: handle of a remote processor
+ * @da: device address
+ * @size: size of segment
+ * @dumpfn: custom dump function called for each segment during coredump
+ *
+ * Add device memory to the list of segments to be included in a coredump for
+ * the remoteproc and associate the segment with the given custom dump
+ * function.
+ *
+ * Return: 0 on success, negative errno on error.
+ */
+int rproc_coredump_add_custom_segment(struct rproc *rproc,
+ dma_addr_t da, size_t size,
+ void (*dumpfn)(struct rproc *rproc,
+ void *ptr, size_t len,
+ void *priv))
+{
+ struct rproc_dump_segment *segment;
+
+ segment = kzalloc(sizeof(*segment), GFP_KERNEL);
+ if (!segment)
+ return -ENOMEM;
+
+ segment->da = da;
+ segment->size = size;
+ segment->dump = dumpfn;
+
+ list_add_tail(&segment->node, &rproc->dump_segments);
+
+ return 0;
+}
+EXPORT_SYMBOL(rproc_coredump_add_custom_segment);
+
/**
* rproc_coredump() - perform coredump
* @rproc: rproc handle
diff --git a/include/linux/remoteproc.h b/include/linux/remoteproc.h
index 0fbb01a9955c..5a1ad008ec28 100644
--- a/include/linux/remoteproc.h
+++ b/include/linux/remoteproc.h
@@ -560,6 +560,11 @@ int rproc_boot(struct rproc *rproc);
void rproc_shutdown(struct rproc *rproc);
void rproc_report_crash(struct rproc *rproc, enum rproc_crash_type type);
int rproc_coredump_add_segment(struct rproc *rproc, dma_addr_t da, size_t size);
+int rproc_coredump_add_custom_segment(struct rproc *rproc,
+ dma_addr_t da, size_t size,
+ void (*dumpfn)(struct rproc *rproc,
+ void *ptr, size_t len,
+ void *priv));
static inline struct rproc_vdev *vdev_to_rvdev(struct virtio_device *vdev)
{
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 19%]
* [PATCH v3 3/6] remoteproc: qcom: q6v5-pil: Refactor mba load/unload sequence
2018-07-27 15:19 14% [PATCH v3 0/6] Add coredump support for Q6v5 Modem remoteproc Sibi Sankar
2018-07-27 15:19 20% ` [PATCH v3 1/6] remoteproc: Introduce custom dump function for each remoteproc segment Sibi Sankar
2018-07-27 15:19 19% ` [PATCH v3 2/6] remoteproc: Add mechanism for custom dump function assignment Sibi Sankar
@ 2018-07-27 15:20 15% ` Sibi Sankar
2018-07-27 15:20 20% ` [PATCH v3 4/6] remoteproc: qcom: q6v5-pil: Add custom dump function for modem Sibi Sankar
` (2 subsequent siblings)
5 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2018-07-27 15:20 UTC (permalink / raw)
To: bjorn.andersson
Cc: linux-remoteproc, linux-kernel, ohad, kyan, sricharan, akdwived,
linux-arm-msm, tsoni, Sibi Sankar
Refactor re-useable parts of mba load/unload sequence into mba_load and
mba_reclaim respectively and introduce mba_load flag. This is done in
order to prevent code duplication for modem coredump which requires the
mba to be loaded.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
drivers/remoteproc/qcom_q6v5_pil.c | 243 +++++++++++++++++------------
1 file changed, 144 insertions(+), 99 deletions(-)
diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
index d7a4b9eca5d2..eacf9f0bf49e 100644
--- a/drivers/remoteproc/qcom_q6v5_pil.c
+++ b/drivers/remoteproc/qcom_q6v5_pil.c
@@ -165,6 +165,7 @@ struct q6v5 {
int proxy_reg_count;
bool running;
+ bool mba_loaded;
phys_addr_t mba_phys;
void *mba_region;
@@ -669,6 +670,145 @@ static bool q6v5_phdr_valid(const struct elf32_phdr *phdr)
return true;
}
+static int q6v5_mba_load(struct q6v5 *qproc)
+{
+ int ret;
+ int xfermemop_ret;
+
+ ret = q6v5_regulator_enable(qproc, qproc->proxy_regs,
+ qproc->proxy_reg_count);
+ if (ret) {
+ dev_err(qproc->dev, "failed to enable proxy supplies\n");
+ return ret;
+ }
+
+ ret = q6v5_clk_enable(qproc->dev, qproc->proxy_clks,
+ qproc->proxy_clk_count);
+ if (ret) {
+ dev_err(qproc->dev, "failed to enable proxy clocks\n");
+ goto disable_proxy_reg;
+ }
+
+ ret = q6v5_regulator_enable(qproc, qproc->active_regs,
+ qproc->active_reg_count);
+ if (ret) {
+ dev_err(qproc->dev, "failed to enable supplies\n");
+ goto disable_proxy_clk;
+ }
+
+ ret = q6v5_clk_enable(qproc->dev, qproc->reset_clks,
+ qproc->reset_clk_count);
+ if (ret) {
+ dev_err(qproc->dev, "failed to enable reset clocks\n");
+ goto disable_vdd;
+ }
+
+ ret = q6v5_reset_deassert(qproc);
+ if (ret) {
+ dev_err(qproc->dev, "failed to deassert mss restart\n");
+ goto disable_reset_clks;
+ }
+
+ ret = q6v5_clk_enable(qproc->dev, qproc->active_clks,
+ qproc->active_clk_count);
+ if (ret) {
+ dev_err(qproc->dev, "failed to enable clocks\n");
+ goto assert_reset;
+ }
+
+ /* Assign MBA image access in DDR to q6 */
+ ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true,
+ qproc->mba_phys, qproc->mba_size);
+ if (ret) {
+ dev_err(qproc->dev,
+ "assigning Q6 access to mba memory failed: %d\n", ret);
+ goto disable_active_clks;
+ }
+
+ writel(qproc->mba_phys, qproc->rmb_base + RMB_MBA_IMAGE_REG);
+
+ ret = q6v5proc_reset(qproc);
+ if (ret)
+ goto reclaim_mba;
+
+ ret = q6v5_rmb_mba_wait(qproc, 0, 5000);
+ if (ret == -ETIMEDOUT) {
+ dev_err(qproc->dev, "MBA boot timed out\n");
+ goto halt_axi_ports;
+ } else if (ret != RMB_MBA_XPU_UNLOCKED &&
+ ret != RMB_MBA_XPU_UNLOCKED_SCRIBBLED) {
+ dev_err(qproc->dev, "MBA returned unexpected status %d\n", ret);
+ ret = -EINVAL;
+ goto halt_axi_ports;
+ }
+
+ qproc->mba_loaded = true;
+ return 0;
+
+halt_axi_ports:
+ q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
+ q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
+ q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
+
+reclaim_mba:
+ xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, false,
+ qproc->mba_phys,
+ qproc->mba_size);
+ if (xfermemop_ret) {
+ dev_err(qproc->dev,
+ "Failed to reclaim mba buffer, system may become unstable\n");
+ }
+
+disable_active_clks:
+ q6v5_clk_disable(qproc->dev, qproc->active_clks,
+ qproc->active_clk_count);
+assert_reset:
+ q6v5_reset_assert(qproc);
+disable_reset_clks:
+ q6v5_clk_disable(qproc->dev, qproc->reset_clks,
+ qproc->reset_clk_count);
+disable_vdd:
+ q6v5_regulator_disable(qproc, qproc->active_regs,
+ qproc->active_reg_count);
+disable_proxy_clk:
+ q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
+ qproc->proxy_clk_count);
+disable_proxy_reg:
+ q6v5_regulator_disable(qproc, qproc->proxy_regs,
+ qproc->proxy_reg_count);
+
+ return ret;
+}
+
+static void q6v5_mba_reclaim(struct q6v5 *qproc)
+{
+ int xfermemop_ret;
+
+ qproc->mba_loaded = false;
+ q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
+ q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
+ q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
+ xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, false,
+ qproc->mba_phys,
+ qproc->mba_size);
+ if (xfermemop_ret) {
+ dev_err(qproc->dev,
+ "Failed to reclaim mba buffer, system may become unstable\n");
+ }
+
+ q6v5_clk_disable(qproc->dev, qproc->active_clks,
+ qproc->active_clk_count);
+ q6v5_reset_assert(qproc);
+ q6v5_clk_disable(qproc->dev, qproc->reset_clks,
+ qproc->reset_clk_count);
+ q6v5_regulator_disable(qproc, qproc->active_regs,
+ qproc->active_reg_count);
+ q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
+ qproc->proxy_clk_count);
+ q6v5_regulator_disable(qproc, qproc->proxy_regs,
+ qproc->proxy_reg_count);
+}
+
static int q6v5_mpss_load(struct q6v5 *qproc)
{
const struct elf32_phdr *phdrs;
@@ -792,72 +932,9 @@ static int q6v5_start(struct rproc *rproc)
qcom_q6v5_prepare(&qproc->q6v5);
- ret = q6v5_regulator_enable(qproc, qproc->proxy_regs,
- qproc->proxy_reg_count);
- if (ret) {
- dev_err(qproc->dev, "failed to enable proxy supplies\n");
- goto disable_irqs;
- }
-
- ret = q6v5_clk_enable(qproc->dev, qproc->proxy_clks,
- qproc->proxy_clk_count);
- if (ret) {
- dev_err(qproc->dev, "failed to enable proxy clocks\n");
- goto disable_proxy_reg;
- }
-
- ret = q6v5_regulator_enable(qproc, qproc->active_regs,
- qproc->active_reg_count);
- if (ret) {
- dev_err(qproc->dev, "failed to enable supplies\n");
- goto disable_proxy_clk;
- }
-
- ret = q6v5_clk_enable(qproc->dev, qproc->reset_clks,
- qproc->reset_clk_count);
- if (ret) {
- dev_err(qproc->dev, "failed to enable reset clocks\n");
- goto disable_vdd;
- }
-
- ret = q6v5_reset_deassert(qproc);
- if (ret) {
- dev_err(qproc->dev, "failed to deassert mss restart\n");
- goto disable_reset_clks;
- }
-
- ret = q6v5_clk_enable(qproc->dev, qproc->active_clks,
- qproc->active_clk_count);
- if (ret) {
- dev_err(qproc->dev, "failed to enable clocks\n");
- goto assert_reset;
- }
-
- /* Assign MBA image access in DDR to q6 */
- ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true,
- qproc->mba_phys, qproc->mba_size);
- if (ret) {
- dev_err(qproc->dev,
- "assigning Q6 access to mba memory failed: %d\n", ret);
- goto disable_active_clks;
- }
-
- writel(qproc->mba_phys, qproc->rmb_base + RMB_MBA_IMAGE_REG);
-
- ret = q6v5proc_reset(qproc);
+ ret = q6v5_mba_load(qproc);
if (ret)
- goto reclaim_mba;
-
- ret = q6v5_rmb_mba_wait(qproc, 0, 5000);
- if (ret == -ETIMEDOUT) {
- dev_err(qproc->dev, "MBA boot timed out\n");
- goto halt_axi_ports;
- } else if (ret != RMB_MBA_XPU_UNLOCKED &&
- ret != RMB_MBA_XPU_UNLOCKED_SCRIBBLED) {
- dev_err(qproc->dev, "MBA returned unexpected status %d\n", ret);
- ret = -EINVAL;
- goto halt_axi_ports;
- }
+ goto disable_irqs;
dev_info(qproc->dev, "MBA booted, loading mpss\n");
@@ -886,40 +963,7 @@ static int q6v5_start(struct rproc *rproc)
false, qproc->mpss_phys,
qproc->mpss_size);
WARN_ON(xfermemop_ret);
-
-halt_axi_ports:
- q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
- q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
- q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
-
-reclaim_mba:
- xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, false,
- qproc->mba_phys,
- qproc->mba_size);
- if (xfermemop_ret) {
- dev_err(qproc->dev,
- "Failed to reclaim mba buffer, system may become unstable\n");
- }
-
-disable_active_clks:
- q6v5_clk_disable(qproc->dev, qproc->active_clks,
- qproc->active_clk_count);
-
-assert_reset:
- q6v5_reset_assert(qproc);
-disable_reset_clks:
- q6v5_clk_disable(qproc->dev, qproc->reset_clks,
- qproc->reset_clk_count);
-disable_vdd:
- q6v5_regulator_disable(qproc, qproc->active_regs,
- qproc->active_reg_count);
-disable_proxy_clk:
- q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
- qproc->proxy_clk_count);
-disable_proxy_reg:
- q6v5_regulator_disable(qproc, qproc->proxy_regs,
- qproc->proxy_reg_count);
-
+ q6v5_mba_reclaim(qproc);
disable_irqs:
qcom_q6v5_unprepare(&qproc->q6v5);
@@ -933,6 +977,7 @@ static int q6v5_stop(struct rproc *rproc)
u32 val;
qproc->running = false;
+ qproc->mba_loaded = false;
ret = qcom_q6v5_request_stop(&qproc->q6v5);
if (ret == -ETIMEDOUT)
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 15%]
* [PATCH v3 4/6] remoteproc: qcom: q6v5-pil: Add custom dump function for modem
2018-07-27 15:19 14% [PATCH v3 0/6] Add coredump support for Q6v5 Modem remoteproc Sibi Sankar
` (2 preceding siblings ...)
2018-07-27 15:20 15% ` [PATCH v3 3/6] remoteproc: qcom: q6v5-pil: Refactor mba load/unload sequence Sibi Sankar
@ 2018-07-27 15:20 20% ` Sibi Sankar
2018-07-27 15:20 20% ` [PATCH v3 5/6] remoteproc: qcom: q6v5-pil: Register segments/dumpfn for coredump Sibi Sankar
2018-07-27 15:20 21% ` [PATCH v3 6/6] remoteproc: qcom: q6v5-pil: Assign the relocated address Sibi Sankar
5 siblings, 1 reply; 200+ results
From: Sibi Sankar @ 2018-07-27 15:20 UTC (permalink / raw)
To: bjorn.andersson
Cc: linux-remoteproc, linux-kernel, ohad, kyan, sricharan, akdwived,
linux-arm-msm, tsoni, Sibi Sankar
The per segment dump function is responsible for loading the mba
before device memory segments associated with coredump can be populated
and for cleaning up the resources post coredump.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
drivers/remoteproc/qcom_q6v5_pil.c | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
index eacf9f0bf49e..ac3342f9ea5a 100644
--- a/drivers/remoteproc/qcom_q6v5_pil.c
+++ b/drivers/remoteproc/qcom_q6v5_pil.c
@@ -182,6 +182,7 @@ struct q6v5 {
struct qcom_sysmon *sysmon;
bool need_mem_protection;
bool has_alt_reset;
+ u32 valid_mask;
int mpss_perm;
int mba_perm;
int version;
@@ -924,6 +925,30 @@ static int q6v5_mpss_load(struct q6v5 *qproc)
return ret < 0 ? ret : 0;
}
+static void qcom_q6v5_dump_segment(struct rproc *rproc, void *ptr, size_t len,
+ void *priv)
+{
+ int ret = 0;
+ struct q6v5 *qproc = (struct q6v5 *)rproc->priv;
+ static u32 pending_mask;
+
+ /* Unlock mba before copying segments */
+ if (!qproc->mba_loaded)
+ ret = q6v5_mba_load(qproc);
+
+ if (!ptr || ret)
+ memset(priv, 0xff, len);
+ else
+ memcpy(priv, ptr, len);
+
+ pending_mask++;
+ if (pending_mask == qproc->valid_mask) {
+ if (qproc->mba_loaded)
+ q6v5_mba_reclaim(qproc);
+ pending_mask = 0;
+ }
+}
+
static int q6v5_start(struct rproc *rproc)
{
struct q6v5 *qproc = (struct q6v5 *)rproc->priv;
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 20%]
* [PATCH v3 5/6] remoteproc: qcom: q6v5-pil: Register segments/dumpfn for coredump
2018-07-27 15:19 14% [PATCH v3 0/6] Add coredump support for Q6v5 Modem remoteproc Sibi Sankar
` (3 preceding siblings ...)
2018-07-27 15:20 20% ` [PATCH v3 4/6] remoteproc: qcom: q6v5-pil: Add custom dump function for modem Sibi Sankar
@ 2018-07-27 15:20 20% ` Sibi Sankar
2018-10-08 6:48 0% ` Bjorn Andersson
2018-07-27 15:20 21% ` [PATCH v3 6/6] remoteproc: qcom: q6v5-pil: Assign the relocated address Sibi Sankar
5 siblings, 1 reply; 200+ results
From: Sibi Sankar @ 2018-07-27 15:20 UTC (permalink / raw)
To: bjorn.andersson
Cc: linux-remoteproc, linux-kernel, ohad, kyan, sricharan, akdwived,
linux-arm-msm, tsoni, Sibi Sankar
Register the MDT segments and custom dumpfn with the remoteproc core
dump functionality.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
drivers/remoteproc/qcom_q6v5_pil.c | 40 ++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
index ac3342f9ea5a..22bb049c3e7f 100644
--- a/drivers/remoteproc/qcom_q6v5_pil.c
+++ b/drivers/remoteproc/qcom_q6v5_pil.c
@@ -1058,10 +1058,50 @@ static void *q6v5_da_to_va(struct rproc *rproc, u64 da, int len)
return qproc->mpss_region + offset;
}
+static int qcom_q6v5_register_dump_segments(struct rproc *rproc,
+ const struct firmware *fw_unused)
+{
+ const struct firmware *fw;
+ const struct elf32_phdr *phdrs;
+ const struct elf32_phdr *phdr;
+ const struct elf32_hdr *ehdr;
+ struct q6v5 *qproc = (struct q6v5 *)rproc->priv;
+ int ret;
+ int i;
+
+ ret = request_firmware(&fw, "modem.mdt", qproc->dev);
+ if (ret < 0) {
+ dev_err(qproc->dev, "unable to load modem.mdt\n");
+ return ret;
+ }
+
+ qproc->valid_mask = 0;
+ ehdr = (struct elf32_hdr *)fw->data;
+ phdrs = (struct elf32_phdr *)(ehdr + 1);
+
+ for (i = 0; i < ehdr->e_phnum; i++) {
+ phdr = &phdrs[i];
+
+ if (!q6v5_phdr_valid(phdr))
+ continue;
+
+ ret = rproc_coredump_add_custom_segment(rproc, phdr->p_paddr,
+ phdr->p_memsz, qcom_q6v5_dump_segment);
+ if (ret)
+ break;
+
+ qproc->valid_mask++;
+ }
+
+ release_firmware(fw);
+ return ret;
+}
+
static const struct rproc_ops q6v5_ops = {
.start = q6v5_start,
.stop = q6v5_stop,
.da_to_va = q6v5_da_to_va,
+ .parse_fw = qcom_q6v5_register_dump_segments,
.load = q6v5_load,
};
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 20%]
* [PATCH v3 6/6] remoteproc: qcom: q6v5-pil: Assign the relocated address
2018-07-27 15:19 14% [PATCH v3 0/6] Add coredump support for Q6v5 Modem remoteproc Sibi Sankar
` (4 preceding siblings ...)
2018-07-27 15:20 20% ` [PATCH v3 5/6] remoteproc: qcom: q6v5-pil: Register segments/dumpfn for coredump Sibi Sankar
@ 2018-07-27 15:20 21% ` Sibi Sankar
2018-10-08 6:55 0% ` Bjorn Andersson
5 siblings, 1 reply; 200+ results
From: Sibi Sankar @ 2018-07-27 15:20 UTC (permalink / raw)
To: bjorn.andersson
Cc: linux-remoteproc, linux-kernel, ohad, kyan, sricharan, akdwived,
linux-arm-msm, tsoni, Sibi Sankar
Assign the relocated base of the modem image, as the offsets
from the virtual memory might not be based on the physical
address.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
drivers/remoteproc/qcom_q6v5_pil.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
index 22bb049c3e7f..b1296d614b8b 100644
--- a/drivers/remoteproc/qcom_q6v5_pil.c
+++ b/drivers/remoteproc/qcom_q6v5_pil.c
@@ -862,6 +862,7 @@ static int q6v5_mpss_load(struct q6v5 *qproc)
}
mpss_reloc = relocate ? min_addr : qproc->mpss_phys;
+ qproc->mpss_reloc = mpss_reloc;
/* Load firmware segments */
for (i = 0; i < ehdr->e_phnum; i++) {
phdr = &phdrs[i];
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 21%]
* [PATCH 1/4] dt-bindings: reset: Add PDC reset binding for SDM845 SoCs
@ 2018-07-27 15:28 19% Sibi Sankar
2018-07-27 15:28 16% ` [PATCH 2/4] reset: qcom: PDC (Power Domain Controller) reset controller Sibi Sankar
` (4 more replies)
0 siblings, 5 replies; 200+ results
From: Sibi Sankar @ 2018-07-27 15:28 UTC (permalink / raw)
To: bjorn.andersson, p.zabel, robh+dt
Cc: linux-remoteproc, linux-kernel, devicetree, ohad, mark.rutland,
sricharan, akdwived, linux-arm-msm, tsoni, Sibi Sankar
Add SDM845 PDC (Power Domain Controller) reset controller binding
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
.../bindings/reset/qcom,pdc-reset.txt | 52 +++++++++++++++++++
include/dt-bindings/reset/qcom,sdm845-pdc.h | 20 +++++++
2 files changed, 72 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/qcom,pdc-reset.txt
create mode 100644 include/dt-bindings/reset/qcom,sdm845-pdc.h
diff --git a/Documentation/devicetree/bindings/reset/qcom,pdc-reset.txt b/Documentation/devicetree/bindings/reset/qcom,pdc-reset.txt
new file mode 100644
index 000000000000..85e159962e08
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/qcom,pdc-reset.txt
@@ -0,0 +1,52 @@
+PDC Reset Controller
+======================================
+
+This binding describes a reset-controller found on PDC-Global(Power Domain
+Controller) block for Qualcomm Technologies Inc SDM845 SoCs.
+
+Required properties:
+- compatible:
+ Usage: required
+ Value type: <string>
+ Definition: must be:
+ "qcom,sdm845-pdc-global"
+
+- reg:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: must specify the base address and size of the register
+ space.
+
+- #reset-cells:
+ Usage: required
+ Value type: <uint>
+ Definition: must be 1; cell entry represents the reset index.
+
+Example:
+
+pdc_reset: reset-controller@b2e0000 {
+ compatible = "qcom,sdm845-pdc-global";
+ reg = <0xb2e0000 0x20000>;
+ #reset-cells = <1>;
+};
+
+PDC reset clients
+======================================
+
+Device nodes that need access to reset lines should
+specify them as a reset phandle in their corresponding node as
+specified in reset.txt.
+
+For list of all valid reset indicies see
+<dt-bindings/reset/qcom,sdm845-pdc.h>
+
+Example:
+
+modem-pil@4080000 {
+ ...
+
+ resets = <&pdc_reset PDC_MODEM_SYNC_RESET>;
+ reset-names = "pdc_restart";
+
+ ...
+};
diff --git a/include/dt-bindings/reset/qcom,sdm845-pdc.h b/include/dt-bindings/reset/qcom,sdm845-pdc.h
new file mode 100644
index 000000000000..53c37f9c319a
--- /dev/null
+++ b/include/dt-bindings/reset/qcom,sdm845-pdc.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_RESET_PDC_SDM_845_H
+#define _DT_BINDINGS_RESET_PDC_SDM_845_H
+
+#define PDC_APPS_SYNC_RESET 0
+#define PDC_SP_SYNC_RESET 1
+#define PDC_AUDIO_SYNC_RESET 2
+#define PDC_SENSORS_SYNC_RESET 3
+#define PDC_AOP_SYNC_RESET 4
+#define PDC_DEBUG_SYNC_RESET 5
+#define PDC_GPU_SYNC_RESET 6
+#define PDC_DISPLAY_SYNC_RESET 7
+#define PDC_COMPUTE_SYNC_RESET 8
+#define PDC_MODEM_SYNC_RESET 9
+
+#endif
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 19%]
* [PATCH 2/4] reset: qcom: PDC (Power Domain Controller) reset controller
2018-07-27 15:28 19% [PATCH 1/4] dt-bindings: reset: Add PDC reset binding for SDM845 SoCs Sibi Sankar
@ 2018-07-27 15:28 16% ` Sibi Sankar
2018-07-31 8:51 0% ` Philipp Zabel
2018-08-21 22:17 0% ` Bjorn Andersson
2018-07-27 15:28 21% ` [PATCH 3/4] remoteproc: qcom: q6v5-pil: Explicitly get mss_restart line Sibi Sankar
` (3 subsequent siblings)
4 siblings, 2 replies; 200+ results
From: Sibi Sankar @ 2018-07-27 15:28 UTC (permalink / raw)
To: bjorn.andersson, p.zabel, robh+dt
Cc: linux-remoteproc, linux-kernel, devicetree, ohad, mark.rutland,
sricharan, akdwived, linux-arm-msm, tsoni, Sibi Sankar
Add reset controller for SDM845 SoC to control reset signals
provided by PDC for Modem, Compute, Display, GPU, Debug, AOP,
Sensors, Audio, SP and APPS
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
drivers/reset/Kconfig | 9 +++
drivers/reset/Makefile | 1 +
drivers/reset/reset-qcom-pdc.c | 139 +++++++++++++++++++++++++++++++++
3 files changed, 149 insertions(+)
create mode 100644 drivers/reset/reset-qcom-pdc.c
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 13d28fdbdbb5..5344e202a630 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -98,6 +98,15 @@ config RESET_QCOM_AOSS
reset signals provided by AOSS for Modem, Venus, ADSP,
GPU, Camera, Wireless, Display subsystem. Otherwise, say N.
+config RESET_QCOM_PDC
+ bool "Qcom PDC Reset Driver"
+ depends on ARCH_QCOM || COMPILE_TEST
+ help
+ This enables the PDC (Power Domain Controller) reset driver
+ for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want
+ to control reset signals provided by PDC for Modem, Compute,
+ Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS.
+
config RESET_SIMPLE
bool "Simple Reset Controller Driver" if COMPILE_TEST
default ARCH_SOCFPGA || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 4243c38228e2..d08e8b90046a 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_RESET_MESON_AUDIO_ARB) += reset-meson-audio-arb.o
obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o
obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o
+obj-$(CONFIG_RESET_QCOM_PDC) += reset-qcom-pdc.o
obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
obj-$(CONFIG_RESET_STM32MP157) += reset-stm32mp1.o
obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
diff --git a/drivers/reset/reset-qcom-pdc.c b/drivers/reset/reset-qcom-pdc.c
new file mode 100644
index 000000000000..64a0041e3452
--- /dev/null
+++ b/drivers/reset/reset-qcom-pdc.c
@@ -0,0 +1,139 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+#include <linux/regmap.h>
+#include <linux/of_device.h>
+#include <dt-bindings/reset/qcom,sdm845-pdc.h>
+
+struct qcom_pdc_reset_map {
+ u8 bit;
+};
+
+struct qcom_pdc_desc {
+ const struct regmap_config *config;
+ const struct qcom_pdc_reset_map *resets;
+ size_t num_resets;
+};
+
+struct qcom_pdc_reset_data {
+ struct reset_controller_dev rcdev;
+ struct regmap *regmap;
+ const struct qcom_pdc_desc *desc;
+};
+
+static const struct regmap_config sdm845_pdc_regmap_config = {
+ .name = "pdc-reset",
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x20000,
+ .fast_io = true,
+};
+
+static const struct qcom_pdc_reset_map sdm845_pdc_resets[] = {
+ [PDC_APPS_SYNC_RESET] = {0},
+ [PDC_SP_SYNC_RESET] = {1},
+ [PDC_AUDIO_SYNC_RESET] = {2},
+ [PDC_SENSORS_SYNC_RESET] = {3},
+ [PDC_AOP_SYNC_RESET] = {4},
+ [PDC_DEBUG_SYNC_RESET] = {5},
+ [PDC_GPU_SYNC_RESET] = {6},
+ [PDC_DISPLAY_SYNC_RESET] = {7},
+ [PDC_COMPUTE_SYNC_RESET] = {8},
+ [PDC_MODEM_SYNC_RESET] = {9},
+};
+
+static const struct qcom_pdc_desc sdm845_pdc_desc = {
+ .config = &sdm845_pdc_regmap_config,
+ .resets = sdm845_pdc_resets,
+ .num_resets = ARRAY_SIZE(sdm845_pdc_resets),
+};
+
+static inline struct qcom_pdc_reset_data *to_qcom_pdc_reset_data(
+ struct reset_controller_dev *rcdev)
+{
+ return container_of(rcdev, struct qcom_pdc_reset_data, rcdev);
+}
+
+static int qcom_pdc_control_assert(struct reset_controller_dev *rcdev,
+ unsigned long idx)
+{
+ struct qcom_pdc_reset_data *data = to_qcom_pdc_reset_data(rcdev);
+ const struct qcom_pdc_reset_map *map = &data->desc->resets[idx];
+
+ return regmap_update_bits(data->regmap, 0x100,
+ BIT(map->bit), BIT(map->bit));
+}
+
+static int qcom_pdc_control_deassert(struct reset_controller_dev *rcdev,
+ unsigned long idx)
+{
+ struct qcom_pdc_reset_data *data = to_qcom_pdc_reset_data(rcdev);
+ const struct qcom_pdc_reset_map *map = &data->desc->resets[idx];
+
+ return regmap_update_bits(data->regmap, 0x100, BIT(map->bit), 0);
+}
+
+static const struct reset_control_ops qcom_pdc_reset_ops = {
+ .assert = qcom_pdc_control_assert,
+ .deassert = qcom_pdc_control_deassert,
+};
+
+static int qcom_pdc_reset_probe(struct platform_device *pdev)
+{
+ struct qcom_pdc_reset_data *data;
+ struct device *dev = &pdev->dev;
+ const struct qcom_pdc_desc *desc;
+ void __iomem *base;
+ struct resource *res;
+
+ desc = of_device_get_match_data(dev);
+ if (!desc)
+ return -EINVAL;
+
+ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ data->desc = desc;
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ data->regmap = devm_regmap_init_mmio(dev, base, desc->config);
+ if (IS_ERR(data->regmap)) {
+ dev_err(dev, "Unable to get pdc-global regmap");
+ return PTR_ERR(data->regmap);
+ }
+
+ data->rcdev.owner = THIS_MODULE;
+ data->rcdev.ops = &qcom_pdc_reset_ops;
+ data->rcdev.nr_resets = desc->num_resets;
+ data->rcdev.of_node = dev->of_node;
+
+ return devm_reset_controller_register(dev, &data->rcdev);
+}
+
+static const struct of_device_id qcom_pdc_reset_of_match[] = {
+ { .compatible = "qcom,sdm845-pdc-global", .data = &sdm845_pdc_desc },
+ {}
+};
+
+static struct platform_driver qcom_pdc_reset_driver = {
+ .probe = qcom_pdc_reset_probe,
+ .driver = {
+ .name = "qcom_pdc_reset",
+ .of_match_table = qcom_pdc_reset_of_match,
+ },
+};
+
+builtin_platform_driver(qcom_pdc_reset_driver);
+
+MODULE_DESCRIPTION("Qualcomm PDC Reset Driver");
+MODULE_LICENSE("GPL v2");
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 16%]
* [PATCH 3/4] remoteproc: qcom: q6v5-pil: Explicitly get mss_restart line
2018-07-27 15:28 19% [PATCH 1/4] dt-bindings: reset: Add PDC reset binding for SDM845 SoCs Sibi Sankar
2018-07-27 15:28 16% ` [PATCH 2/4] reset: qcom: PDC (Power Domain Controller) reset controller Sibi Sankar
@ 2018-07-27 15:28 21% ` Sibi Sankar
2018-07-31 8:57 0% ` Philipp Zabel
2018-07-27 15:28 19% ` [PATCH 4/4] remoteproc: qcom: q6v5-pil: Add PDC restart for modem on SDM845 SoCs Sibi Sankar
` (2 subsequent siblings)
4 siblings, 1 reply; 200+ results
From: Sibi Sankar @ 2018-07-27 15:28 UTC (permalink / raw)
To: bjorn.andersson, p.zabel, robh+dt
Cc: linux-remoteproc, linux-kernel, devicetree, ohad, mark.rutland,
sricharan, akdwived, linux-arm-msm, tsoni, Sibi Sankar
Explicitly get mss_restart to facilitate adding PDC
restart line for modem on SDM845 SoCs
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
drivers/remoteproc/qcom_q6v5_pil.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
index b1296d614b8b..d57fdb34e3dd 100644
--- a/drivers/remoteproc/qcom_q6v5_pil.c
+++ b/drivers/remoteproc/qcom_q6v5_pil.c
@@ -1176,8 +1176,7 @@ static int q6v5_init_clocks(struct device *dev, struct clk **clks,
static int q6v5_init_reset(struct q6v5 *qproc)
{
- qproc->mss_restart = devm_reset_control_get_exclusive(qproc->dev,
- NULL);
+ qproc->mss_restart = devm_reset_control_get(qproc->dev, "mss_restart");
if (IS_ERR(qproc->mss_restart)) {
dev_err(qproc->dev, "failed to acquire mss restart\n");
return PTR_ERR(qproc->mss_restart);
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 21%]
* [PATCH 4/4] remoteproc: qcom: q6v5-pil: Add PDC restart for modem on SDM845 SoCs
2018-07-27 15:28 19% [PATCH 1/4] dt-bindings: reset: Add PDC reset binding for SDM845 SoCs Sibi Sankar
2018-07-27 15:28 16% ` [PATCH 2/4] reset: qcom: PDC (Power Domain Controller) reset controller Sibi Sankar
2018-07-27 15:28 21% ` [PATCH 3/4] remoteproc: qcom: q6v5-pil: Explicitly get mss_restart line Sibi Sankar
@ 2018-07-27 15:28 19% ` Sibi Sankar
2018-07-31 8:54 0% ` Philipp Zabel
` (2 more replies)
2018-07-31 8:42 0% ` [PATCH 1/4] dt-bindings: reset: Add PDC reset binding for " Philipp Zabel
2018-08-21 22:08 0% ` Bjorn Andersson
4 siblings, 3 replies; 200+ results
From: Sibi Sankar @ 2018-07-27 15:28 UTC (permalink / raw)
To: bjorn.andersson, p.zabel, robh+dt
Cc: linux-remoteproc, linux-kernel, devicetree, ohad, mark.rutland,
sricharan, akdwived, linux-arm-msm, tsoni, Sibi Sankar
In the presence of a PDC block working with subsystem RSC,
assert/deassert PDC restart in modem start/stop path.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
.../bindings/remoteproc/qcom,q6v5.txt | 4 +++
drivers/remoteproc/qcom_q6v5_pil.c | 27 ++++++++++++++++---
2 files changed, 27 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
index 601dd9f389aa..124fb1dc6fb8 100644
--- a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
+++ b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
@@ -51,6 +51,8 @@ on the Qualcomm Hexagon core.
Usage: required
Value type: <phandle>
Definition: reference to the reset-controller for the modem sub-system
+ reference to the list of 2 reset-controllers for the modem
+ sub-system on SDM845 SoCs
reference to the list of 3 reset-controllers for the
wcss sub-system
@@ -58,6 +60,8 @@ on the Qualcomm Hexagon core.
Usage: required
Value type: <stringlist>
Definition: must be "mss_restart" for the modem sub-system
+ Definition: must be "mss_restart", "pdc_restart" for the modem
+ sub-system on SDM845 SoCs
Definition: must be "wcss_aon_reset", "wcss_reset", "wcss_q6_reset"
for the wcss syb-system
diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
index d57fdb34e3dd..5be794639fc3 100644
--- a/drivers/remoteproc/qcom_q6v5_pil.c
+++ b/drivers/remoteproc/qcom_q6v5_pil.c
@@ -149,6 +149,7 @@ struct q6v5 {
u32 halt_nc;
struct reset_control *mss_restart;
+ struct reset_control *pdc_restart;
struct qcom_q6v5 q6v5;
@@ -349,10 +350,17 @@ static int q6v5_load(struct rproc *rproc, const struct firmware *fw)
static int q6v5_reset_assert(struct q6v5 *qproc)
{
- if (qproc->has_alt_reset)
- return reset_control_reset(qproc->mss_restart);
- else
- return reset_control_assert(qproc->mss_restart);
+ int ret;
+
+ if (qproc->has_alt_reset) {
+ reset_control_assert(qproc->pdc_restart);
+ ret = reset_control_reset(qproc->mss_restart);
+ reset_control_deassert(qproc->pdc_restart);
+ } else {
+ ret = reset_control_assert(qproc->mss_restart);
+ }
+
+ return ret;
}
static int q6v5_reset_deassert(struct q6v5 *qproc)
@@ -360,9 +368,11 @@ static int q6v5_reset_deassert(struct q6v5 *qproc)
int ret;
if (qproc->has_alt_reset) {
+ reset_control_assert(qproc->pdc_restart);
writel(1, qproc->rmb_base + RMB_MBA_ALT_RESET);
ret = reset_control_reset(qproc->mss_restart);
writel(0, qproc->rmb_base + RMB_MBA_ALT_RESET);
+ reset_control_deassert(qproc->pdc_restart);
} else {
ret = reset_control_deassert(qproc->mss_restart);
}
@@ -1182,6 +1192,15 @@ static int q6v5_init_reset(struct q6v5 *qproc)
return PTR_ERR(qproc->mss_restart);
}
+ if (qproc->has_alt_reset) {
+ qproc->pdc_restart = devm_reset_control_get(qproc->dev,
+ "pdc_restart");
+ if (IS_ERR(qproc->pdc_restart)) {
+ dev_err(qproc->dev, "failed to acquire pdc restart\n");
+ return PTR_ERR(qproc->pdc_restart);
+ }
+ }
+
return 0;
}
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 19%]
* Re: [PATCH 1/4] dt-bindings: reset: Add PDC reset binding for SDM845 SoCs
2018-07-27 15:28 19% [PATCH 1/4] dt-bindings: reset: Add PDC reset binding for SDM845 SoCs Sibi Sankar
` (2 preceding siblings ...)
2018-07-27 15:28 19% ` [PATCH 4/4] remoteproc: qcom: q6v5-pil: Add PDC restart for modem on SDM845 SoCs Sibi Sankar
@ 2018-07-31 8:42 0% ` Philipp Zabel
2018-07-31 12:57 6% ` Sibi S
2018-08-21 22:08 0% ` Bjorn Andersson
4 siblings, 1 reply; 200+ results
From: Philipp Zabel @ 2018-07-31 8:42 UTC (permalink / raw)
To: Sibi Sankar, bjorn.andersson, robh+dt
Cc: linux-remoteproc, linux-kernel, devicetree, ohad, mark.rutland,
sricharan, akdwived, linux-arm-msm, tsoni
Hi Sibi,
On Fri, 2018-07-27 at 20:58 +0530, Sibi Sankar wrote:
> Add SDM845 PDC (Power Domain Controller) reset controller binding
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
> .../bindings/reset/qcom,pdc-reset.txt | 52 +++++++++++++++++++
> include/dt-bindings/reset/qcom,sdm845-pdc.h | 20 +++++++
> 2 files changed, 72 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/reset/qcom,pdc-reset.txt
> create mode 100644 include/dt-bindings/reset/qcom,sdm845-pdc.h
>
> diff --git a/Documentation/devicetree/bindings/reset/qcom,pdc-reset.txt b/Documentation/devicetree/bindings/reset/qcom,pdc-reset.txt
> new file mode 100644
> index 000000000000..85e159962e08
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/reset/qcom,pdc-reset.txt
> @@ -0,0 +1,52 @@
> +PDC Reset Controller
> +======================================
> +
> +This binding describes a reset-controller found on PDC-Global(Power Domain
> +Controller) block for Qualcomm Technologies Inc SDM845 SoCs.
> +
> +Required properties:
> +- compatible:
> + Usage: required
> + Value type: <string>
> + Definition: must be:
> + "qcom,sdm845-pdc-global"
> +
> +- reg:
> + Usage: required
> + Value type: <prop-encoded-array>
> + Definition: must specify the base address and size of the register
> + space.
> +
> +- #reset-cells:
> + Usage: required
> + Value type: <uint>
> + Definition: must be 1; cell entry represents the reset index.
> +
> +Example:
> +
> +pdc_reset: reset-controller@b2e0000 {
Is this really just a reset controller?
The name makes it sound like a driver binding to this should also
provide pm_genpd and the binding should probably call this a power-
controller: Documentation/devicetree/bindings/power/power_domain.txt.
> + compatible = "qcom,sdm845-pdc-global";
> + reg = <0xb2e0000 0x20000>;
This looks like this is the register space of the complete PDC, not just
the reset register?
> + #reset-cells = <1>;
> +};
> +
> +PDC reset clients
> +======================================
> +
> +Device nodes that need access to reset lines should
> +specify them as a reset phandle in their corresponding node as
> +specified in reset.txt.
> +
> +For list of all valid reset indicies see
> +<dt-bindings/reset/qcom,sdm845-pdc.h>
> +
> +Example:
> +
> +modem-pil@4080000 {
> + ...
> +
> + resets = <&pdc_reset PDC_MODEM_SYNC_RESET>;
> + reset-names = "pdc_restart";
> +
> + ...
> +};
> diff --git a/include/dt-bindings/reset/qcom,sdm845-pdc.h b/include/dt-bindings/reset/qcom,sdm845-pdc.h
> new file mode 100644
> index 000000000000..53c37f9c319a
> --- /dev/null
> +++ b/include/dt-bindings/reset/qcom,sdm845-pdc.h
> @@ -0,0 +1,20 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2018 The Linux Foundation. All rights reserved.
> + */
> +
> +#ifndef _DT_BINDINGS_RESET_PDC_SDM_845_H
> +#define _DT_BINDINGS_RESET_PDC_SDM_845_H
> +
> +#define PDC_APPS_SYNC_RESET 0
> +#define PDC_SP_SYNC_RESET 1
> +#define PDC_AUDIO_SYNC_RESET 2
> +#define PDC_SENSORS_SYNC_RESET 3
> +#define PDC_AOP_SYNC_RESET 4
> +#define PDC_DEBUG_SYNC_RESET 5
> +#define PDC_GPU_SYNC_RESET 6
> +#define PDC_DISPLAY_SYNC_RESET 7
> +#define PDC_COMPUTE_SYNC_RESET 8
> +#define PDC_MODEM_SYNC_RESET 9
> +
> +#endif
regards
Philipp
^ permalink raw reply [relevance 0%]
* Re: [PATCH 2/4] reset: qcom: PDC (Power Domain Controller) reset controller
2018-07-27 15:28 16% ` [PATCH 2/4] reset: qcom: PDC (Power Domain Controller) reset controller Sibi Sankar
@ 2018-07-31 8:51 0% ` Philipp Zabel
2018-07-31 13:00 6% ` Sibi S
2018-08-21 22:17 0% ` Bjorn Andersson
1 sibling, 1 reply; 200+ results
From: Philipp Zabel @ 2018-07-31 8:51 UTC (permalink / raw)
To: Sibi Sankar, bjorn.andersson, robh+dt
Cc: linux-remoteproc, linux-kernel, devicetree, ohad, mark.rutland,
sricharan, akdwived, linux-arm-msm, tsoni
On Fri, 2018-07-27 at 20:58 +0530, Sibi Sankar wrote:
> Add reset controller for SDM845 SoC to control reset signals
> provided by PDC for Modem, Compute, Display, GPU, Debug, AOP,
> Sensors, Audio, SP and APPS
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
> drivers/reset/Kconfig | 9 +++
> drivers/reset/Makefile | 1 +
> drivers/reset/reset-qcom-pdc.c | 139 +++++++++++++++++++++++++++++++++
> 3 files changed, 149 insertions(+)
> create mode 100644 drivers/reset/reset-qcom-pdc.c
>
> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
> index 13d28fdbdbb5..5344e202a630 100644
> --- a/drivers/reset/Kconfig
> +++ b/drivers/reset/Kconfig
> @@ -98,6 +98,15 @@ config RESET_QCOM_AOSS
> reset signals provided by AOSS for Modem, Venus, ADSP,
> GPU, Camera, Wireless, Display subsystem. Otherwise, say N.
>
> +config RESET_QCOM_PDC
> + bool "Qcom PDC Reset Driver"
> + depends on ARCH_QCOM || COMPILE_TEST
> + help
> + This enables the PDC (Power Domain Controller) reset driver
> + for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want
> + to control reset signals provided by PDC for Modem, Compute,
> + Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS.
> +
> config RESET_SIMPLE
> bool "Simple Reset Controller Driver" if COMPILE_TEST
> default ARCH_SOCFPGA || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED
> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
> index 4243c38228e2..d08e8b90046a 100644
> --- a/drivers/reset/Makefile
> +++ b/drivers/reset/Makefile
> @@ -16,6 +16,7 @@ obj-$(CONFIG_RESET_MESON_AUDIO_ARB) += reset-meson-audio-arb.o
> obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
> obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o
> obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o
> +obj-$(CONFIG_RESET_QCOM_PDC) += reset-qcom-pdc.o
> obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
> obj-$(CONFIG_RESET_STM32MP157) += reset-stm32mp1.o
> obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
> diff --git a/drivers/reset/reset-qcom-pdc.c b/drivers/reset/reset-qcom-pdc.c
> new file mode 100644
> index 000000000000..64a0041e3452
> --- /dev/null
> +++ b/drivers/reset/reset-qcom-pdc.c
> @@ -0,0 +1,139 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2018 The Linux Foundation. All rights reserved.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/reset-controller.h>
> +#include <linux/regmap.h>
> +#include <linux/of_device.h>
> +#include <dt-bindings/reset/qcom,sdm845-pdc.h>
> +
> +struct qcom_pdc_reset_map {
> + u8 bit;
> +};
> +
> +struct qcom_pdc_desc {
> + const struct regmap_config *config;
> + const struct qcom_pdc_reset_map *resets;
> + size_t num_resets;
> +};
> +
> +struct qcom_pdc_reset_data {
> + struct reset_controller_dev rcdev;
> + struct regmap *regmap;
> + const struct qcom_pdc_desc *desc;
> +};
> +
> +static const struct regmap_config sdm845_pdc_regmap_config = {
> + .name = "pdc-reset",
> + .reg_bits = 32,
> + .reg_stride = 4,
> + .val_bits = 32,
> + .max_register = 0x20000,
> + .fast_io = true,
> +};
> +
> +static const struct qcom_pdc_reset_map sdm845_pdc_resets[] = {
> + [PDC_APPS_SYNC_RESET] = {0},
> + [PDC_SP_SYNC_RESET] = {1},
> + [PDC_AUDIO_SYNC_RESET] = {2},
> + [PDC_SENSORS_SYNC_RESET] = {3},
> + [PDC_AOP_SYNC_RESET] = {4},
> + [PDC_DEBUG_SYNC_RESET] = {5},
> + [PDC_GPU_SYNC_RESET] = {6},
> + [PDC_DISPLAY_SYNC_RESET] = {7},
> + [PDC_COMPUTE_SYNC_RESET] = {8},
> + [PDC_MODEM_SYNC_RESET] = {9},
> +};
> +
> +static const struct qcom_pdc_desc sdm845_pdc_desc = {
> + .config = &sdm845_pdc_regmap_config,
> + .resets = sdm845_pdc_resets,
> + .num_resets = ARRAY_SIZE(sdm845_pdc_resets),
> +};
> +
> +static inline struct qcom_pdc_reset_data *to_qcom_pdc_reset_data(
> + struct reset_controller_dev *rcdev)
> +{
> + return container_of(rcdev, struct qcom_pdc_reset_data, rcdev);
> +}
> +
> +static int qcom_pdc_control_assert(struct reset_controller_dev *rcdev,
> + unsigned long idx)
> +{
> + struct qcom_pdc_reset_data *data = to_qcom_pdc_reset_data(rcdev);
> + const struct qcom_pdc_reset_map *map = &data->desc->resets[idx];
> +
> + return regmap_update_bits(data->regmap, 0x100,
Does this register have a name? If so, a #define would be preferable.
Otherwise this driver looks fine to me.
> + BIT(map->bit), BIT(map->bit));
> +}
> +
> +static int qcom_pdc_control_deassert(struct reset_controller_dev *rcdev,
> + unsigned long idx)
> +{
> + struct qcom_pdc_reset_data *data = to_qcom_pdc_reset_data(rcdev);
> + const struct qcom_pdc_reset_map *map = &data->desc->resets[idx];
> +
> + return regmap_update_bits(data->regmap, 0x100, BIT(map->bit), 0);
> +}
> +
> +static const struct reset_control_ops qcom_pdc_reset_ops = {
> + .assert = qcom_pdc_control_assert,
> + .deassert = qcom_pdc_control_deassert,
> +};
> +
> +static int qcom_pdc_reset_probe(struct platform_device *pdev)
> +{
> + struct qcom_pdc_reset_data *data;
> + struct device *dev = &pdev->dev;
> + const struct qcom_pdc_desc *desc;
> + void __iomem *base;
> + struct resource *res;
> +
> + desc = of_device_get_match_data(dev);
> + if (!desc)
> + return -EINVAL;
> +
> + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
> + if (!data)
> + return -ENOMEM;
> +
> + data->desc = desc;
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + base = devm_ioremap_resource(dev, res);
> + if (IS_ERR(base))
> + return PTR_ERR(base);
> +
> + data->regmap = devm_regmap_init_mmio(dev, base, desc->config);
> + if (IS_ERR(data->regmap)) {
> + dev_err(dev, "Unable to get pdc-global regmap");
> + return PTR_ERR(data->regmap);
> + }
> +
> + data->rcdev.owner = THIS_MODULE;
> + data->rcdev.ops = &qcom_pdc_reset_ops;
> + data->rcdev.nr_resets = desc->num_resets;
> + data->rcdev.of_node = dev->of_node;
> +
> + return devm_reset_controller_register(dev, &data->rcdev);
> +}
> +
> +static const struct of_device_id qcom_pdc_reset_of_match[] = {
> + { .compatible = "qcom,sdm845-pdc-global", .data = &sdm845_pdc_desc },
> + {}
> +};
> +
> +static struct platform_driver qcom_pdc_reset_driver = {
> + .probe = qcom_pdc_reset_probe,
> + .driver = {
> + .name = "qcom_pdc_reset",
> + .of_match_table = qcom_pdc_reset_of_match,
> + },
> +};
> +
> +builtin_platform_driver(qcom_pdc_reset_driver);
> +
> +MODULE_DESCRIPTION("Qualcomm PDC Reset Driver");
> +MODULE_LICENSE("GPL v2");
regards
Philipp
^ permalink raw reply [relevance 0%]
* Re: [PATCH 4/4] remoteproc: qcom: q6v5-pil: Add PDC restart for modem on SDM845 SoCs
2018-07-27 15:28 19% ` [PATCH 4/4] remoteproc: qcom: q6v5-pil: Add PDC restart for modem on SDM845 SoCs Sibi Sankar
@ 2018-07-31 8:54 0% ` Philipp Zabel
2018-07-31 13:13 6% ` Sibi S
2018-08-07 18:18 0% ` Rob Herring
2018-08-21 22:33 0% ` Bjorn Andersson
2 siblings, 1 reply; 200+ results
From: Philipp Zabel @ 2018-07-31 8:54 UTC (permalink / raw)
To: Sibi Sankar, bjorn.andersson, robh+dt
Cc: linux-remoteproc, linux-kernel, devicetree, ohad, mark.rutland,
sricharan, akdwived, linux-arm-msm, tsoni
On Fri, 2018-07-27 at 20:58 +0530, Sibi Sankar wrote:
> In the presence of a PDC block working with subsystem RSC,
> assert/deassert PDC restart in modem start/stop path.
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
> .../bindings/remoteproc/qcom,q6v5.txt | 4 +++
> drivers/remoteproc/qcom_q6v5_pil.c | 27 ++++++++++++++++---
> 2 files changed, 27 insertions(+), 4 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
> index 601dd9f389aa..124fb1dc6fb8 100644
> --- a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
> +++ b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
[...]
> @@ -1182,6 +1192,15 @@ static int q6v5_init_reset(struct q6v5 *qproc)
> return PTR_ERR(qproc->mss_restart);
> }
>
> + if (qproc->has_alt_reset) {
> + qproc->pdc_restart = devm_reset_control_get(qproc->dev,
> + "pdc_restart");
Please use devm_reset_control_get_exclusive() instead.
> + if (IS_ERR(qproc->pdc_restart)) {
> + dev_err(qproc->dev, "failed to acquire pdc restart\n");
> + return PTR_ERR(qproc->pdc_restart);
> + }
> + }
> +
> return 0;
> }
regards
Philipp
^ permalink raw reply [relevance 0%]
* Re: [PATCH 3/4] remoteproc: qcom: q6v5-pil: Explicitly get mss_restart line
2018-07-27 15:28 21% ` [PATCH 3/4] remoteproc: qcom: q6v5-pil: Explicitly get mss_restart line Sibi Sankar
@ 2018-07-31 8:57 0% ` Philipp Zabel
2018-07-31 13:11 6% ` Sibi S
0 siblings, 1 reply; 200+ results
From: Philipp Zabel @ 2018-07-31 8:57 UTC (permalink / raw)
To: Sibi Sankar, bjorn.andersson, robh+dt
Cc: linux-remoteproc, linux-kernel, devicetree, ohad, mark.rutland,
sricharan, akdwived, linux-arm-msm, tsoni
On Fri, 2018-07-27 at 20:58 +0530, Sibi Sankar wrote:
> Explicitly get mss_restart to facilitate adding PDC
> restart line for modem on SDM845 SoCs
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
> drivers/remoteproc/qcom_q6v5_pil.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
> index b1296d614b8b..d57fdb34e3dd 100644
> --- a/drivers/remoteproc/qcom_q6v5_pil.c
> +++ b/drivers/remoteproc/qcom_q6v5_pil.c
> @@ -1176,8 +1176,7 @@ static int q6v5_init_clocks(struct device *dev, struct clk **clks,
>
> static int q6v5_init_reset(struct q6v5 *qproc)
> {
> - qproc->mss_restart = devm_reset_control_get_exclusive(qproc->dev,
> - NULL);
> + qproc->mss_restart = devm_reset_control_get(qproc->dev, "mss_restart");
Please keep using devm_reset_control_get_exclusive.
regards
Philipp
^ permalink raw reply [relevance 0%]
* Re: [PATCH 1/4] dt-bindings: reset: Add PDC reset binding for SDM845 SoCs
2018-07-31 8:42 0% ` [PATCH 1/4] dt-bindings: reset: Add PDC reset binding for " Philipp Zabel
@ 2018-07-31 12:57 6% ` Sibi S
2018-08-07 18:16 0% ` Rob Herring
0 siblings, 1 reply; 200+ results
From: Sibi S @ 2018-07-31 12:57 UTC (permalink / raw)
To: Philipp Zabel, bjorn.andersson, robh+dt
Cc: linux-remoteproc, linux-kernel, devicetree, ohad, mark.rutland,
sricharan, akdwived, linux-arm-msm, tsoni, ilina
Hi Philipp,
Thanks for the review!
On 07/31/2018 02:12 PM, Philipp Zabel wrote:
> Hi Sibi,
>
> On Fri, 2018-07-27 at 20:58 +0530, Sibi Sankar wrote:
>> Add SDM845 PDC (Power Domain Controller) reset controller binding
>>
>> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
>> ---
>> .../bindings/reset/qcom,pdc-reset.txt | 52 +++++++++++++++++++
>> include/dt-bindings/reset/qcom,sdm845-pdc.h | 20 +++++++
>> 2 files changed, 72 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/reset/qcom,pdc-reset.txt
>> create mode 100644 include/dt-bindings/reset/qcom,sdm845-pdc.h
>>
>> diff --git a/Documentation/devicetree/bindings/reset/qcom,pdc-reset.txt b/Documentation/devicetree/bindings/reset/qcom,pdc-reset.txt
>> new file mode 100644
>> index 000000000000..85e159962e08
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/reset/qcom,pdc-reset.txt
>> @@ -0,0 +1,52 @@
>> +PDC Reset Controller
>> +======================================
>> +
>> +This binding describes a reset-controller found on PDC-Global(Power Domain
>> +Controller) block for Qualcomm Technologies Inc SDM845 SoCs.
>> +
>> +Required properties:
>> +- compatible:
>> + Usage: required
>> + Value type: <string>
>> + Definition: must be:
>> + "qcom,sdm845-pdc-global"
>> +
>> +- reg:
>> + Usage: required
>> + Value type: <prop-encoded-array>
>> + Definition: must specify the base address and size of the register
>> + space.
>> +
>> +- #reset-cells:
>> + Usage: required
>> + Value type: <uint>
>> + Definition: must be 1; cell entry represents the reset index.
>> +
>> +Example:
>> +
>> +pdc_reset: reset-controller@b2e0000 {
>
> Is this really just a reset controller?
>
> The name makes it sound like a driver binding to this should also
> provide pm_genpd and the binding should probably call this a power-
> controller: Documentation/devicetree/bindings/power/power_domain.txt.
>
The PDC-global reg space which is a part of PDC-wrapper reg space seems
to be only used for the reset lines.
Couple of other drivers use other parts of the PDC-wrapper reg space:
https://patchwork.kernel.org/patch/10223701/ (PDC-Interrupt controller)
https://patchwork.kernel.org/patch/10255767/ (GMU-PDC incorrectly tries
to occupy the entire pdc-wrapper reg space)
since it couldn't be logically mapped into pdc-interrupt driver, it had
to be included as a separate reset driver.
>> + compatible = "qcom,sdm845-pdc-global";
>> + reg = <0xb2e0000 0x20000>;
>
> This looks like this is the register space of the complete PDC, not just
> the reset register?
>
The entire register space was chosen because it is only used for its
reset lines (had a good look at the downstream kernel and had a
conversation with Lina) and to ensure break backward compatibility for
the for the dt entry if the reg-space was used for other purposes in
the future.
>> + #reset-cells = <1>;
>> +};
>> +
>> +PDC reset clients
>> +======================================
>> +
>> +Device nodes that need access to reset lines should
>> +specify them as a reset phandle in their corresponding node as
>> +specified in reset.txt.
>> +
>> +For list of all valid reset indicies see
>> +<dt-bindings/reset/qcom,sdm845-pdc.h>
>> +
>> +Example:
>> +
>> +modem-pil@4080000 {
>> + ...
>> +
>> + resets = <&pdc_reset PDC_MODEM_SYNC_RESET>;
>> + reset-names = "pdc_restart";
>> +
>> + ...
>> +};
>> diff --git a/include/dt-bindings/reset/qcom,sdm845-pdc.h b/include/dt-bindings/reset/qcom,sdm845-pdc.h
>> new file mode 100644
>> index 000000000000..53c37f9c319a
>> --- /dev/null
>> +++ b/include/dt-bindings/reset/qcom,sdm845-pdc.h
>> @@ -0,0 +1,20 @@
>> +/* SPDX-License-Identifier: GPL-2.0 */
>> +/*
>> + * Copyright (C) 2018 The Linux Foundation. All rights reserved.
>> + */
>> +
>> +#ifndef _DT_BINDINGS_RESET_PDC_SDM_845_H
>> +#define _DT_BINDINGS_RESET_PDC_SDM_845_H
>> +
>> +#define PDC_APPS_SYNC_RESET 0
>> +#define PDC_SP_SYNC_RESET 1
>> +#define PDC_AUDIO_SYNC_RESET 2
>> +#define PDC_SENSORS_SYNC_RESET 3
>> +#define PDC_AOP_SYNC_RESET 4
>> +#define PDC_DEBUG_SYNC_RESET 5
>> +#define PDC_GPU_SYNC_RESET 6
>> +#define PDC_DISPLAY_SYNC_RESET 7
>> +#define PDC_COMPUTE_SYNC_RESET 8
>> +#define PDC_MODEM_SYNC_RESET 9
>> +
>> +#endif
>
> regards
> Philipp
>
--
Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc, is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [relevance 6%]
* Re: [PATCH 2/4] reset: qcom: PDC (Power Domain Controller) reset controller
2018-07-31 8:51 0% ` Philipp Zabel
@ 2018-07-31 13:00 6% ` Sibi S
0 siblings, 0 replies; 200+ results
From: Sibi S @ 2018-07-31 13:00 UTC (permalink / raw)
To: Philipp Zabel, bjorn.andersson, robh+dt
Cc: linux-remoteproc, linux-kernel, devicetree, ohad, mark.rutland,
sricharan, akdwived, linux-arm-msm, tsoni
Hi Philipp,
Thanks for the review!
On 07/31/2018 02:21 PM, Philipp Zabel wrote:
> On Fri, 2018-07-27 at 20:58 +0530, Sibi Sankar wrote:
>> Add reset controller for SDM845 SoC to control reset signals
>> provided by PDC for Modem, Compute, Display, GPU, Debug, AOP,
>> Sensors, Audio, SP and APPS
>>
>> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
>> ---
>> drivers/reset/Kconfig | 9 +++
>> drivers/reset/Makefile | 1 +
>> drivers/reset/reset-qcom-pdc.c | 139 +++++++++++++++++++++++++++++++++
>> 3 files changed, 149 insertions(+)
>> create mode 100644 drivers/reset/reset-qcom-pdc.c
>>
>> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
>> index 13d28fdbdbb5..5344e202a630 100644
>> --- a/drivers/reset/Kconfig
>> +++ b/drivers/reset/Kconfig
>> @@ -98,6 +98,15 @@ config RESET_QCOM_AOSS
>> reset signals provided by AOSS for Modem, Venus, ADSP,
>> GPU, Camera, Wireless, Display subsystem. Otherwise, say N.
>>
>> +config RESET_QCOM_PDC
>> + bool "Qcom PDC Reset Driver"
>> + depends on ARCH_QCOM || COMPILE_TEST
>> + help
>> + This enables the PDC (Power Domain Controller) reset driver
>> + for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want
>> + to control reset signals provided by PDC for Modem, Compute,
>> + Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS.
>> +
>> config RESET_SIMPLE
>> bool "Simple Reset Controller Driver" if COMPILE_TEST
>> default ARCH_SOCFPGA || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED
>> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
>> index 4243c38228e2..d08e8b90046a 100644
>> --- a/drivers/reset/Makefile
>> +++ b/drivers/reset/Makefile
>> @@ -16,6 +16,7 @@ obj-$(CONFIG_RESET_MESON_AUDIO_ARB) += reset-meson-audio-arb.o
>> obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
>> obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o
>> obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o
>> +obj-$(CONFIG_RESET_QCOM_PDC) += reset-qcom-pdc.o
>> obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
>> obj-$(CONFIG_RESET_STM32MP157) += reset-stm32mp1.o
>> obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
>> diff --git a/drivers/reset/reset-qcom-pdc.c b/drivers/reset/reset-qcom-pdc.c
>> new file mode 100644
>> index 000000000000..64a0041e3452
>> --- /dev/null
>> +++ b/drivers/reset/reset-qcom-pdc.c
>> @@ -0,0 +1,139 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (C) 2018 The Linux Foundation. All rights reserved.
>> + */
>> +
>> +#include <linux/module.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/reset-controller.h>
>> +#include <linux/regmap.h>
>> +#include <linux/of_device.h>
>> +#include <dt-bindings/reset/qcom,sdm845-pdc.h>
>> +
>> +struct qcom_pdc_reset_map {
>> + u8 bit;
>> +};
>> +
>> +struct qcom_pdc_desc {
>> + const struct regmap_config *config;
>> + const struct qcom_pdc_reset_map *resets;
>> + size_t num_resets;
>> +};
>> +
>> +struct qcom_pdc_reset_data {
>> + struct reset_controller_dev rcdev;
>> + struct regmap *regmap;
>> + const struct qcom_pdc_desc *desc;
>> +};
>> +
>> +static const struct regmap_config sdm845_pdc_regmap_config = {
>> + .name = "pdc-reset",
>> + .reg_bits = 32,
>> + .reg_stride = 4,
>> + .val_bits = 32,
>> + .max_register = 0x20000,
>> + .fast_io = true,
>> +};
>> +
>> +static const struct qcom_pdc_reset_map sdm845_pdc_resets[] = {
>> + [PDC_APPS_SYNC_RESET] = {0},
>> + [PDC_SP_SYNC_RESET] = {1},
>> + [PDC_AUDIO_SYNC_RESET] = {2},
>> + [PDC_SENSORS_SYNC_RESET] = {3},
>> + [PDC_AOP_SYNC_RESET] = {4},
>> + [PDC_DEBUG_SYNC_RESET] = {5},
>> + [PDC_GPU_SYNC_RESET] = {6},
>> + [PDC_DISPLAY_SYNC_RESET] = {7},
>> + [PDC_COMPUTE_SYNC_RESET] = {8},
>> + [PDC_MODEM_SYNC_RESET] = {9},
>> +};
>> +
>> +static const struct qcom_pdc_desc sdm845_pdc_desc = {
>> + .config = &sdm845_pdc_regmap_config,
>> + .resets = sdm845_pdc_resets,
>> + .num_resets = ARRAY_SIZE(sdm845_pdc_resets),
>> +};
>> +
>> +static inline struct qcom_pdc_reset_data *to_qcom_pdc_reset_data(
>> + struct reset_controller_dev *rcdev)
>> +{
>> + return container_of(rcdev, struct qcom_pdc_reset_data, rcdev);
>> +}
>> +
>> +static int qcom_pdc_control_assert(struct reset_controller_dev *rcdev,
>> + unsigned long idx)
>> +{
>> + struct qcom_pdc_reset_data *data = to_qcom_pdc_reset_data(rcdev);
>> + const struct qcom_pdc_reset_map *map = &data->desc->resets[idx];
>> +
>> + return regmap_update_bits(data->regmap, 0x100,
>
> Does this register have a name? If so, a #define would be preferable.
> Otherwise this driver looks fine to me.
>
Yes will had a separate #define for it.
>> + BIT(map->bit), BIT(map->bit));
>> +}
>> +
>> +static int qcom_pdc_control_deassert(struct reset_controller_dev *rcdev,
>> + unsigned long idx)
>> +{
>> + struct qcom_pdc_reset_data *data = to_qcom_pdc_reset_data(rcdev);
>> + const struct qcom_pdc_reset_map *map = &data->desc->resets[idx];
>> +
>> + return regmap_update_bits(data->regmap, 0x100, BIT(map->bit), 0);
>> +}
>> +
>> +static const struct reset_control_ops qcom_pdc_reset_ops = {
>> + .assert = qcom_pdc_control_assert,
>> + .deassert = qcom_pdc_control_deassert,
>> +};
>> +
>> +static int qcom_pdc_reset_probe(struct platform_device *pdev)
>> +{
>> + struct qcom_pdc_reset_data *data;
>> + struct device *dev = &pdev->dev;
>> + const struct qcom_pdc_desc *desc;
>> + void __iomem *base;
>> + struct resource *res;
>> +
>> + desc = of_device_get_match_data(dev);
>> + if (!desc)
>> + return -EINVAL;
>> +
>> + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
>> + if (!data)
>> + return -ENOMEM;
>> +
>> + data->desc = desc;
>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> + base = devm_ioremap_resource(dev, res);
>> + if (IS_ERR(base))
>> + return PTR_ERR(base);
>> +
>> + data->regmap = devm_regmap_init_mmio(dev, base, desc->config);
>> + if (IS_ERR(data->regmap)) {
>> + dev_err(dev, "Unable to get pdc-global regmap");
>> + return PTR_ERR(data->regmap);
>> + }
>> +
>> + data->rcdev.owner = THIS_MODULE;
>> + data->rcdev.ops = &qcom_pdc_reset_ops;
>> + data->rcdev.nr_resets = desc->num_resets;
>> + data->rcdev.of_node = dev->of_node;
>> +
>> + return devm_reset_controller_register(dev, &data->rcdev);
>> +}
>> +
>> +static const struct of_device_id qcom_pdc_reset_of_match[] = {
>> + { .compatible = "qcom,sdm845-pdc-global", .data = &sdm845_pdc_desc },
>> + {}
>> +};
>> +
>> +static struct platform_driver qcom_pdc_reset_driver = {
>> + .probe = qcom_pdc_reset_probe,
>> + .driver = {
>> + .name = "qcom_pdc_reset",
>> + .of_match_table = qcom_pdc_reset_of_match,
>> + },
>> +};
>> +
>> +builtin_platform_driver(qcom_pdc_reset_driver);
>> +
>> +MODULE_DESCRIPTION("Qualcomm PDC Reset Driver");
>> +MODULE_LICENSE("GPL v2");
>
> regards
> Philipp
>
--
Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc, is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [relevance 6%]
* Re: [PATCH 3/4] remoteproc: qcom: q6v5-pil: Explicitly get mss_restart line
2018-07-31 8:57 0% ` Philipp Zabel
@ 2018-07-31 13:11 6% ` Sibi S
0 siblings, 0 replies; 200+ results
From: Sibi S @ 2018-07-31 13:11 UTC (permalink / raw)
To: Philipp Zabel, bjorn.andersson, robh+dt
Cc: linux-remoteproc, linux-kernel, devicetree, ohad, mark.rutland,
sricharan, akdwived, linux-arm-msm, tsoni
Hi Philipp,
Thanks for the review!
On 07/31/2018 02:27 PM, Philipp Zabel wrote:
> On Fri, 2018-07-27 at 20:58 +0530, Sibi Sankar wrote:
>> Explicitly get mss_restart to facilitate adding PDC
>> restart line for modem on SDM845 SoCs
>>
>> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
>> ---
>> drivers/remoteproc/qcom_q6v5_pil.c | 3 +--
>> 1 file changed, 1 insertion(+), 2 deletions(-)
>>
>> diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
>> index b1296d614b8b..d57fdb34e3dd 100644
>> --- a/drivers/remoteproc/qcom_q6v5_pil.c
>> +++ b/drivers/remoteproc/qcom_q6v5_pil.c
>> @@ -1176,8 +1176,7 @@ static int q6v5_init_clocks(struct device *dev, struct clk **clks,
>>
>> static int q6v5_init_reset(struct q6v5 *qproc)
>> {
>> - qproc->mss_restart = devm_reset_control_get_exclusive(qproc->dev,
>> - NULL);
>> + qproc->mss_restart = devm_reset_control_get(qproc->dev, "mss_restart");
>
> Please keep using devm_reset_control_get_exclusive.
>
got misled when I saw it being used in a recent driver :), will revert
it back.
> regards
> Philipp
>
--
Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc, is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [relevance 6%]
* Re: [PATCH 4/4] remoteproc: qcom: q6v5-pil: Add PDC restart for modem on SDM845 SoCs
2018-07-31 8:54 0% ` Philipp Zabel
@ 2018-07-31 13:13 6% ` Sibi S
0 siblings, 0 replies; 200+ results
From: Sibi S @ 2018-07-31 13:13 UTC (permalink / raw)
To: Philipp Zabel, bjorn.andersson, robh+dt
Cc: linux-remoteproc, linux-kernel, devicetree, ohad, mark.rutland,
sricharan, akdwived, linux-arm-msm, tsoni
Hi Philipp,
Thanks for the review!
On 07/31/2018 02:24 PM, Philipp Zabel wrote:
> On Fri, 2018-07-27 at 20:58 +0530, Sibi Sankar wrote:
>> In the presence of a PDC block working with subsystem RSC,
>> assert/deassert PDC restart in modem start/stop path.
>>
>> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
>> ---
>> .../bindings/remoteproc/qcom,q6v5.txt | 4 +++
>> drivers/remoteproc/qcom_q6v5_pil.c | 27 ++++++++++++++++---
>> 2 files changed, 27 insertions(+), 4 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
>> index 601dd9f389aa..124fb1dc6fb8 100644
>> --- a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
>> +++ b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
> [...]
>> @@ -1182,6 +1192,15 @@ static int q6v5_init_reset(struct q6v5 *qproc)
>> return PTR_ERR(qproc->mss_restart);
>> }
>>
>> + if (qproc->has_alt_reset) {
>> + qproc->pdc_restart = devm_reset_control_get(qproc->dev,
>> + "pdc_restart");
>
> Please use devm_reset_control_get_exclusive() instead.
>
will replace it in the next re-spin.
>> + if (IS_ERR(qproc->pdc_restart)) {
>> + dev_err(qproc->dev, "failed to acquire pdc restart\n");
>> + return PTR_ERR(qproc->pdc_restart);
>> + }
>> + }
>> +
>> return 0;
>> }
>
> regards
> Philipp
>
--
Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc, is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [relevance 6%]
* Re: [PATCH v3 1/6] remoteproc: Introduce custom dump function for each remoteproc segment
2018-07-27 15:19 20% ` [PATCH v3 1/6] remoteproc: Introduce custom dump function for each remoteproc segment Sibi Sankar
@ 2018-08-07 6:15 0% ` Vinod
2018-08-08 14:10 6% ` Sibi Sankar
2018-10-08 6:23 0% ` Bjorn Andersson
1 sibling, 1 reply; 200+ results
From: Vinod @ 2018-08-07 6:15 UTC (permalink / raw)
To: Sibi Sankar
Cc: bjorn.andersson, linux-remoteproc, linux-kernel, ohad, kyan,
sricharan, akdwived, linux-arm-msm, tsoni
Hi Sibi,
On 27-07-18, 20:49, Sibi Sankar wrote:
> Introduce custom dump function per remoteproc segment. It is responsible
> for filling the device memory segment associated with coredump
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
> drivers/remoteproc/remoteproc_core.c | 15 ++++++++++-----
> include/linux/remoteproc.h | 3 +++
> 2 files changed, 13 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/remoteproc/remoteproc_core.c b/drivers/remoteproc/remoteproc_core.c
> index 283b258f5e0f..ec56cd822b26 100644
> --- a/drivers/remoteproc/remoteproc_core.c
> +++ b/drivers/remoteproc/remoteproc_core.c
> @@ -1183,13 +1183,18 @@ static void rproc_coredump(struct rproc *rproc)
> phdr->p_align = 0;
>
> ptr = rproc_da_to_va(rproc, segment->da, segment->size);
> - if (!ptr) {
> - dev_err(&rproc->dev,
> +
> + if (segment->dump) {
> + segment->dump(rproc, ptr, segment->size, data + offset);
Am not sure I follow, you are calling this w/o checking if ptr is valid,
so you maybe passing null to segment->dump() ?
> + } else {
> + if (!ptr) {
> + dev_err(&rproc->dev,
> "invalid coredump segment (%pad, %zu)\n",
> &segment->da, segment->size);
> - memset(data + offset, 0xff, segment->size);
> - } else {
> - memcpy(data + offset, ptr, segment->size);
> + memset(data + offset, 0xff, segment->size);
> + } else {
> + memcpy(data + offset, ptr, segment->size);
> + }
--
~Vinod
^ permalink raw reply [relevance 0%]
* Re: [PATCH 1/4] dt-bindings: reset: Add PDC reset binding for SDM845 SoCs
2018-07-31 12:57 6% ` Sibi S
@ 2018-08-07 18:16 0% ` Rob Herring
2018-08-08 15:44 6% ` Sibi Sankar
0 siblings, 1 reply; 200+ results
From: Rob Herring @ 2018-08-07 18:16 UTC (permalink / raw)
To: Sibi S
Cc: Philipp Zabel, bjorn.andersson, linux-remoteproc, linux-kernel,
devicetree, ohad, mark.rutland, sricharan, akdwived,
linux-arm-msm, tsoni, ilina
On Tue, Jul 31, 2018 at 06:27:24PM +0530, Sibi S wrote:
> Hi Philipp,
> Thanks for the review!
>
> On 07/31/2018 02:12 PM, Philipp Zabel wrote:
> > Hi Sibi,
> >
> > On Fri, 2018-07-27 at 20:58 +0530, Sibi Sankar wrote:
> > > Add SDM845 PDC (Power Domain Controller) reset controller binding
> > >
> > > Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> > > ---
> > > .../bindings/reset/qcom,pdc-reset.txt | 52 +++++++++++++++++++
> > > include/dt-bindings/reset/qcom,sdm845-pdc.h | 20 +++++++
> > > 2 files changed, 72 insertions(+)
> > > create mode 100644 Documentation/devicetree/bindings/reset/qcom,pdc-reset.txt
> > > create mode 100644 include/dt-bindings/reset/qcom,sdm845-pdc.h
> > >
> > > diff --git a/Documentation/devicetree/bindings/reset/qcom,pdc-reset.txt b/Documentation/devicetree/bindings/reset/qcom,pdc-reset.txt
> > > new file mode 100644
> > > index 000000000000..85e159962e08
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/reset/qcom,pdc-reset.txt
> > > @@ -0,0 +1,52 @@
> > > +PDC Reset Controller
> > > +======================================
> > > +
> > > +This binding describes a reset-controller found on PDC-Global(Power Domain
> > > +Controller) block for Qualcomm Technologies Inc SDM845 SoCs.
> > > +
> > > +Required properties:
> > > +- compatible:
> > > + Usage: required
> > > + Value type: <string>
> > > + Definition: must be:
> > > + "qcom,sdm845-pdc-global"
> > > +
> > > +- reg:
> > > + Usage: required
> > > + Value type: <prop-encoded-array>
> > > + Definition: must specify the base address and size of the register
> > > + space.
> > > +
> > > +- #reset-cells:
> > > + Usage: required
> > > + Value type: <uint>
> > > + Definition: must be 1; cell entry represents the reset index.
> > > +
> > > +Example:
> > > +
> > > +pdc_reset: reset-controller@b2e0000 {
> >
> > Is this really just a reset controller?
> >
> > The name makes it sound like a driver binding to this should also
> > provide pm_genpd and the binding should probably call this a power-
> > controller: Documentation/devicetree/bindings/power/power_domain.txt.
> >
>
> The PDC-global reg space which is a part of PDC-wrapper reg space seems
> to be only used for the reset lines.
>
> Couple of other drivers use other parts of the PDC-wrapper reg space:
> https://patchwork.kernel.org/patch/10223701/ (PDC-Interrupt controller)
> https://patchwork.kernel.org/patch/10255767/ (GMU-PDC incorrectly tries
> to occupy the entire pdc-wrapper reg space)
>
> since it couldn't be logically mapped into pdc-interrupt driver, it had
> to be included as a separate reset driver.
You can't have overlapping regions in DT (well, you can because we have
to work-around existing DTs that do, but you shouldn't).
A single node can be multiple providers such as interrupt controller and
reset controller. It's an OS problem to split that into multiple
drivers.
> > > + compatible = "qcom,sdm845-pdc-global";
> > > + reg = <0xb2e0000 0x20000>;
> >
> > This looks like this is the register space of the complete PDC, not just
> > the reset register?
> >
>
> The entire register space was chosen because it is only used for its
> reset lines (had a good look at the downstream kernel and had a conversation
> with Lina) and to ensure break backward compatibility for
> the for the dt entry if the reg-space was used for other purposes in
> the future.
Why do you want to ensure breaking backwards compatibility?
Rob
^ permalink raw reply [relevance 0%]
* Re: [PATCH 4/4] remoteproc: qcom: q6v5-pil: Add PDC restart for modem on SDM845 SoCs
2018-07-27 15:28 19% ` [PATCH 4/4] remoteproc: qcom: q6v5-pil: Add PDC restart for modem on SDM845 SoCs Sibi Sankar
2018-07-31 8:54 0% ` Philipp Zabel
@ 2018-08-07 18:18 0% ` Rob Herring
2018-08-08 15:45 6% ` Sibi Sankar
2018-08-21 22:33 0% ` Bjorn Andersson
2 siblings, 1 reply; 200+ results
From: Rob Herring @ 2018-08-07 18:18 UTC (permalink / raw)
To: Sibi Sankar
Cc: bjorn.andersson, p.zabel, linux-remoteproc, linux-kernel,
devicetree, ohad, mark.rutland, sricharan, akdwived,
linux-arm-msm, tsoni
On Fri, Jul 27, 2018 at 08:58:11PM +0530, Sibi Sankar wrote:
> In the presence of a PDC block working with subsystem RSC,
> assert/deassert PDC restart in modem start/stop path.
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
> .../bindings/remoteproc/qcom,q6v5.txt | 4 +++
Please split bindings to separate patch.
> drivers/remoteproc/qcom_q6v5_pil.c | 27 ++++++++++++++++---
> 2 files changed, 27 insertions(+), 4 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
> index 601dd9f389aa..124fb1dc6fb8 100644
> --- a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
> +++ b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
> @@ -51,6 +51,8 @@ on the Qualcomm Hexagon core.
> Usage: required
> Value type: <phandle>
> Definition: reference to the reset-controller for the modem sub-system
> + reference to the list of 2 reset-controllers for the modem
> + sub-system on SDM845 SoCs
> reference to the list of 3 reset-controllers for the
> wcss sub-system
>
> @@ -58,6 +60,8 @@ on the Qualcomm Hexagon core.
> Usage: required
> Value type: <stringlist>
> Definition: must be "mss_restart" for the modem sub-system
> + Definition: must be "mss_restart", "pdc_restart" for the modem
> + sub-system on SDM845 SoCs
> Definition: must be "wcss_aon_reset", "wcss_reset", "wcss_q6_reset"
> for the wcss syb-system
>
^ permalink raw reply [relevance 0%]
* Re: [PATCH v3 1/6] remoteproc: Introduce custom dump function for each remoteproc segment
2018-08-07 6:15 0% ` Vinod
@ 2018-08-08 14:10 6% ` Sibi Sankar
0 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2018-08-08 14:10 UTC (permalink / raw)
To: Vinod
Cc: bjorn.andersson, linux-remoteproc, linux-kernel, ohad, kyan,
sricharan, akdwived, linux-arm-msm, tsoni
Hi Vinod,
Thanks for the review,
On 08/07/2018 11:45 AM, Vinod wrote:
> Hi Sibi,
>
> On 27-07-18, 20:49, Sibi Sankar wrote:
>> Introduce custom dump function per remoteproc segment. It is responsible
>> for filling the device memory segment associated with coredump
>>
>> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
>> ---
>> drivers/remoteproc/remoteproc_core.c | 15 ++++++++++-----
>> include/linux/remoteproc.h | 3 +++
>> 2 files changed, 13 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/remoteproc/remoteproc_core.c b/drivers/remoteproc/remoteproc_core.c
>> index 283b258f5e0f..ec56cd822b26 100644
>> --- a/drivers/remoteproc/remoteproc_core.c
>> +++ b/drivers/remoteproc/remoteproc_core.c
>> @@ -1183,13 +1183,18 @@ static void rproc_coredump(struct rproc *rproc)
>> phdr->p_align = 0;
>>
>> ptr = rproc_da_to_va(rproc, segment->da, segment->size);
>> - if (!ptr) {
>> - dev_err(&rproc->dev,
>> +
>> + if (segment->dump) {
>> + segment->dump(rproc, ptr, segment->size, data + offset);
>
> Am not sure I follow, you are calling this w/o checking if ptr is valid,
> so you maybe passing null to segment->dump() ?
>
the rationale behind passing ptr directly to dump_fn is that it will
help in tracking the segments being core dumped (q6v5_pil in particular
requires to unlock mba before dumping and cleanup after all the segments
are dumped which is currently decided based on a mask that is
maintained). It also allows the remoteproc driver to fill the memory as
needed (instead of the default 0xff). This is applicable to drivers that
implement dump_fn, for others the default behavior is maintained.
>> + } else {
>> + if (!ptr) {
>> + dev_err(&rproc->dev,
>> "invalid coredump segment (%pad, %zu)\n",
>> &segment->da, segment->size);
>> - memset(data + offset, 0xff, segment->size);
>> - } else {
>> - memcpy(data + offset, ptr, segment->size);
>> + memset(data + offset, 0xff, segment->size);
>> + } else {
>> + memcpy(data + offset, ptr, segment->size);
>> + }
>
--
Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc, is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [relevance 6%]
* Re: [PATCH 1/4] dt-bindings: reset: Add PDC reset binding for SDM845 SoCs
2018-08-07 18:16 0% ` Rob Herring
@ 2018-08-08 15:44 6% ` Sibi Sankar
2018-08-08 21:37 0% ` Jordan Crouse
0 siblings, 1 reply; 200+ results
From: Sibi Sankar @ 2018-08-08 15:44 UTC (permalink / raw)
To: Rob Herring
Cc: Philipp Zabel, bjorn.andersson, linux-remoteproc, linux-kernel,
devicetree, ohad, mark.rutland, sricharan, akdwived,
linux-arm-msm, tsoni, ilina, jcrouse
Hi Rob,
Thanks for the review
On 08/07/2018 11:46 PM, Rob Herring wrote:
> On Tue, Jul 31, 2018 at 06:27:24PM +0530, Sibi S wrote:
>> Hi Philipp,
>> Thanks for the review!
>>
>> On 07/31/2018 02:12 PM, Philipp Zabel wrote:
>>> Hi Sibi,
>>>
>>> On Fri, 2018-07-27 at 20:58 +0530, Sibi Sankar wrote:
>>>> Add SDM845 PDC (Power Domain Controller) reset controller binding
>>>>
>>>> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
>>>> ---
>>>> .../bindings/reset/qcom,pdc-reset.txt | 52 +++++++++++++++++++
>>>> include/dt-bindings/reset/qcom,sdm845-pdc.h | 20 +++++++
>>>> 2 files changed, 72 insertions(+)
>>>> create mode 100644 Documentation/devicetree/bindings/reset/qcom,pdc-reset.txt
>>>> create mode 100644 include/dt-bindings/reset/qcom,sdm845-pdc.h
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/reset/qcom,pdc-reset.txt b/Documentation/devicetree/bindings/reset/qcom,pdc-reset.txt
>>>> new file mode 100644
>>>> index 000000000000..85e159962e08
>>>> --- /dev/null
>>>> +++ b/Documentation/devicetree/bindings/reset/qcom,pdc-reset.txt
>>>> @@ -0,0 +1,52 @@
>>>> +PDC Reset Controller
>>>> +======================================
>>>> +
>>>> +This binding describes a reset-controller found on PDC-Global(Power Domain
>>>> +Controller) block for Qualcomm Technologies Inc SDM845 SoCs.
>>>> +
>>>> +Required properties:
>>>> +- compatible:
>>>> + Usage: required
>>>> + Value type: <string>
>>>> + Definition: must be:
>>>> + "qcom,sdm845-pdc-global"
>>>> +
>>>> +- reg:
>>>> + Usage: required
>>>> + Value type: <prop-encoded-array>
>>>> + Definition: must specify the base address and size of the register
>>>> + space.
>>>> +
>>>> +- #reset-cells:
>>>> + Usage: required
>>>> + Value type: <uint>
>>>> + Definition: must be 1; cell entry represents the reset index.
>>>> +
>>>> +Example:
>>>> +
>>>> +pdc_reset: reset-controller@b2e0000 {
>>>
>>> Is this really just a reset controller?
>>>
>>> The name makes it sound like a driver binding to this should also
>>> provide pm_genpd and the binding should probably call this a power-
>>> controller: Documentation/devicetree/bindings/power/power_domain.txt.
>>>
>>
>> The PDC-global reg space which is a part of PDC-wrapper reg space seems
>> to be only used for the reset lines.
>>
>> Couple of other drivers use other parts of the PDC-wrapper reg space:
>> https://patchwork.kernel.org/patch/10223701/ (PDC-Interrupt controller)
>> https://patchwork.kernel.org/patch/10255767/ (GMU-PDC incorrectly tries
>> to occupy the entire pdc-wrapper reg space)
>>
>> since it couldn't be logically mapped into pdc-interrupt driver, it had
>> to be included as a separate reset driver.
>
> You can't have overlapping regions in DT (well, you can because we have
> to work-around existing DTs that do, but you shouldn't).
>
> A single node can be multiple providers such as interrupt controller and
> reset controller. It's an OS problem to split that into multiple
> drivers.
>
There will be no overlaps. Jordan will be changing the dt binding of
gmu_pdc so that there is no overlap I guess. What I meant to say is that
pdc-global is a separate reg-space and currently has no other
functionality other than exposing the reset lines.
>>>> + compatible = "qcom,sdm845-pdc-global";
>>>> + reg = <0xb2e0000 0x20000>;
>>>
>>> This looks like this is the register space of the complete PDC, not just
>>> the reset register?
>>>
>>
>> The entire register space was chosen because it is only used for its
>> reset lines (had a good look at the downstream kernel and had a conversation
>> with Lina) and to ensure break backward compatibility for
>> the for the dt entry if the reg-space was used for other purposes in
>> the future.
>
> Why do you want to ensure breaking backwards compatibility?
>
Similar to the AOSS reset driver which had a unused clock part, this
driver also exposes a reg space of which only reset lines are used.
> Rob
>
--
Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc, is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [relevance 6%]
* Re: [PATCH 4/4] remoteproc: qcom: q6v5-pil: Add PDC restart for modem on SDM845 SoCs
2018-08-07 18:18 0% ` Rob Herring
@ 2018-08-08 15:45 6% ` Sibi Sankar
0 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2018-08-08 15:45 UTC (permalink / raw)
To: Rob Herring
Cc: bjorn.andersson, p.zabel, linux-remoteproc, linux-kernel,
devicetree, ohad, mark.rutland, sricharan, akdwived,
linux-arm-msm, tsoni
On 08/07/2018 11:48 PM, Rob Herring wrote:
> On Fri, Jul 27, 2018 at 08:58:11PM +0530, Sibi Sankar wrote:
>> In the presence of a PDC block working with subsystem RSC,
>> assert/deassert PDC restart in modem start/stop path.
>>
>> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
>> ---
>> .../bindings/remoteproc/qcom,q6v5.txt | 4 +++
>
> Please split bindings to separate patch.
>
Okay will split them.
>> drivers/remoteproc/qcom_q6v5_pil.c | 27 ++++++++++++++++---
>> 2 files changed, 27 insertions(+), 4 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
>> index 601dd9f389aa..124fb1dc6fb8 100644
>> --- a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
>> +++ b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
>> @@ -51,6 +51,8 @@ on the Qualcomm Hexagon core.
>> Usage: required
>> Value type: <phandle>
>> Definition: reference to the reset-controller for the modem sub-system
>> + reference to the list of 2 reset-controllers for the modem
>> + sub-system on SDM845 SoCs
>> reference to the list of 3 reset-controllers for the
>> wcss sub-system
>>
>> @@ -58,6 +60,8 @@ on the Qualcomm Hexagon core.
>> Usage: required
>> Value type: <stringlist>
>> Definition: must be "mss_restart" for the modem sub-system
>> + Definition: must be "mss_restart", "pdc_restart" for the modem
>> + sub-system on SDM845 SoCs
>> Definition: must be "wcss_aon_reset", "wcss_reset", "wcss_q6_reset"
>> for the wcss syb-system
>>
--
Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc, is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [relevance 6%]
* Re: [PATCH 1/4] dt-bindings: reset: Add PDC reset binding for SDM845 SoCs
2018-08-08 15:44 6% ` Sibi Sankar
@ 2018-08-08 21:37 0% ` Jordan Crouse
2018-08-08 22:48 0% ` Jordan Crouse
0 siblings, 1 reply; 200+ results
From: Jordan Crouse @ 2018-08-08 21:37 UTC (permalink / raw)
To: Sibi Sankar
Cc: Rob Herring, Philipp Zabel, bjorn.andersson, linux-remoteproc,
linux-kernel, devicetree, ohad, mark.rutland, sricharan,
akdwived, linux-arm-msm, tsoni, ilina
On Wed, Aug 08, 2018 at 09:14:05PM +0530, Sibi Sankar wrote:
> Hi Rob,
> Thanks for the review
>
> On 08/07/2018 11:46 PM, Rob Herring wrote:
> >On Tue, Jul 31, 2018 at 06:27:24PM +0530, Sibi S wrote:
> >>Hi Philipp,
> >>Thanks for the review!
> >>
> >>On 07/31/2018 02:12 PM, Philipp Zabel wrote:
> >>>Hi Sibi,
> >>>
> >>>On Fri, 2018-07-27 at 20:58 +0530, Sibi Sankar wrote:
> >>>>Add SDM845 PDC (Power Domain Controller) reset controller binding
> >>>>
> >>>>Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> >>>>---
> >>>> .../bindings/reset/qcom,pdc-reset.txt | 52 +++++++++++++++++++
> >>>> include/dt-bindings/reset/qcom,sdm845-pdc.h | 20 +++++++
> >>>> 2 files changed, 72 insertions(+)
> >>>> create mode 100644 Documentation/devicetree/bindings/reset/qcom,pdc-reset.txt
> >>>> create mode 100644 include/dt-bindings/reset/qcom,sdm845-pdc.h
> >>>>
> >>>>diff --git a/Documentation/devicetree/bindings/reset/qcom,pdc-reset.txt b/Documentation/devicetree/bindings/reset/qcom,pdc-reset.txt
> >>>>new file mode 100644
> >>>>index 000000000000..85e159962e08
> >>>>--- /dev/null
> >>>>+++ b/Documentation/devicetree/bindings/reset/qcom,pdc-reset.txt
> >>>>@@ -0,0 +1,52 @@
> >>>>+PDC Reset Controller
> >>>>+======================================
> >>>>+
> >>>>+This binding describes a reset-controller found on PDC-Global(Power Domain
> >>>>+Controller) block for Qualcomm Technologies Inc SDM845 SoCs.
> >>>>+
> >>>>+Required properties:
> >>>>+- compatible:
> >>>>+ Usage: required
> >>>>+ Value type: <string>
> >>>>+ Definition: must be:
> >>>>+ "qcom,sdm845-pdc-global"
> >>>>+
> >>>>+- reg:
> >>>>+ Usage: required
> >>>>+ Value type: <prop-encoded-array>
> >>>>+ Definition: must specify the base address and size of the register
> >>>>+ space.
> >>>>+
> >>>>+- #reset-cells:
> >>>>+ Usage: required
> >>>>+ Value type: <uint>
> >>>>+ Definition: must be 1; cell entry represents the reset index.
> >>>>+
> >>>>+Example:
> >>>>+
> >>>>+pdc_reset: reset-controller@b2e0000 {
> >>>
> >>>Is this really just a reset controller?
> >>>
> >>>The name makes it sound like a driver binding to this should also
> >>>provide pm_genpd and the binding should probably call this a power-
> >>>controller: Documentation/devicetree/bindings/power/power_domain.txt.
> >>>
> >>
> >>The PDC-global reg space which is a part of PDC-wrapper reg space seems
> >>to be only used for the reset lines.
> >>
> >>Couple of other drivers use other parts of the PDC-wrapper reg space:
> >>https://patchwork.kernel.org/patch/10223701/ (PDC-Interrupt controller)
> >>https://patchwork.kernel.org/patch/10255767/ (GMU-PDC incorrectly tries
> >>to occupy the entire pdc-wrapper reg space)
> >>
> >>since it couldn't be logically mapped into pdc-interrupt driver, it had
> >>to be included as a separate reset driver.
> >
> >You can't have overlapping regions in DT (well, you can because we have
> >to work-around existing DTs that do, but you shouldn't).
> >
> >A single node can be multiple providers such as interrupt controller and
> >reset controller. It's an OS problem to split that into multiple
> >drivers.
>
> There will be no overlaps. Jordan will be changing the dt binding of
> gmu_pdc so that there is no overlap I guess. What I meant to say is that
> pdc-global is a separate reg-space and currently has no other
> functionality other than exposing the reset lines.
Correct - the updated GPU DT will be:
reg = <0x506a000 0x30000>,
<0xb280000 0x10000>,
<0xb480000, 0x10000>;
reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
Jordan
--
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [relevance 0%]
* Re: [PATCH 1/4] dt-bindings: reset: Add PDC reset binding for SDM845 SoCs
2018-08-08 21:37 0% ` Jordan Crouse
@ 2018-08-08 22:48 0% ` Jordan Crouse
0 siblings, 0 replies; 200+ results
From: Jordan Crouse @ 2018-08-08 22:48 UTC (permalink / raw)
To: Sibi Sankar, Rob Herring, Philipp Zabel, bjorn.andersson,
linux-remoteproc, linux-kernel, devicetree, ohad, mark.rutland,
sricharan, akdwived, linux-arm-msm, tsoni, ilina
On Wed, Aug 08, 2018 at 03:37:24PM -0600, Jordan Crouse wrote:
> On Wed, Aug 08, 2018 at 09:14:05PM +0530, Sibi Sankar wrote:
> > Hi Rob,
> > Thanks for the review
> >
> > On 08/07/2018 11:46 PM, Rob Herring wrote:
> > >On Tue, Jul 31, 2018 at 06:27:24PM +0530, Sibi S wrote:
> > >>Hi Philipp,
> > >>Thanks for the review!
> > >>
> > >>On 07/31/2018 02:12 PM, Philipp Zabel wrote:
> > >>>Hi Sibi,
> > >>>
> > >>>On Fri, 2018-07-27 at 20:58 +0530, Sibi Sankar wrote:
> > >>>>Add SDM845 PDC (Power Domain Controller) reset controller binding
> > >>>>
> > >>>>Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> > >>>>---
> > >>>> .../bindings/reset/qcom,pdc-reset.txt | 52 +++++++++++++++++++
> > >>>> include/dt-bindings/reset/qcom,sdm845-pdc.h | 20 +++++++
> > >>>> 2 files changed, 72 insertions(+)
> > >>>> create mode 100644 Documentation/devicetree/bindings/reset/qcom,pdc-reset.txt
> > >>>> create mode 100644 include/dt-bindings/reset/qcom,sdm845-pdc.h
> > >>>>
> > >>>>diff --git a/Documentation/devicetree/bindings/reset/qcom,pdc-reset.txt b/Documentation/devicetree/bindings/reset/qcom,pdc-reset.txt
> > >>>>new file mode 100644
> > >>>>index 000000000000..85e159962e08
> > >>>>--- /dev/null
> > >>>>+++ b/Documentation/devicetree/bindings/reset/qcom,pdc-reset.txt
> > >>>>@@ -0,0 +1,52 @@
> > >>>>+PDC Reset Controller
> > >>>>+======================================
> > >>>>+
> > >>>>+This binding describes a reset-controller found on PDC-Global(Power Domain
> > >>>>+Controller) block for Qualcomm Technologies Inc SDM845 SoCs.
> > >>>>+
> > >>>>+Required properties:
> > >>>>+- compatible:
> > >>>>+ Usage: required
> > >>>>+ Value type: <string>
> > >>>>+ Definition: must be:
> > >>>>+ "qcom,sdm845-pdc-global"
> > >>>>+
> > >>>>+- reg:
> > >>>>+ Usage: required
> > >>>>+ Value type: <prop-encoded-array>
> > >>>>+ Definition: must specify the base address and size of the register
> > >>>>+ space.
> > >>>>+
> > >>>>+- #reset-cells:
> > >>>>+ Usage: required
> > >>>>+ Value type: <uint>
> > >>>>+ Definition: must be 1; cell entry represents the reset index.
> > >>>>+
> > >>>>+Example:
> > >>>>+
> > >>>>+pdc_reset: reset-controller@b2e0000 {
> > >>>
> > >>>Is this really just a reset controller?
> > >>>
> > >>>The name makes it sound like a driver binding to this should also
> > >>>provide pm_genpd and the binding should probably call this a power-
> > >>>controller: Documentation/devicetree/bindings/power/power_domain.txt.
> > >>>
> > >>
> > >>The PDC-global reg space which is a part of PDC-wrapper reg space seems
> > >>to be only used for the reset lines.
> > >>
> > >>Couple of other drivers use other parts of the PDC-wrapper reg space:
> > >>https://patchwork.kernel.org/patch/10223701/ (PDC-Interrupt controller)
> > >>https://patchwork.kernel.org/patch/10255767/ (GMU-PDC incorrectly tries
> > >>to occupy the entire pdc-wrapper reg space)
> > >>
> > >>since it couldn't be logically mapped into pdc-interrupt driver, it had
> > >>to be included as a separate reset driver.
> > >
> > >You can't have overlapping regions in DT (well, you can because we have
> > >to work-around existing DTs that do, but you shouldn't).
> > >
> > >A single node can be multiple providers such as interrupt controller and
> > >reset controller. It's an OS problem to split that into multiple
> > >drivers.
> >
> > There will be no overlaps. Jordan will be changing the dt binding of
> > gmu_pdc so that there is no overlap I guess. What I meant to say is that
> > pdc-global is a separate reg-space and currently has no other
> > functionality other than exposing the reset lines.
>
> Correct - the updated GPU DT will be:
>
> reg = <0x506a000 0x30000>,
> <0xb280000 0x10000>,
> <0xb480000, 0x10000>;
> reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
>
> Jordan
Code change: https://patchwork.freedesktop.org/patch/243513/
DT change: https://patchwork.freedesktop.org/patch/243539/
Jordan
--
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [relevance 0%]
* Re: [PATCH 1/4] dt-bindings: reset: Add PDC reset binding for SDM845 SoCs
2018-07-27 15:28 19% [PATCH 1/4] dt-bindings: reset: Add PDC reset binding for SDM845 SoCs Sibi Sankar
` (3 preceding siblings ...)
2018-07-31 8:42 0% ` [PATCH 1/4] dt-bindings: reset: Add PDC reset binding for " Philipp Zabel
@ 2018-08-21 22:08 0% ` Bjorn Andersson
4 siblings, 0 replies; 200+ results
From: Bjorn Andersson @ 2018-08-21 22:08 UTC (permalink / raw)
To: Sibi Sankar
Cc: p.zabel, robh+dt, linux-remoteproc, linux-kernel, devicetree,
ohad, mark.rutland, sricharan, akdwived, linux-arm-msm, tsoni
On Fri 27 Jul 08:28 PDT 2018, Sibi Sankar wrote:
> Add SDM845 PDC (Power Domain Controller) reset controller binding
>
Even though this is currently describing only a reset controller I think
this binding better be talking about the "PDC Global" hardware.
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
> .../bindings/reset/qcom,pdc-reset.txt | 52 +++++++++++++++++++
> include/dt-bindings/reset/qcom,sdm845-pdc.h | 20 +++++++
> 2 files changed, 72 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/reset/qcom,pdc-reset.txt
> create mode 100644 include/dt-bindings/reset/qcom,sdm845-pdc.h
>
> diff --git a/Documentation/devicetree/bindings/reset/qcom,pdc-reset.txt b/Documentation/devicetree/bindings/reset/qcom,pdc-reset.txt
Rename this qcom,pdc-global to match the compatible, and hardware name.
> new file mode 100644
> index 000000000000..85e159962e08
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/reset/qcom,pdc-reset.txt
> @@ -0,0 +1,52 @@
> +PDC Reset Controller
PDC Global
> +======================================
> +
> +This binding describes a reset-controller found on PDC-Global(Power Domain
> +Controller) block for Qualcomm Technologies Inc SDM845 SoCs.
This looks good.
> +
> +Required properties:
> +- compatible:
> + Usage: required
> + Value type: <string>
> + Definition: must be:
> + "qcom,sdm845-pdc-global"
> +
> +- reg:
> + Usage: required
> + Value type: <prop-encoded-array>
> + Definition: must specify the base address and size of the register
> + space.
> +
> +- #reset-cells:
> + Usage: required
> + Value type: <uint>
> + Definition: must be 1; cell entry represents the reset index.
> +
> +Example:
> +
> +pdc_reset: reset-controller@b2e0000 {
This is perfectly fine, in its current form it is a reset-controller.
> + compatible = "qcom,sdm845-pdc-global";
> + reg = <0xb2e0000 0x20000>;
> + #reset-cells = <1>;
> +};
> +
Apart from this, the binding looks good!
Regards,
Bjorn
^ permalink raw reply [relevance 0%]
* Re: [PATCH 2/4] reset: qcom: PDC (Power Domain Controller) reset controller
2018-07-27 15:28 16% ` [PATCH 2/4] reset: qcom: PDC (Power Domain Controller) reset controller Sibi Sankar
2018-07-31 8:51 0% ` Philipp Zabel
@ 2018-08-21 22:17 0% ` Bjorn Andersson
1 sibling, 0 replies; 200+ results
From: Bjorn Andersson @ 2018-08-21 22:17 UTC (permalink / raw)
To: Sibi Sankar
Cc: p.zabel, robh+dt, linux-remoteproc, linux-kernel, devicetree,
ohad, mark.rutland, sricharan, akdwived, linux-arm-msm, tsoni
On Fri 27 Jul 08:28 PDT 2018, Sibi Sankar wrote:
> Add reset controller for SDM845 SoC to control reset signals
> provided by PDC for Modem, Compute, Display, GPU, Debug, AOP,
> Sensors, Audio, SP and APPS
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
> drivers/reset/Kconfig | 9 +++
> drivers/reset/Makefile | 1 +
> drivers/reset/reset-qcom-pdc.c | 139 +++++++++++++++++++++++++++++++++
> 3 files changed, 149 insertions(+)
> create mode 100644 drivers/reset/reset-qcom-pdc.c
>
> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
> index 13d28fdbdbb5..5344e202a630 100644
> --- a/drivers/reset/Kconfig
> +++ b/drivers/reset/Kconfig
> @@ -98,6 +98,15 @@ config RESET_QCOM_AOSS
> reset signals provided by AOSS for Modem, Venus, ADSP,
> GPU, Camera, Wireless, Display subsystem. Otherwise, say N.
>
> +config RESET_QCOM_PDC
> + bool "Qcom PDC Reset Driver"
"Qualcomm"
And I do not see a strong reason for this not being tristate, the
consumers we've talked about so far can all be modules.
> + depends on ARCH_QCOM || COMPILE_TEST
> + help
> + This enables the PDC (Power Domain Controller) reset driver
> + for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want
> + to control reset signals provided by PDC for Modem, Compute,
> + Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS.
> +
Implementation looks fine.
Regards,
Bjorn
^ permalink raw reply [relevance 0%]
* Re: [PATCH 4/4] remoteproc: qcom: q6v5-pil: Add PDC restart for modem on SDM845 SoCs
2018-07-27 15:28 19% ` [PATCH 4/4] remoteproc: qcom: q6v5-pil: Add PDC restart for modem on SDM845 SoCs Sibi Sankar
2018-07-31 8:54 0% ` Philipp Zabel
2018-08-07 18:18 0% ` Rob Herring
@ 2018-08-21 22:33 0% ` Bjorn Andersson
2 siblings, 0 replies; 200+ results
From: Bjorn Andersson @ 2018-08-21 22:33 UTC (permalink / raw)
To: Sibi Sankar
Cc: p.zabel, robh+dt, linux-remoteproc, linux-kernel, devicetree,
ohad, mark.rutland, sricharan, akdwived, linux-arm-msm, tsoni
On Fri 27 Jul 08:28 PDT 2018, Sibi Sankar wrote:
> In the presence of a PDC block working with subsystem RSC,
> assert/deassert PDC restart in modem start/stop path.
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
> .../bindings/remoteproc/qcom,q6v5.txt | 4 +++
> drivers/remoteproc/qcom_q6v5_pil.c | 27 ++++++++++++++++---
> 2 files changed, 27 insertions(+), 4 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
> index 601dd9f389aa..124fb1dc6fb8 100644
> --- a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
> +++ b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
> @@ -51,6 +51,8 @@ on the Qualcomm Hexagon core.
> Usage: required
> Value type: <phandle>
> Definition: reference to the reset-controller for the modem sub-system
> + reference to the list of 2 reset-controllers for the modem
> + sub-system on SDM845 SoCs
> reference to the list of 3 reset-controllers for the
> wcss sub-system
>
> @@ -58,6 +60,8 @@ on the Qualcomm Hexagon core.
> Usage: required
> Value type: <stringlist>
> Definition: must be "mss_restart" for the modem sub-system
> + Definition: must be "mss_restart", "pdc_restart" for the modem
> + sub-system on SDM845 SoCs
> Definition: must be "wcss_aon_reset", "wcss_reset", "wcss_q6_reset"
> for the wcss syb-system
Seems like we got an additional "Definition:" added here as we added the
wcss. Please don't add another one.
The rest looks good.
Regards,
Bjorn
^ permalink raw reply [relevance 0%]
* [PATCH v2 0/6] Add support for PDC Global on SDM845 SoCs
@ 2018-08-24 13:18 13% Sibi Sankar
2018-08-24 13:18 19% ` [PATCH v2 1/6] dt-bindings: reset: Add PDC Global binding for " Sibi Sankar
` (5 more replies)
0 siblings, 6 replies; 200+ results
From: Sibi Sankar @ 2018-08-24 13:18 UTC (permalink / raw)
To: bjorn.andersson, p.zabel, robh+dt
Cc: linux-remoteproc, linux-kernel, devicetree, ohad, mark.rutland,
sricharan, akdwived, linux-arm-msm, tsoni, Sibi Sankar
This patch series add support for PDC Global (Power Domain Controller)
on SDM845 SoCs and adds pdc reset lines assert/deassert to remoteproc
Q6v5 modem-pil. The first two patches adds PDC Global reset driver to
control reset signals of Modem, Compute, Display, GPU, Debug, AOP,
Sensors, Audio, SP and APPS. The last four patches (cleans up)/adds pdc
reset lines to q6v5 bindings and asserts/deasserts in modem start/stop
path.
v2:
Incorporated Philipp/Bjorn/Rob suggestions
Renamed reset binding to pdc-global.txt
replaced offset with #define of register name
replaced with devm_reset_control_get_exclusive()
Separted dt binding from the drivers
The last 4 remoteproc patches can be picked up after the pdc global
reset driver lands on linux-next.
Sibi Sankar (6):
dt-bindings: reset: Add PDC Global binding for SDM845 SoCs
reset: qcom: PDC Global (Power Domain Controller) reset controller
dt-bindings: remoteproc: Remove additional definition tag
dt-bindings: remoteproc: Add PDC reset binding for Q6V5 PIL
remoteproc: qcom: q6v5-pil: Explicitly get mss_restart line
remoteproc: qcom: q6v5-pil: Add PDC reset for modem on SDM845 SoCs
.../bindings/remoteproc/qcom,q6v5.txt | 6 +-
.../bindings/reset/qcom,pdc-global.txt | 52 +++++++
drivers/remoteproc/qcom_q6v5_pil.c | 31 +++-
drivers/reset/Kconfig | 9 ++
drivers/reset/Makefile | 1 +
drivers/reset/reset-qcom-pdc.c | 142 ++++++++++++++++++
include/dt-bindings/reset/qcom,sdm845-pdc.h | 20 +++
7 files changed, 254 insertions(+), 7 deletions(-)
create mode 100644 Documentation/devicetree/bindings/reset/qcom,pdc-global.txt
create mode 100644 drivers/reset/reset-qcom-pdc.c
create mode 100644 include/dt-bindings/reset/qcom,sdm845-pdc.h
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [relevance 13%]
* [PATCH v2 1/6] dt-bindings: reset: Add PDC Global binding for SDM845 SoCs
2018-08-24 13:18 13% [PATCH v2 0/6] Add support for PDC Global on SDM845 SoCs Sibi Sankar
@ 2018-08-24 13:18 19% ` Sibi Sankar
2018-08-28 0:33 0% ` Bjorn Andersson
` (2 more replies)
2018-08-24 13:18 16% ` [PATCH v2 2/6] reset: qcom: PDC Global (Power Domain Controller) reset controller Sibi Sankar
` (4 subsequent siblings)
5 siblings, 3 replies; 200+ results
From: Sibi Sankar @ 2018-08-24 13:18 UTC (permalink / raw)
To: bjorn.andersson, p.zabel, robh+dt
Cc: linux-remoteproc, linux-kernel, devicetree, ohad, mark.rutland,
sricharan, akdwived, linux-arm-msm, tsoni, Sibi Sankar
Add PDC Global(Power Domain Controller) binding for SDM845 SoCs.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
.../bindings/reset/qcom,pdc-global.txt | 52 +++++++++++++++++++
include/dt-bindings/reset/qcom,sdm845-pdc.h | 20 +++++++
2 files changed, 72 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/qcom,pdc-global.txt
create mode 100644 include/dt-bindings/reset/qcom,sdm845-pdc.h
diff --git a/Documentation/devicetree/bindings/reset/qcom,pdc-global.txt b/Documentation/devicetree/bindings/reset/qcom,pdc-global.txt
new file mode 100644
index 000000000000..69f9edca9503
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/qcom,pdc-global.txt
@@ -0,0 +1,52 @@
+PDC Global
+======================================
+
+This binding describes a reset-controller found on PDC-Global(Power Domain
+Controller) block for Qualcomm Technologies Inc SDM845 SoCs.
+
+Required properties:
+- compatible:
+ Usage: required
+ Value type: <string>
+ Definition: must be:
+ "qcom,sdm845-pdc-global"
+
+- reg:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: must specify the base address and size of the register
+ space.
+
+- #reset-cells:
+ Usage: required
+ Value type: <uint>
+ Definition: must be 1; cell entry represents the reset index.
+
+Example:
+
+pdc_reset: reset-controller@b2e0000 {
+ compatible = "qcom,sdm845-pdc-global";
+ reg = <0xb2e0000 0x20000>;
+ #reset-cells = <1>;
+};
+
+PDC reset clients
+======================================
+
+Device nodes that need access to reset lines should
+specify them as a reset phandle in their corresponding node as
+specified in reset.txt.
+
+For list of all valid reset indicies see
+<dt-bindings/reset/qcom,sdm845-pdc.h>
+
+Example:
+
+modem-pil@4080000 {
+ ...
+
+ resets = <&pdc_reset PDC_MODEM_SYNC_RESET>;
+ reset-names = "pdc_reset";
+
+ ...
+};
diff --git a/include/dt-bindings/reset/qcom,sdm845-pdc.h b/include/dt-bindings/reset/qcom,sdm845-pdc.h
new file mode 100644
index 000000000000..53c37f9c319a
--- /dev/null
+++ b/include/dt-bindings/reset/qcom,sdm845-pdc.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_RESET_PDC_SDM_845_H
+#define _DT_BINDINGS_RESET_PDC_SDM_845_H
+
+#define PDC_APPS_SYNC_RESET 0
+#define PDC_SP_SYNC_RESET 1
+#define PDC_AUDIO_SYNC_RESET 2
+#define PDC_SENSORS_SYNC_RESET 3
+#define PDC_AOP_SYNC_RESET 4
+#define PDC_DEBUG_SYNC_RESET 5
+#define PDC_GPU_SYNC_RESET 6
+#define PDC_DISPLAY_SYNC_RESET 7
+#define PDC_COMPUTE_SYNC_RESET 8
+#define PDC_MODEM_SYNC_RESET 9
+
+#endif
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 19%]
* [PATCH v2 2/6] reset: qcom: PDC Global (Power Domain Controller) reset controller
2018-08-24 13:18 13% [PATCH v2 0/6] Add support for PDC Global on SDM845 SoCs Sibi Sankar
2018-08-24 13:18 19% ` [PATCH v2 1/6] dt-bindings: reset: Add PDC Global binding for " Sibi Sankar
@ 2018-08-24 13:18 16% ` Sibi Sankar
2018-08-28 0:22 0% ` Matthias Kaehlcke
2018-08-24 13:18 21% ` [PATCH v2 3/6] dt-bindings: remoteproc: Remove additional definition tag Sibi Sankar
` (3 subsequent siblings)
5 siblings, 1 reply; 200+ results
From: Sibi Sankar @ 2018-08-24 13:18 UTC (permalink / raw)
To: bjorn.andersson, p.zabel, robh+dt
Cc: linux-remoteproc, linux-kernel, devicetree, ohad, mark.rutland,
sricharan, akdwived, linux-arm-msm, tsoni, Sibi Sankar
Add reset controller for SDM845 SoCs to control reset signals provided
by PDC Global for Modem, Compute, Display, GPU, Debug, AOP, Sensors,
Audio, SP and APPS
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
drivers/reset/Kconfig | 9 +++
drivers/reset/Makefile | 1 +
drivers/reset/reset-qcom-pdc.c | 142 +++++++++++++++++++++++++++++++++
3 files changed, 152 insertions(+)
create mode 100644 drivers/reset/reset-qcom-pdc.c
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 13d28fdbdbb5..c21da9fe51ec 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -98,6 +98,15 @@ config RESET_QCOM_AOSS
reset signals provided by AOSS for Modem, Venus, ADSP,
GPU, Camera, Wireless, Display subsystem. Otherwise, say N.
+config RESET_QCOM_PDC
+ tristate "Qualcomm PDC Reset Driver"
+ depends on ARCH_QCOM || COMPILE_TEST
+ help
+ This enables the PDC (Power Domain Controller) reset driver
+ for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want
+ to control reset signals provided by PDC for Modem, Compute,
+ Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS.
+
config RESET_SIMPLE
bool "Simple Reset Controller Driver" if COMPILE_TEST
default ARCH_SOCFPGA || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 4243c38228e2..d08e8b90046a 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_RESET_MESON_AUDIO_ARB) += reset-meson-audio-arb.o
obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o
obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o
+obj-$(CONFIG_RESET_QCOM_PDC) += reset-qcom-pdc.o
obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
obj-$(CONFIG_RESET_STM32MP157) += reset-stm32mp1.o
obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
diff --git a/drivers/reset/reset-qcom-pdc.c b/drivers/reset/reset-qcom-pdc.c
new file mode 100644
index 000000000000..bb6a5e5ee0f8
--- /dev/null
+++ b/drivers/reset/reset-qcom-pdc.c
@@ -0,0 +1,142 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+#include <linux/regmap.h>
+#include <linux/of_device.h>
+#include <dt-bindings/reset/qcom,sdm845-pdc.h>
+
+#define RPMH_PDC_SYNC_RESET 0x100
+
+struct qcom_pdc_reset_map {
+ u8 bit;
+};
+
+struct qcom_pdc_desc {
+ const struct regmap_config *config;
+ const struct qcom_pdc_reset_map *resets;
+ size_t num_resets;
+};
+
+struct qcom_pdc_reset_data {
+ struct reset_controller_dev rcdev;
+ struct regmap *regmap;
+ const struct qcom_pdc_desc *desc;
+};
+
+static const struct regmap_config sdm845_pdc_regmap_config = {
+ .name = "pdc-reset",
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x20000,
+ .fast_io = true,
+};
+
+static const struct qcom_pdc_reset_map sdm845_pdc_resets[] = {
+ [PDC_APPS_SYNC_RESET] = {0},
+ [PDC_SP_SYNC_RESET] = {1},
+ [PDC_AUDIO_SYNC_RESET] = {2},
+ [PDC_SENSORS_SYNC_RESET] = {3},
+ [PDC_AOP_SYNC_RESET] = {4},
+ [PDC_DEBUG_SYNC_RESET] = {5},
+ [PDC_GPU_SYNC_RESET] = {6},
+ [PDC_DISPLAY_SYNC_RESET] = {7},
+ [PDC_COMPUTE_SYNC_RESET] = {8},
+ [PDC_MODEM_SYNC_RESET] = {9},
+};
+
+static const struct qcom_pdc_desc sdm845_pdc_desc = {
+ .config = &sdm845_pdc_regmap_config,
+ .resets = sdm845_pdc_resets,
+ .num_resets = ARRAY_SIZE(sdm845_pdc_resets),
+};
+
+static inline struct qcom_pdc_reset_data *to_qcom_pdc_reset_data(
+ struct reset_controller_dev *rcdev)
+{
+ return container_of(rcdev, struct qcom_pdc_reset_data, rcdev);
+}
+
+static int qcom_pdc_control_assert(struct reset_controller_dev *rcdev,
+ unsigned long idx)
+{
+ struct qcom_pdc_reset_data *data = to_qcom_pdc_reset_data(rcdev);
+ const struct qcom_pdc_reset_map *map = &data->desc->resets[idx];
+
+ return regmap_update_bits(data->regmap, RPMH_PDC_SYNC_RESET,
+ BIT(map->bit), BIT(map->bit));
+}
+
+static int qcom_pdc_control_deassert(struct reset_controller_dev *rcdev,
+ unsigned long idx)
+{
+ struct qcom_pdc_reset_data *data = to_qcom_pdc_reset_data(rcdev);
+ const struct qcom_pdc_reset_map *map = &data->desc->resets[idx];
+
+ return regmap_update_bits(data->regmap, RPMH_PDC_SYNC_RESET,
+ BIT(map->bit), 0);
+}
+
+static const struct reset_control_ops qcom_pdc_reset_ops = {
+ .assert = qcom_pdc_control_assert,
+ .deassert = qcom_pdc_control_deassert,
+};
+
+static int qcom_pdc_reset_probe(struct platform_device *pdev)
+{
+ struct qcom_pdc_reset_data *data;
+ struct device *dev = &pdev->dev;
+ const struct qcom_pdc_desc *desc;
+ void __iomem *base;
+ struct resource *res;
+
+ desc = of_device_get_match_data(dev);
+ if (!desc)
+ return -EINVAL;
+
+ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ data->desc = desc;
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ data->regmap = devm_regmap_init_mmio(dev, base, desc->config);
+ if (IS_ERR(data->regmap)) {
+ dev_err(dev, "Unable to get pdc-global regmap");
+ return PTR_ERR(data->regmap);
+ }
+
+ data->rcdev.owner = THIS_MODULE;
+ data->rcdev.ops = &qcom_pdc_reset_ops;
+ data->rcdev.nr_resets = desc->num_resets;
+ data->rcdev.of_node = dev->of_node;
+
+ return devm_reset_controller_register(dev, &data->rcdev);
+}
+
+static const struct of_device_id qcom_pdc_reset_of_match[] = {
+ { .compatible = "qcom,sdm845-pdc-global", .data = &sdm845_pdc_desc },
+ {}
+};
+MODULE_DEVICE_TABLE(of, qcom_pdc_reset_of_match);
+
+static struct platform_driver qcom_pdc_reset_driver = {
+ .probe = qcom_pdc_reset_probe,
+ .driver = {
+ .name = "qcom_pdc_reset",
+ .of_match_table = qcom_pdc_reset_of_match,
+ },
+};
+module_platform_driver(qcom_pdc_reset_driver);
+
+MODULE_DESCRIPTION("Qualcomm PDC Reset Driver");
+MODULE_LICENSE("GPL v2");
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 16%]
* [PATCH v2 3/6] dt-bindings: remoteproc: Remove additional definition tag
2018-08-24 13:18 13% [PATCH v2 0/6] Add support for PDC Global on SDM845 SoCs Sibi Sankar
2018-08-24 13:18 19% ` [PATCH v2 1/6] dt-bindings: reset: Add PDC Global binding for " Sibi Sankar
2018-08-24 13:18 16% ` [PATCH v2 2/6] reset: qcom: PDC Global (Power Domain Controller) reset controller Sibi Sankar
@ 2018-08-24 13:18 21% ` Sibi Sankar
2018-08-28 0:44 0% ` Matthias Kaehlcke
2018-08-24 13:18 20% ` [PATCH v2 4/6] dt-bindings: remoteproc: Add PDC reset binding for Q6V5 PIL Sibi Sankar
` (2 subsequent siblings)
5 siblings, 1 reply; 200+ results
From: Sibi Sankar @ 2018-08-24 13:18 UTC (permalink / raw)
To: bjorn.andersson, p.zabel, robh+dt
Cc: linux-remoteproc, linux-kernel, devicetree, ohad, mark.rutland,
sricharan, akdwived, linux-arm-msm, tsoni, Sibi Sankar
Remove the additional definition tag declared for WCSS sub-system
under reset-names.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
index 601dd9f389aa..c45e4c131fa2 100644
--- a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
+++ b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
@@ -58,7 +58,7 @@ on the Qualcomm Hexagon core.
Usage: required
Value type: <stringlist>
Definition: must be "mss_restart" for the modem sub-system
- Definition: must be "wcss_aon_reset", "wcss_reset", "wcss_q6_reset"
+ must be "wcss_aon_reset", "wcss_reset", "wcss_q6_reset"
for the wcss syb-system
- cx-supply:
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 21%]
* [PATCH v2 4/6] dt-bindings: remoteproc: Add PDC reset binding for Q6V5 PIL
2018-08-24 13:18 13% [PATCH v2 0/6] Add support for PDC Global on SDM845 SoCs Sibi Sankar
` (2 preceding siblings ...)
2018-08-24 13:18 21% ` [PATCH v2 3/6] dt-bindings: remoteproc: Remove additional definition tag Sibi Sankar
@ 2018-08-24 13:18 20% ` Sibi Sankar
2018-08-29 0:44 0% ` Rob Herring
2018-08-24 13:18 21% ` [PATCH v2 5/6] remoteproc: qcom: q6v5-pil: Explicitly get mss_restart line Sibi Sankar
2018-08-24 13:19 19% ` [PATCH v2 6/6] remoteproc: qcom: q6v5-pil: Add PDC reset for modem on SDM845 SoCs Sibi Sankar
5 siblings, 1 reply; 200+ results
From: Sibi Sankar @ 2018-08-24 13:18 UTC (permalink / raw)
To: bjorn.andersson, p.zabel, robh+dt
Cc: linux-remoteproc, linux-kernel, devicetree, ohad, mark.rutland,
sricharan, akdwived, linux-arm-msm, tsoni, Sibi Sankar
Add additional pdc_reset binding required for Q6V5 Modem PIL on
SDM845 SoCs.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
index c45e4c131fa2..4c5473aeb697 100644
--- a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
+++ b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
@@ -53,6 +53,8 @@ on the Qualcomm Hexagon core.
Definition: reference to the reset-controller for the modem sub-system
reference to the list of 3 reset-controllers for the
wcss sub-system
+ reference to the list of 2 reset-controllers for the modem
+ sub-system on SDM845 SoCs
- reset-names:
Usage: required
@@ -60,6 +62,8 @@ on the Qualcomm Hexagon core.
Definition: must be "mss_restart" for the modem sub-system
must be "wcss_aon_reset", "wcss_reset", "wcss_q6_reset"
for the wcss syb-system
+ must be "mss_restart", "pdc_reset" for the modem
+ sub-system on SDM845 SoCs
- cx-supply:
- mss-supply:
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 20%]
* [PATCH v2 5/6] remoteproc: qcom: q6v5-pil: Explicitly get mss_restart line
2018-08-24 13:18 13% [PATCH v2 0/6] Add support for PDC Global on SDM845 SoCs Sibi Sankar
` (3 preceding siblings ...)
2018-08-24 13:18 20% ` [PATCH v2 4/6] dt-bindings: remoteproc: Add PDC reset binding for Q6V5 PIL Sibi Sankar
@ 2018-08-24 13:18 21% ` Sibi Sankar
2018-08-24 13:19 19% ` [PATCH v2 6/6] remoteproc: qcom: q6v5-pil: Add PDC reset for modem on SDM845 SoCs Sibi Sankar
5 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2018-08-24 13:18 UTC (permalink / raw)
To: bjorn.andersson, p.zabel, robh+dt
Cc: linux-remoteproc, linux-kernel, devicetree, ohad, mark.rutland,
sricharan, akdwived, linux-arm-msm, tsoni, Sibi Sankar
Explicitly get mss_restart to facilitate adding PDC reset line
for modem on SDM845 SoCs
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
drivers/remoteproc/qcom_q6v5_pil.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
index b1296d614b8b..968413edf0c8 100644
--- a/drivers/remoteproc/qcom_q6v5_pil.c
+++ b/drivers/remoteproc/qcom_q6v5_pil.c
@@ -1177,7 +1177,7 @@ static int q6v5_init_clocks(struct device *dev, struct clk **clks,
static int q6v5_init_reset(struct q6v5 *qproc)
{
qproc->mss_restart = devm_reset_control_get_exclusive(qproc->dev,
- NULL);
+ "mss_restart");
if (IS_ERR(qproc->mss_restart)) {
dev_err(qproc->dev, "failed to acquire mss restart\n");
return PTR_ERR(qproc->mss_restart);
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 21%]
* [PATCH v2 6/6] remoteproc: qcom: q6v5-pil: Add PDC reset for modem on SDM845 SoCs
2018-08-24 13:18 13% [PATCH v2 0/6] Add support for PDC Global on SDM845 SoCs Sibi Sankar
` (4 preceding siblings ...)
2018-08-24 13:18 21% ` [PATCH v2 5/6] remoteproc: qcom: q6v5-pil: Explicitly get mss_restart line Sibi Sankar
@ 2018-08-24 13:19 19% ` Sibi Sankar
5 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2018-08-24 13:19 UTC (permalink / raw)
To: bjorn.andersson, p.zabel, robh+dt
Cc: linux-remoteproc, linux-kernel, devicetree, ohad, mark.rutland,
sricharan, akdwived, linux-arm-msm, tsoni, Sibi Sankar
In the presence of a PDC block working with subsystem RSC, assert/deassert
PDC reset in modem start/stop path.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
drivers/remoteproc/qcom_q6v5_pil.c | 29 ++++++++++++++++++++++++-----
1 file changed, 24 insertions(+), 5 deletions(-)
diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
index 968413edf0c8..835fa005fe3e 100644
--- a/drivers/remoteproc/qcom_q6v5_pil.c
+++ b/drivers/remoteproc/qcom_q6v5_pil.c
@@ -149,6 +149,7 @@ struct q6v5 {
u32 halt_nc;
struct reset_control *mss_restart;
+ struct reset_control *pdc_reset;
struct qcom_q6v5 q6v5;
@@ -349,10 +350,17 @@ static int q6v5_load(struct rproc *rproc, const struct firmware *fw)
static int q6v5_reset_assert(struct q6v5 *qproc)
{
- if (qproc->has_alt_reset)
- return reset_control_reset(qproc->mss_restart);
- else
- return reset_control_assert(qproc->mss_restart);
+ int ret;
+
+ if (qproc->has_alt_reset) {
+ reset_control_assert(qproc->pdc_reset);
+ ret = reset_control_reset(qproc->mss_restart);
+ reset_control_deassert(qproc->pdc_reset);
+ } else {
+ ret = reset_control_assert(qproc->mss_restart);
+ }
+
+ return ret;
}
static int q6v5_reset_deassert(struct q6v5 *qproc)
@@ -360,9 +368,11 @@ static int q6v5_reset_deassert(struct q6v5 *qproc)
int ret;
if (qproc->has_alt_reset) {
+ reset_control_assert(qproc->pdc_reset);
writel(1, qproc->rmb_base + RMB_MBA_ALT_RESET);
ret = reset_control_reset(qproc->mss_restart);
writel(0, qproc->rmb_base + RMB_MBA_ALT_RESET);
+ reset_control_deassert(qproc->pdc_reset);
} else {
ret = reset_control_deassert(qproc->mss_restart);
}
@@ -1183,6 +1193,15 @@ static int q6v5_init_reset(struct q6v5 *qproc)
return PTR_ERR(qproc->mss_restart);
}
+ if (qproc->has_alt_reset) {
+ qproc->pdc_reset = devm_reset_control_get_exclusive(qproc->dev,
+ "pdc_reset");
+ if (IS_ERR(qproc->pdc_reset)) {
+ dev_err(qproc->dev, "failed to acquire pdc reset\n");
+ return PTR_ERR(qproc->pdc_reset);
+ }
+ }
+
return 0;
}
@@ -1303,12 +1322,12 @@ static int q6v5_probe(struct platform_device *pdev)
}
qproc->active_reg_count = ret;
+ qproc->has_alt_reset = desc->has_alt_reset;
ret = q6v5_init_reset(qproc);
if (ret)
goto free_rproc;
qproc->version = desc->version;
- qproc->has_alt_reset = desc->has_alt_reset;
qproc->need_mem_protection = desc->need_mem_protection;
ret = qcom_q6v5_init(&qproc->q6v5, pdev, rproc, MPSS_CRASH_REASON_SMEM,
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 19%]
* Re: [PATCH v2 2/6] reset: qcom: PDC Global (Power Domain Controller) reset controller
2018-08-24 13:18 16% ` [PATCH v2 2/6] reset: qcom: PDC Global (Power Domain Controller) reset controller Sibi Sankar
@ 2018-08-28 0:22 0% ` Matthias Kaehlcke
0 siblings, 1 reply; 200+ results
From: Matthias Kaehlcke @ 2018-08-28 0:22 UTC (permalink / raw)
To: Sibi Sankar
Cc: bjorn.andersson, p.zabel, robh+dt, linux-remoteproc,
linux-kernel, devicetree, ohad, mark.rutland, sricharan,
akdwived, linux-arm-msm, tsoni
Hi Sibi,
On Fri, Aug 24, 2018 at 06:48:56PM +0530, Sibi Sankar wrote:
> Add reset controller for SDM845 SoCs to control reset signals provided
> by PDC Global for Modem, Compute, Display, GPU, Debug, AOP, Sensors,
> Audio, SP and APPS
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
> drivers/reset/Kconfig | 9 +++
> drivers/reset/Makefile | 1 +
> drivers/reset/reset-qcom-pdc.c | 142 +++++++++++++++++++++++++++++++++
> 3 files changed, 152 insertions(+)
> create mode 100644 drivers/reset/reset-qcom-pdc.c
>
> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
> index 13d28fdbdbb5..c21da9fe51ec 100644
> --- a/drivers/reset/Kconfig
> +++ b/drivers/reset/Kconfig
> @@ -98,6 +98,15 @@ config RESET_QCOM_AOSS
> reset signals provided by AOSS for Modem, Venus, ADSP,
> GPU, Camera, Wireless, Display subsystem. Otherwise, say N.
>
> +config RESET_QCOM_PDC
> + tristate "Qualcomm PDC Reset Driver"
> + depends on ARCH_QCOM || COMPILE_TEST
> + help
> + This enables the PDC (Power Domain Controller) reset driver
> + for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want
> + to control reset signals provided by PDC for Modem, Compute,
> + Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS.
What exactly does APPS mean? The AP cores, the entire SoC, something
else?
> +
> config RESET_SIMPLE
> bool "Simple Reset Controller Driver" if COMPILE_TEST
> default ARCH_SOCFPGA || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED
> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
> index 4243c38228e2..d08e8b90046a 100644
> --- a/drivers/reset/Makefile
> +++ b/drivers/reset/Makefile
> @@ -16,6 +16,7 @@ obj-$(CONFIG_RESET_MESON_AUDIO_ARB) += reset-meson-audio-arb.o
> obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
> obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o
> obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o
> +obj-$(CONFIG_RESET_QCOM_PDC) += reset-qcom-pdc.o
> obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
> obj-$(CONFIG_RESET_STM32MP157) += reset-stm32mp1.o
> obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
> diff --git a/drivers/reset/reset-qcom-pdc.c b/drivers/reset/reset-qcom-pdc.c
> new file mode 100644
> index 000000000000..bb6a5e5ee0f8
> --- /dev/null
> +++ b/drivers/reset/reset-qcom-pdc.c
> @@ -0,0 +1,142 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2018 The Linux Foundation. All rights reserved.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/reset-controller.h>
> +#include <linux/regmap.h>
> +#include <linux/of_device.h>
> +#include <dt-bindings/reset/qcom,sdm845-pdc.h>
Headers should be sorted in alphabetical order.
> +
> +#define RPMH_PDC_SYNC_RESET 0x100
> +
> +struct qcom_pdc_reset_map {
> + u8 bit;
> +};
> +
> +struct qcom_pdc_desc {
> + const struct regmap_config *config;
> + const struct qcom_pdc_reset_map *resets;
> + size_t num_resets;
> +};
Not sure if this structure adds much value or just a layer of
indirection:
- .config is only accessed in _probe(), sdm845_pdc_regmap_config could
be used directly
- .resets is used in _(de)assert(), sdm845_pdc_resets could be used
directly
- .num_resets is only accessed in _probe(),
ARRAY_SIZE(sdm845_pdc_resets) could be used instead
It probably makes sense if it is planned to support reset controllers
of other SoCs with this driver.
> +struct qcom_pdc_reset_data {
> + struct reset_controller_dev rcdev;
> + struct regmap *regmap;
> + const struct qcom_pdc_desc *desc;
> +};
> +
> +static const struct regmap_config sdm845_pdc_regmap_config = {
> + .name = "pdc-reset",
> + .reg_bits = 32,
> + .reg_stride = 4,
> + .val_bits = 32,
> + .max_register = 0x20000,
> + .fast_io = true,
> +};
> +
> +static const struct qcom_pdc_reset_map sdm845_pdc_resets[] = {
> + [PDC_APPS_SYNC_RESET] = {0},
> + [PDC_SP_SYNC_RESET] = {1},
> + [PDC_AUDIO_SYNC_RESET] = {2},
> + [PDC_SENSORS_SYNC_RESET] = {3},
> + [PDC_AOP_SYNC_RESET] = {4},
> + [PDC_DEBUG_SYNC_RESET] = {5},
> + [PDC_GPU_SYNC_RESET] = {6},
> + [PDC_DISPLAY_SYNC_RESET] = {7},
> + [PDC_COMPUTE_SYNC_RESET] = {8},
> + [PDC_MODEM_SYNC_RESET] = {9},
> +};
> +
> +static const struct qcom_pdc_desc sdm845_pdc_desc = {
> + .config = &sdm845_pdc_regmap_config,
> + .resets = sdm845_pdc_resets,
> + .num_resets = ARRAY_SIZE(sdm845_pdc_resets),
> +};
> +
> +static inline struct qcom_pdc_reset_data *to_qcom_pdc_reset_data(
> + struct reset_controller_dev *rcdev)
> +{
> + return container_of(rcdev, struct qcom_pdc_reset_data, rcdev);
> +}
> +
> +static int qcom_pdc_control_assert(struct reset_controller_dev *rcdev,
> + unsigned long idx)
> +{
> + struct qcom_pdc_reset_data *data = to_qcom_pdc_reset_data(rcdev);
> + const struct qcom_pdc_reset_map *map = &data->desc->resets[idx];
> +
> + return regmap_update_bits(data->regmap, RPMH_PDC_SYNC_RESET,
> + BIT(map->bit), BIT(map->bit));
> +}
> +
> +static int qcom_pdc_control_deassert(struct reset_controller_dev *rcdev,
> + unsigned long idx)
> +{
> + struct qcom_pdc_reset_data *data = to_qcom_pdc_reset_data(rcdev);
> + const struct qcom_pdc_reset_map *map = &data->desc->resets[idx];
> +
> + return regmap_update_bits(data->regmap, RPMH_PDC_SYNC_RESET,
> + BIT(map->bit), 0);
> +}
> +
> +static const struct reset_control_ops qcom_pdc_reset_ops = {
> + .assert = qcom_pdc_control_assert,
> + .deassert = qcom_pdc_control_deassert,
> +};
> +
> +static int qcom_pdc_reset_probe(struct platform_device *pdev)
> +{
> + struct qcom_pdc_reset_data *data;
> + struct device *dev = &pdev->dev;
> + const struct qcom_pdc_desc *desc;
> + void __iomem *base;
> + struct resource *res;
> +
> + desc = of_device_get_match_data(dev);
> + if (!desc)
> + return -EINVAL;
> +
> + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
> + if (!data)
> + return -ENOMEM;
> +
> + data->desc = desc;
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + base = devm_ioremap_resource(dev, res);
> + if (IS_ERR(base))
> + return PTR_ERR(base);
> +
> + data->regmap = devm_regmap_init_mmio(dev, base, desc->config);
> + if (IS_ERR(data->regmap)) {
> + dev_err(dev, "Unable to get pdc-global regmap");
Add missing '\n'
Say 'pdc-reset' instead of 'pdc-global'? (see also my other comment
below).
> + return PTR_ERR(data->regmap);
> + }
> +
> + data->rcdev.owner = THIS_MODULE;
> + data->rcdev.ops = &qcom_pdc_reset_ops;
> + data->rcdev.nr_resets = desc->num_resets;
> + data->rcdev.of_node = dev->of_node;
> +
> + return devm_reset_controller_register(dev, &data->rcdev);
> +}
> +
> +static const struct of_device_id qcom_pdc_reset_of_match[] = {
> + { .compatible = "qcom,sdm845-pdc-global", .data = &sdm845_pdc_desc },
Should this be 'qcom,sdm845-pdc-reset' which is more specific than
'global' and in line with the name and purpose of the driver?
Obviously this would require to adjust the bindings doc too.
Cheers
Matthias
^ permalink raw reply [relevance 0%]
* Re: [PATCH v2 1/6] dt-bindings: reset: Add PDC Global binding for SDM845 SoCs
2018-08-24 13:18 19% ` [PATCH v2 1/6] dt-bindings: reset: Add PDC Global binding for " Sibi Sankar
@ 2018-08-28 0:33 0% ` Bjorn Andersson
2018-08-28 0:38 0% ` Matthias Kaehlcke
2018-08-29 0:43 0% ` Rob Herring
2 siblings, 0 replies; 200+ results
From: Bjorn Andersson @ 2018-08-28 0:33 UTC (permalink / raw)
To: Sibi Sankar
Cc: p.zabel, robh+dt, linux-remoteproc, linux-kernel, devicetree,
ohad, mark.rutland, sricharan, akdwived, linux-arm-msm, tsoni
On Fri 24 Aug 06:18 PDT 2018, Sibi Sankar wrote:
> Add PDC Global(Power Domain Controller) binding for SDM845 SoCs.
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Regards,
Bjorn
> ---
> .../bindings/reset/qcom,pdc-global.txt | 52 +++++++++++++++++++
> include/dt-bindings/reset/qcom,sdm845-pdc.h | 20 +++++++
> 2 files changed, 72 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/reset/qcom,pdc-global.txt
> create mode 100644 include/dt-bindings/reset/qcom,sdm845-pdc.h
>
> diff --git a/Documentation/devicetree/bindings/reset/qcom,pdc-global.txt b/Documentation/devicetree/bindings/reset/qcom,pdc-global.txt
> new file mode 100644
> index 000000000000..69f9edca9503
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/reset/qcom,pdc-global.txt
> @@ -0,0 +1,52 @@
> +PDC Global
> +======================================
> +
> +This binding describes a reset-controller found on PDC-Global(Power Domain
> +Controller) block for Qualcomm Technologies Inc SDM845 SoCs.
> +
> +Required properties:
> +- compatible:
> + Usage: required
> + Value type: <string>
> + Definition: must be:
> + "qcom,sdm845-pdc-global"
> +
> +- reg:
> + Usage: required
> + Value type: <prop-encoded-array>
> + Definition: must specify the base address and size of the register
> + space.
> +
> +- #reset-cells:
> + Usage: required
> + Value type: <uint>
> + Definition: must be 1; cell entry represents the reset index.
> +
> +Example:
> +
> +pdc_reset: reset-controller@b2e0000 {
> + compatible = "qcom,sdm845-pdc-global";
> + reg = <0xb2e0000 0x20000>;
> + #reset-cells = <1>;
> +};
> +
> +PDC reset clients
> +======================================
> +
> +Device nodes that need access to reset lines should
> +specify them as a reset phandle in their corresponding node as
> +specified in reset.txt.
> +
> +For list of all valid reset indicies see
> +<dt-bindings/reset/qcom,sdm845-pdc.h>
> +
> +Example:
> +
> +modem-pil@4080000 {
> + ...
> +
> + resets = <&pdc_reset PDC_MODEM_SYNC_RESET>;
> + reset-names = "pdc_reset";
> +
> + ...
> +};
> diff --git a/include/dt-bindings/reset/qcom,sdm845-pdc.h b/include/dt-bindings/reset/qcom,sdm845-pdc.h
> new file mode 100644
> index 000000000000..53c37f9c319a
> --- /dev/null
> +++ b/include/dt-bindings/reset/qcom,sdm845-pdc.h
> @@ -0,0 +1,20 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2018 The Linux Foundation. All rights reserved.
> + */
> +
> +#ifndef _DT_BINDINGS_RESET_PDC_SDM_845_H
> +#define _DT_BINDINGS_RESET_PDC_SDM_845_H
> +
> +#define PDC_APPS_SYNC_RESET 0
> +#define PDC_SP_SYNC_RESET 1
> +#define PDC_AUDIO_SYNC_RESET 2
> +#define PDC_SENSORS_SYNC_RESET 3
> +#define PDC_AOP_SYNC_RESET 4
> +#define PDC_DEBUG_SYNC_RESET 5
> +#define PDC_GPU_SYNC_RESET 6
> +#define PDC_DISPLAY_SYNC_RESET 7
> +#define PDC_COMPUTE_SYNC_RESET 8
> +#define PDC_MODEM_SYNC_RESET 9
> +
> +#endif
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
^ permalink raw reply [relevance 0%]
* Re: [PATCH v2 1/6] dt-bindings: reset: Add PDC Global binding for SDM845 SoCs
2018-08-24 13:18 19% ` [PATCH v2 1/6] dt-bindings: reset: Add PDC Global binding for " Sibi Sankar
2018-08-28 0:33 0% ` Bjorn Andersson
@ 2018-08-28 0:38 0% ` Matthias Kaehlcke
2018-08-28 6:08 6% ` sibis
2018-08-29 0:43 0% ` Rob Herring
2 siblings, 1 reply; 200+ results
From: Matthias Kaehlcke @ 2018-08-28 0:38 UTC (permalink / raw)
To: Sibi Sankar
Cc: bjorn.andersson, p.zabel, robh+dt, linux-remoteproc,
linux-kernel, devicetree, ohad, mark.rutland, sricharan,
akdwived, linux-arm-msm, tsoni
Hi Sibi,
On Fri, Aug 24, 2018 at 06:48:55PM +0530, Sibi Sankar wrote:
> Add PDC Global(Power Domain Controller) binding for SDM845 SoCs.
nit: missing blank before the opening parenthesis.
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
> .../bindings/reset/qcom,pdc-global.txt | 52 +++++++++++++++++++
> include/dt-bindings/reset/qcom,sdm845-pdc.h | 20 +++++++
> 2 files changed, 72 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/reset/qcom,pdc-global.txt
> create mode 100644 include/dt-bindings/reset/qcom,sdm845-pdc.h
>
> diff --git a/Documentation/devicetree/bindings/reset/qcom,pdc-global.txt b/Documentation/devicetree/bindings/reset/qcom,pdc-global.txt
> new file mode 100644
> index 000000000000..69f9edca9503
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/reset/qcom,pdc-global.txt
> @@ -0,0 +1,52 @@
> +PDC Global
> +======================================
> +
> +This binding describes a reset-controller found on PDC-Global(Power Domain
> +Controller) block for Qualcomm Technologies Inc SDM845 SoCs.
Are there other PDC reset controllers that aren't 'global'? Otherwise
I'd suggest to use 'pdc-reset' instead of 'pdc-global', which is more
specific and in line with the name of the driver added by this series.
Or something like 'pdc-reset-global/main' if there are other
controllers?
> +Required properties:
> +- compatible:
> + Usage: required
> + Value type: <string>
> + Definition: must be:
> + "qcom,sdm845-pdc-global"
> +
> +- reg:
> + Usage: required
> + Value type: <prop-encoded-array>
> + Definition: must specify the base address and size of the register
> + space.
> +
> +- #reset-cells:
> + Usage: required
> + Value type: <uint>
> + Definition: must be 1; cell entry represents the reset index.
> +
> +Example:
> +
> +pdc_reset: reset-controller@b2e0000 {
> + compatible = "qcom,sdm845-pdc-global";
> + reg = <0xb2e0000 0x20000>;
> + #reset-cells = <1>;
> +};
> +
> +PDC reset clients
> +======================================
> +
> +Device nodes that need access to reset lines should
> +specify them as a reset phandle in their corresponding node as
> +specified in reset.txt.
> +
> +For list of all valid reset indicies see
s/indicies/indices/ (or s/indicies/lines/ ?)
Cheers
Matthias
^ permalink raw reply [relevance 0%]
* Re: [PATCH v2 3/6] dt-bindings: remoteproc: Remove additional definition tag
2018-08-24 13:18 21% ` [PATCH v2 3/6] dt-bindings: remoteproc: Remove additional definition tag Sibi Sankar
@ 2018-08-28 0:44 0% ` Matthias Kaehlcke
2018-08-29 16:38 6% ` Sibi Sankar
0 siblings, 1 reply; 200+ results
From: Matthias Kaehlcke @ 2018-08-28 0:44 UTC (permalink / raw)
To: Sibi Sankar
Cc: bjorn.andersson, p.zabel, robh+dt, linux-remoteproc,
linux-kernel, devicetree, ohad, mark.rutland, sricharan,
akdwived, linux-arm-msm, tsoni
Hi Sibi,
Subject: dt-bindings: remoteproc: Remove additional definition tag
nit: the subject is a bit generic, you probably should at least add
'qcom: ' to the 'path'.
On Fri, Aug 24, 2018 at 06:48:57PM +0530, Sibi Sankar wrote:
> Remove the additional definition tag declared for WCSS sub-system
> under reset-names.
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
> Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
> index 601dd9f389aa..c45e4c131fa2 100644
> --- a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
> +++ b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
> @@ -58,7 +58,7 @@ on the Qualcomm Hexagon core.
> Usage: required
> Value type: <stringlist>
> Definition: must be "mss_restart" for the modem sub-system
> - Definition: must be "wcss_aon_reset", "wcss_reset", "wcss_q6_reset"
> + must be "wcss_aon_reset", "wcss_reset", "wcss_q6_reset"
> for the wcss syb-system
Since you are already at it you might also want to fix the typo in
'wcss syb-system'.
Other than the nits:
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
^ permalink raw reply [relevance 0%]
* Re: [PATCH v2 1/6] dt-bindings: reset: Add PDC Global binding for SDM845 SoCs
2018-08-28 0:38 0% ` Matthias Kaehlcke
@ 2018-08-28 6:08 6% ` sibis
2018-08-28 17:11 6% ` Matthias Kaehlcke
0 siblings, 1 reply; 200+ results
From: sibis @ 2018-08-28 6:08 UTC (permalink / raw)
To: Matthias Kaehlcke
Cc: bjorn.andersson, p.zabel, robh+dt, linux-remoteproc,
linux-kernel, devicetree, ohad, mark.rutland, sricharan,
akdwived, linux-arm-msm, tsoni
Hi Matthias,
Thanks for the review
On 2018-08-28 06:08, Matthias Kaehlcke wrote:
> Hi Sibi,
>
> On Fri, Aug 24, 2018 at 06:48:55PM +0530, Sibi Sankar wrote:
>> Add PDC Global(Power Domain Controller) binding for SDM845 SoCs.
>
> nit: missing blank before the opening parenthesis.
>
Will fix it
>>
>> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
>> ---
>> .../bindings/reset/qcom,pdc-global.txt | 52
>> +++++++++++++++++++
>> include/dt-bindings/reset/qcom,sdm845-pdc.h | 20 +++++++
>> 2 files changed, 72 insertions(+)
>> create mode 100644
>> Documentation/devicetree/bindings/reset/qcom,pdc-global.txt
>> create mode 100644 include/dt-bindings/reset/qcom,sdm845-pdc.h
>>
>> diff --git
>> a/Documentation/devicetree/bindings/reset/qcom,pdc-global.txt
>> b/Documentation/devicetree/bindings/reset/qcom,pdc-global.txt
>> new file mode 100644
>> index 000000000000..69f9edca9503
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/reset/qcom,pdc-global.txt
>> @@ -0,0 +1,52 @@
>> +PDC Global
>> +======================================
>> +
>> +This binding describes a reset-controller found on PDC-Global(Power
>> Domain
>> +Controller) block for Qualcomm Technologies Inc SDM845 SoCs.
>
> Are there other PDC reset controllers that aren't 'global'? Otherwise
> I'd suggest to use 'pdc-reset' instead of 'pdc-global', which is more
> specific and in line with the name of the driver added by this series.
> Or something like 'pdc-reset-global/main' if there are other
> controllers?
>
These are the only reset lines found in the pdc-global register space.
But as
explained by Bjorn, wouldn't it be better to leave it as such since
pdc-global
best describes the hardware without being limited by the current
functionality
it is being used for?
>> +Required properties:
>> +- compatible:
>> + Usage: required
>> + Value type: <string>
>> + Definition: must be:
>> + "qcom,sdm845-pdc-global"
>> +
>> +- reg:
>> + Usage: required
>> + Value type: <prop-encoded-array>
>> + Definition: must specify the base address and size of the register
>> + space.
>> +
>> +- #reset-cells:
>> + Usage: required
>> + Value type: <uint>
>> + Definition: must be 1; cell entry represents the reset index.
>> +
>> +Example:
>> +
>> +pdc_reset: reset-controller@b2e0000 {
>> + compatible = "qcom,sdm845-pdc-global";
>> + reg = <0xb2e0000 0x20000>;
>> + #reset-cells = <1>;
>> +};
>> +
>> +PDC reset clients
>> +======================================
>> +
>> +Device nodes that need access to reset lines should
>> +specify them as a reset phandle in their corresponding node as
>> +specified in reset.txt.
>> +
>> +For list of all valid reset indicies see
>
> s/indicies/indices/ (or s/indicies/lines/ ?)
>
> Cheers
>
> Matthias
^ permalink raw reply [relevance 6%]
* Re: [PATCH v2 2/6] reset: qcom: PDC Global (Power Domain Controller) reset controller
@ 2018-08-28 7:11 6% ` Sibi Sankar
0 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2018-08-28 7:11 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Matthias Kaehlcke, p.zabel, robh+dt, linux-remoteproc,
linux-kernel, devicetree, ohad, mark.rutland, sricharan,
akdwived, linux-arm-msm, tsoni, linux-remoteproc-owner
Hi Bjorn/Matthias,
Thanks for the review, will fix them in the next-respin.
On 2018-08-28 08:32, Bjorn Andersson wrote:
> On Mon 27 Aug 17:22 PDT 2018, Matthias Kaehlcke wrote:
>> On Fri, Aug 24, 2018 at 06:48:56PM +0530, Sibi Sankar wrote:
>> > diff --git a/drivers/reset/reset-qcom-pdc.c b/drivers/reset/reset-qcom-pdc.c
> [..]
>> > +struct qcom_pdc_desc {
>> > + const struct regmap_config *config;
>> > + const struct qcom_pdc_reset_map *resets;
>> > + size_t num_resets;
>> > +};
>>
>> Not sure if this structure adds much value or just a layer of
>> indirection:
>>
>> - .config is only accessed in _probe(), sdm845_pdc_regmap_config could
>> be used directly
>> - .resets is used in _(de)assert(), sdm845_pdc_resets could be used
>> directly
>> - .num_resets is only accessed in _probe(),
>> ARRAY_SIZE(sdm845_pdc_resets) could be used instead
>>
>> It probably makes sense if it is planned to support reset controllers
>> of other SoCs with this driver.
>>
>
> I like this suggestion, once we need the configurability we can add the
> type for it. It also shows that only .resets would need to be
> referenced
> by qcom_pdc_reset_data.
>
Will change it accordingly
>> > +struct qcom_pdc_reset_data {
>> > + struct reset_controller_dev rcdev;
>> > + struct regmap *regmap;
>> > + const struct qcom_pdc_desc *desc;
>> > +};
> [..]
>> > +static int qcom_pdc_reset_probe(struct platform_device *pdev)
>> > +{
> [..]
>> > + data->regmap = devm_regmap_init_mmio(dev, base, desc->config);
>> > + if (IS_ERR(data->regmap)) {
>> > + dev_err(dev, "Unable to get pdc-global regmap");
>>
>> Add missing '\n'
>>
>> Say 'pdc-reset' instead of 'pdc-global'? (see also my other comment
>> below).
>>
>
> This regmap is created out of the single anonymous "reg", so I think
> the
> error should be reduced to "Unable to initialize regmap\n".
>
Sure will add it but aren't we trying to regmap the entire pdc-global
register space though?
> [..]
>> > +static const struct of_device_id qcom_pdc_reset_of_match[] = {
>> > + { .compatible = "qcom,sdm845-pdc-global", .data = &sdm845_pdc_desc },
>>
>> Should this be 'qcom,sdm845-pdc-reset' which is more specific than
>> 'global' and in line with the name and purpose of the driver?
>> Obviously this would require to adjust the bindings doc too.
>>
>
> No, the binding describes the hardware block named "PDC Global",
> currently implemented as a reset controller. The reason for doing this
> is so that we one day can expose additional interfaces in a backwards
> compatible fashion.
>
> Regards,
> Bjorn
--
-- Sibi Sankar --
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
^ permalink raw reply [relevance 6%]
* Re: [PATCH] remoteproc: qcom: adsp: Add SDM845 ADSP and CDSP support
@ 2018-08-28 8:43 13% ` Sibi Sankar
0 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2018-08-28 8:43 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Ohad Ben-Cohen, Rob Herring, Mark Rutland, linux-remoteproc,
devicetree, linux-kernel, linux-arm-msm, linux-kernel-owner
Tested-by: Sibi Sankar <sibis@codeaurora.org>
On 2018-08-28 12:44, Bjorn Andersson wrote:
> Add support for booting the Audio and Compute DSPs found in Qualcomm's
> SDM845 platform.
>
> As with the previous platforms the power rail handling needs to be
> updated once the appropriate support lands upstream.
>
> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> ---
> .../devicetree/bindings/remoteproc/qcom,adsp.txt | 2 ++
> drivers/remoteproc/qcom_q6v5_pas.c | 12 ++++++++++++
> 2 files changed, 14 insertions(+)
>
> diff --git
> a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.txt
> b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.txt
> index 728e4193f7a6..b7d058228185 100644
> --- a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.txt
> +++ b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.txt
> @@ -10,6 +10,8 @@ on the Qualcomm ADSP Hexagon core.
> "qcom,msm8974-adsp-pil"
> "qcom,msm8996-adsp-pil"
> "qcom,msm8996-slpi-pil"
> + "qcom,sdm845-adsp-pas"
> + "qcom,sdm845-cdsp-pas"
>
> - interrupts-extended:
> Usage: required
> diff --git a/drivers/remoteproc/qcom_q6v5_pas.c
> b/drivers/remoteproc/qcom_q6v5_pas.c
> index 2478ef3cd519..53eff2afda06 100644
> --- a/drivers/remoteproc/qcom_q6v5_pas.c
> +++ b/drivers/remoteproc/qcom_q6v5_pas.c
> @@ -342,6 +342,16 @@ static const struct adsp_data adsp_resource_init =
> {
> .ssctl_id = 0x14,
> };
>
> +static const struct adsp_data cdsp_resource_init = {
> + .crash_reason_smem = 601,
> + .firmware_name = "cdsp.mdt",
> + .pas_id = 18,
> + .has_aggre2_clk = false,
> + .ssr_name = "cdsp",
> + .sysmon_name = "cdsp",
> + .ssctl_id = 0x17,
> +};
> +
> static const struct adsp_data slpi_resource_init = {
> .crash_reason_smem = 424,
> .firmware_name = "slpi.mdt",
> @@ -355,6 +365,8 @@ static const struct adsp_data slpi_resource_init =
> {
> static const struct of_device_id adsp_of_match[] = {
> { .compatible = "qcom,msm8974-adsp-pil", .data =
> &adsp_resource_init},
> { .compatible = "qcom,msm8996-adsp-pil", .data =
> &adsp_resource_init},
> { .compatible = "qcom,msm8996-slpi-pil", .data =
> &slpi_resource_init},
> + { .compatible = "qcom,sdm845-adsp-pas", .data = &adsp_resource_init},
> + { .compatible = "qcom,sdm845-cdsp-pas", .data = &cdsp_resource_init},
> { },
> };
--
-- Sibi Sankar --
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
^ permalink raw reply [relevance 13%]
* Re: [PATCH] arm64: dts: qcom: sdm845: Add smp2p nodes
@ 2018-08-28 8:52 13% ` Sibi Sankar
0 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2018-08-28 8:52 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Andy Gross, David Brown, Rob Herring, Mark Rutland,
linux-arm-msm, linux-soc, devicetree, linux-kernel,
linux-arm-msm-owner
Reviewed-by: Sibi Sankar <sibis@codeaurora.org>
On 2018-08-28 12:42, Bjorn Andersson wrote:
> Add the SMP2P nodes for the remoteproc states for adsp, cdsp, mpss and
> slpi.
>
> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/sdm845.dtsi | 88 ++++++++++++++++++++++++++++
> 1 file changed, 88 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> index 0c9a2aa6a1b5..d977117acac4 100644
> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> @@ -230,6 +230,94 @@
> hwlocks = <&tcsr_mutex 3>;
> };
>
> + smp2p-cdsp {
> + compatible = "qcom,smp2p";
> + qcom,smem = <94>, <432>;
> +
> + interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
> +
> + mboxes = <&apss_shared 6>;
> +
> + qcom,local-pid = <0>;
> + qcom,remote-pid = <5>;
> +
> + cdsp_smp2p_out: master-kernel {
> + qcom,entry-name = "master-kernel";
> + #qcom,smem-state-cells = <1>;
> + };
> +
> + cdsp_smp2p_in: slave-kernel {
> + qcom,entry-name = "slave-kernel";
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + };
> +
> + smp2p-lpass {
> + compatible = "qcom,smp2p";
> + qcom,smem = <443>, <429>;
> +
> + interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
> +
> + mboxes = <&apss_shared 10>;
> +
> + qcom,local-pid = <0>;
> + qcom,remote-pid = <2>;
> +
> + adsp_smp2p_out: master-kernel {
> + qcom,entry-name = "master-kernel";
> + #qcom,smem-state-cells = <1>;
> + };
> +
> + adsp_smp2p_in: slave-kernel {
> + qcom,entry-name = "slave-kernel";
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + };
> +
> + smp2p-mpss {
> + compatible = "qcom,smp2p";
> + qcom,smem = <435>, <428>;
> + interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
> + mboxes = <&apss_shared 14>;
> + qcom,local-pid = <0>;
> + qcom,remote-pid = <1>;
> +
> + modem_smp2p_out: master-kernel {
> + qcom,entry-name = "master-kernel";
> + #qcom,smem-state-cells = <1>;
> + };
> +
> + modem_smp2p_in: slave-kernel {
> + qcom,entry-name = "slave-kernel";
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + };
> +
> + smp2p-slpi {
> + compatible = "qcom,smp2p";
> + qcom,smem = <481>, <430>;
> + interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
> + mboxes = <&apss_shared 26>;
> + qcom,local-pid = <0>;
> + qcom,remote-pid = <3>;
> +
> + slpi_smp2p_out: master-kernel {
> + qcom,entry-name = "master-kernel";
> + #qcom,smem-state-cells = <1>;
> + };
> +
> + slpi_smp2p_in: slave-kernel {
> + qcom,entry-name = "slave-kernel";
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + };
> +
> psci {
> compatible = "arm,psci-1.0";
> method = "smc";
--
-- Sibi Sankar --
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
^ permalink raw reply [relevance 13%]
* Re: [PATCH v2 1/6] dt-bindings: reset: Add PDC Global binding for SDM845 SoCs
2018-08-28 6:08 6% ` sibis
@ 2018-08-28 17:11 6% ` Matthias Kaehlcke
0 siblings, 0 replies; 200+ results
From: Matthias Kaehlcke @ 2018-08-28 17:11 UTC (permalink / raw)
To: sibis
Cc: bjorn.andersson, p.zabel, robh+dt, linux-remoteproc,
linux-kernel, devicetree, ohad, mark.rutland, sricharan,
akdwived, linux-arm-msm, tsoni
On Tue, Aug 28, 2018 at 11:38:26AM +0530, sibis@codeaurora.org wrote:
> Hi Matthias,
> Thanks for the review
>
> On 2018-08-28 06:08, Matthias Kaehlcke wrote:
> > Hi Sibi,
> >
> > On Fri, Aug 24, 2018 at 06:48:55PM +0530, Sibi Sankar wrote:
> > > Add PDC Global(Power Domain Controller) binding for SDM845 SoCs.
> >
> > nit: missing blank before the opening parenthesis.
> >
>
> Will fix it
>
> > >
> > > Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> > > ---
> > > .../bindings/reset/qcom,pdc-global.txt | 52
> > > +++++++++++++++++++
> > > include/dt-bindings/reset/qcom,sdm845-pdc.h | 20 +++++++
> > > 2 files changed, 72 insertions(+)
> > > create mode 100644
> > > Documentation/devicetree/bindings/reset/qcom,pdc-global.txt
> > > create mode 100644 include/dt-bindings/reset/qcom,sdm845-pdc.h
> > >
> > > diff --git
> > > a/Documentation/devicetree/bindings/reset/qcom,pdc-global.txt
> > > b/Documentation/devicetree/bindings/reset/qcom,pdc-global.txt
> > > new file mode 100644
> > > index 000000000000..69f9edca9503
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/reset/qcom,pdc-global.txt
> > > @@ -0,0 +1,52 @@
> > > +PDC Global
> > > +======================================
> > > +
> > > +This binding describes a reset-controller found on PDC-Global(Power
> > > Domain
> > > +Controller) block for Qualcomm Technologies Inc SDM845 SoCs.
> >
> > Are there other PDC reset controllers that aren't 'global'? Otherwise
> > I'd suggest to use 'pdc-reset' instead of 'pdc-global', which is more
> > specific and in line with the name of the driver added by this series.
> > Or something like 'pdc-reset-global/main' if there are other
> > controllers?
> >
>
> These are the only reset lines found in the pdc-global register space. But
> as
> explained by Bjorn, wouldn't it be better to leave it as such since
> pdc-global
> best describes the hardware without being limited by the current
> functionality
> it is being used for?
If I understand Bjorn's reply on
https://patchwork.kernel.org/patch/10575335/ correctly it is planned
to use the 'pdc-global' compatible string in the future in some sort
of MFD driver for the 'PDC Global' IP block, which then instantiates
other drivers like the reset controller. In this case I agree that
'pdc-global' seems a reasonable choice.
^ permalink raw reply [relevance 6%]
* Re: [PATCH v2 1/6] dt-bindings: reset: Add PDC Global binding for SDM845 SoCs
2018-08-24 13:18 19% ` [PATCH v2 1/6] dt-bindings: reset: Add PDC Global binding for " Sibi Sankar
2018-08-28 0:33 0% ` Bjorn Andersson
2018-08-28 0:38 0% ` Matthias Kaehlcke
@ 2018-08-29 0:43 0% ` Rob Herring
2 siblings, 0 replies; 200+ results
From: Rob Herring @ 2018-08-29 0:43 UTC (permalink / raw)
To: Sibi Sankar
Cc: bjorn.andersson, p.zabel, robh+dt, linux-remoteproc,
linux-kernel, devicetree, ohad, mark.rutland, sricharan,
akdwived, linux-arm-msm, tsoni, Sibi Sankar
On Fri, 24 Aug 2018 18:48:55 +0530, Sibi Sankar wrote:
> Add PDC Global(Power Domain Controller) binding for SDM845 SoCs.
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
> .../bindings/reset/qcom,pdc-global.txt | 52 +++++++++++++++++++
> include/dt-bindings/reset/qcom,sdm845-pdc.h | 20 +++++++
> 2 files changed, 72 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/reset/qcom,pdc-global.txt
> create mode 100644 include/dt-bindings/reset/qcom,sdm845-pdc.h
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [relevance 0%]
* Re: [PATCH v2 4/6] dt-bindings: remoteproc: Add PDC reset binding for Q6V5 PIL
2018-08-24 13:18 20% ` [PATCH v2 4/6] dt-bindings: remoteproc: Add PDC reset binding for Q6V5 PIL Sibi Sankar
@ 2018-08-29 0:44 0% ` Rob Herring
0 siblings, 0 replies; 200+ results
From: Rob Herring @ 2018-08-29 0:44 UTC (permalink / raw)
To: Sibi Sankar
Cc: bjorn.andersson, p.zabel, robh+dt, linux-remoteproc,
linux-kernel, devicetree, ohad, mark.rutland, sricharan,
akdwived, linux-arm-msm, tsoni, Sibi Sankar
On Fri, 24 Aug 2018 18:48:58 +0530, Sibi Sankar wrote:
> Add additional pdc_reset binding required for Q6V5 Modem PIL on
> SDM845 SoCs.
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
> Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt | 4 ++++
> 1 file changed, 4 insertions(+)
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [relevance 0%]
* Re: [PATCH v2 3/6] dt-bindings: remoteproc: Remove additional definition tag
2018-08-28 0:44 0% ` Matthias Kaehlcke
@ 2018-08-29 16:38 6% ` Sibi Sankar
0 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2018-08-29 16:38 UTC (permalink / raw)
To: Matthias Kaehlcke
Cc: bjorn.andersson, p.zabel, robh+dt, linux-remoteproc,
linux-kernel, devicetree, ohad, mark.rutland, sricharan,
akdwived, linux-arm-msm, tsoni
Hi Matthias,
Thanks for the review!
On 2018-08-28 06:14, Matthias Kaehlcke wrote:
> Hi Sibi,
>
> Subject: dt-bindings: remoteproc: Remove additional definition tag
>
> nit: the subject is a bit generic, you probably should at least add
> 'qcom: ' to the 'path'.
>
Will add
> On Fri, Aug 24, 2018 at 06:48:57PM +0530, Sibi Sankar wrote:
>> Remove the additional definition tag declared for WCSS sub-system
>> under reset-names.
>>
>> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
>> ---
>> Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git
>> a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
>> b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
>> index 601dd9f389aa..c45e4c131fa2 100644
>> --- a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
>> +++ b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
>> @@ -58,7 +58,7 @@ on the Qualcomm Hexagon core.
>> Usage: required
>> Value type: <stringlist>
>> Definition: must be "mss_restart" for the modem sub-system
>> - Definition: must be "wcss_aon_reset", "wcss_reset", "wcss_q6_reset"
>> + must be "wcss_aon_reset", "wcss_reset", "wcss_q6_reset"
>> for the wcss syb-system
>
> Since you are already at it you might also want to fix the typo in
> 'wcss syb-system'.
>
nice catch, will correct it.
I missed your query in the other thread, APPS refers to the pdc_sync
reset line for the Application processor.
> Other than the nits:
>
> Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
--
-- Sibi Sankar --
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
^ permalink raw reply [relevance 6%]
* [PATCH v3 0/6] Add support for PDC Global on SDM845 SoCs
@ 2018-08-29 19:12 13% Sibi Sankar
2018-08-29 19:12 19% ` [PATCH v3 1/6] dt-bindings: reset: Add PDC Global binding for " Sibi Sankar
` (6 more replies)
0 siblings, 7 replies; 200+ results
From: Sibi Sankar @ 2018-08-29 19:12 UTC (permalink / raw)
To: bjorn.andersson, p.zabel, mka, robh+dt
Cc: linux-kernel, devicetree, mark.rutland, linux-arm-msm, tsoni,
Sibi Sankar
This patch series add support for PDC Global (Power Domain Controller)
on SDM845 SoCs and adds pdc reset lines assert/deassert to remoteproc
Q6v5 modem-pil. The first two patches adds PDC Global reset driver to
control reset signals of Modem, Compute, Display, GPU, Debug, AOP,
Sensors, Audio, SP and APPS. The last four patches (cleans up)/adds pdc
reset lines to q6v5 bindings and asserts/deasserts in modem start/stop
path.
V3:
refactored pdc reset driver to remove unused layer of indirection
as suggested by Matthias
Other minor fixes suggested by Matthias/Bjorn
V2:
Incorporated Philipp/Bjorn/Rob suggestions
Renamed reset binding to pdc-global.txt
replaced offset with #define of register name
replaced with devm_reset_control_get_exclusive()
Separted dt binding from the drivers
Sibi Sankar (6):
dt-bindings: reset: Add PDC Global binding for SDM845 SoCs
reset: qcom: PDC Global (Power Domain Controller) reset controller
dt-bindings: remoteproc: qcom: Remove additional definition tag
dt-bindings: remoteproc: Add PDC reset binding for Q6V5 PIL
remoteproc: qcom: q6v5-pil: Explicitly get mss_restart line
remoteproc: qcom: q6v5-pil: Add PDC reset for modem on SDM845 SoCs
.../bindings/remoteproc/qcom,q6v5.txt | 8 +-
.../bindings/reset/qcom,pdc-global.txt | 52 ++++++++
drivers/remoteproc/qcom_q6v5_pil.c | 31 ++++-
drivers/reset/Kconfig | 9 ++
drivers/reset/Makefile | 1 +
drivers/reset/reset-qcom-pdc.c | 124 ++++++++++++++++++
include/dt-bindings/reset/qcom,sdm845-pdc.h | 20 +++
7 files changed, 237 insertions(+), 8 deletions(-)
create mode 100644 Documentation/devicetree/bindings/reset/qcom,pdc-global.txt
create mode 100644 drivers/reset/reset-qcom-pdc.c
create mode 100644 include/dt-bindings/reset/qcom,sdm845-pdc.h
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [relevance 13%]
* [PATCH v3 1/6] dt-bindings: reset: Add PDC Global binding for SDM845 SoCs
2018-08-29 19:12 13% [PATCH v3 0/6] Add support for PDC Global on SDM845 SoCs Sibi Sankar
@ 2018-08-29 19:12 19% ` Sibi Sankar
2018-08-29 19:12 17% ` [PATCH v3 2/6] reset: qcom: PDC Global (Power Domain Controller) reset controller Sibi Sankar
` (5 subsequent siblings)
6 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2018-08-29 19:12 UTC (permalink / raw)
To: bjorn.andersson, p.zabel, mka, robh+dt
Cc: linux-kernel, devicetree, mark.rutland, linux-arm-msm, tsoni,
Sibi Sankar
Add PDC Global (Power Domain Controller) binding for SDM845 SoCs.
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
.../bindings/reset/qcom,pdc-global.txt | 52 +++++++++++++++++++
include/dt-bindings/reset/qcom,sdm845-pdc.h | 20 +++++++
2 files changed, 72 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/qcom,pdc-global.txt
create mode 100644 include/dt-bindings/reset/qcom,sdm845-pdc.h
diff --git a/Documentation/devicetree/bindings/reset/qcom,pdc-global.txt b/Documentation/devicetree/bindings/reset/qcom,pdc-global.txt
new file mode 100644
index 000000000000..a62a492843e7
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/qcom,pdc-global.txt
@@ -0,0 +1,52 @@
+PDC Global
+======================================
+
+This binding describes a reset-controller found on PDC-Global (Power Domain
+Controller) block for Qualcomm Technologies Inc SDM845 SoCs.
+
+Required properties:
+- compatible:
+ Usage: required
+ Value type: <string>
+ Definition: must be:
+ "qcom,sdm845-pdc-global"
+
+- reg:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: must specify the base address and size of the register
+ space.
+
+- #reset-cells:
+ Usage: required
+ Value type: <uint>
+ Definition: must be 1; cell entry represents the reset index.
+
+Example:
+
+pdc_reset: reset-controller@b2e0000 {
+ compatible = "qcom,sdm845-pdc-global";
+ reg = <0xb2e0000 0x20000>;
+ #reset-cells = <1>;
+};
+
+PDC reset clients
+======================================
+
+Device nodes that need access to reset lines should
+specify them as a reset phandle in their corresponding node as
+specified in reset.txt.
+
+For a list of all valid reset indices see
+<dt-bindings/reset/qcom,sdm845-pdc.h>
+
+Example:
+
+modem-pil@4080000 {
+ ...
+
+ resets = <&pdc_reset PDC_MODEM_SYNC_RESET>;
+ reset-names = "pdc_reset";
+
+ ...
+};
diff --git a/include/dt-bindings/reset/qcom,sdm845-pdc.h b/include/dt-bindings/reset/qcom,sdm845-pdc.h
new file mode 100644
index 000000000000..53c37f9c319a
--- /dev/null
+++ b/include/dt-bindings/reset/qcom,sdm845-pdc.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_RESET_PDC_SDM_845_H
+#define _DT_BINDINGS_RESET_PDC_SDM_845_H
+
+#define PDC_APPS_SYNC_RESET 0
+#define PDC_SP_SYNC_RESET 1
+#define PDC_AUDIO_SYNC_RESET 2
+#define PDC_SENSORS_SYNC_RESET 3
+#define PDC_AOP_SYNC_RESET 4
+#define PDC_DEBUG_SYNC_RESET 5
+#define PDC_GPU_SYNC_RESET 6
+#define PDC_DISPLAY_SYNC_RESET 7
+#define PDC_COMPUTE_SYNC_RESET 8
+#define PDC_MODEM_SYNC_RESET 9
+
+#endif
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 19%]
* [PATCH v3 2/6] reset: qcom: PDC Global (Power Domain Controller) reset controller
2018-08-29 19:12 13% [PATCH v3 0/6] Add support for PDC Global on SDM845 SoCs Sibi Sankar
2018-08-29 19:12 19% ` [PATCH v3 1/6] dt-bindings: reset: Add PDC Global binding for " Sibi Sankar
@ 2018-08-29 19:12 17% ` Sibi Sankar
2018-09-03 19:31 0% ` Bjorn Andersson
2018-08-29 19:12 21% ` [PATCH v3 3/6] dt-bindings: remoteproc: qcom: Remove additional definition tag Sibi Sankar
` (4 subsequent siblings)
6 siblings, 1 reply; 200+ results
From: Sibi Sankar @ 2018-08-29 19:12 UTC (permalink / raw)
To: bjorn.andersson, p.zabel, mka, robh+dt
Cc: linux-kernel, devicetree, mark.rutland, linux-arm-msm, tsoni,
Sibi Sankar
Add reset controller for SDM845 SoCs to control reset signals provided
by PDC Global for Modem, Compute, Display, GPU, Debug, AOP, Sensors,
Audio, SP and APPS
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
drivers/reset/Kconfig | 9 +++
drivers/reset/Makefile | 1 +
drivers/reset/reset-qcom-pdc.c | 124 +++++++++++++++++++++++++++++++++
3 files changed, 134 insertions(+)
create mode 100644 drivers/reset/reset-qcom-pdc.c
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 13d28fdbdbb5..c21da9fe51ec 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -98,6 +98,15 @@ config RESET_QCOM_AOSS
reset signals provided by AOSS for Modem, Venus, ADSP,
GPU, Camera, Wireless, Display subsystem. Otherwise, say N.
+config RESET_QCOM_PDC
+ tristate "Qualcomm PDC Reset Driver"
+ depends on ARCH_QCOM || COMPILE_TEST
+ help
+ This enables the PDC (Power Domain Controller) reset driver
+ for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want
+ to control reset signals provided by PDC for Modem, Compute,
+ Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS.
+
config RESET_SIMPLE
bool "Simple Reset Controller Driver" if COMPILE_TEST
default ARCH_SOCFPGA || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 4243c38228e2..d08e8b90046a 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_RESET_MESON_AUDIO_ARB) += reset-meson-audio-arb.o
obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o
obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o
+obj-$(CONFIG_RESET_QCOM_PDC) += reset-qcom-pdc.o
obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
obj-$(CONFIG_RESET_STM32MP157) += reset-stm32mp1.o
obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
diff --git a/drivers/reset/reset-qcom-pdc.c b/drivers/reset/reset-qcom-pdc.c
new file mode 100644
index 000000000000..ab74bccd4a5b
--- /dev/null
+++ b/drivers/reset/reset-qcom-pdc.c
@@ -0,0 +1,124 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/reset-controller.h>
+
+#include <dt-bindings/reset/qcom,sdm845-pdc.h>
+
+#define RPMH_PDC_SYNC_RESET 0x100
+
+struct qcom_pdc_reset_map {
+ u8 bit;
+};
+
+struct qcom_pdc_reset_data {
+ struct reset_controller_dev rcdev;
+ struct regmap *regmap;
+};
+
+static const struct regmap_config sdm845_pdc_regmap_config = {
+ .name = "pdc-reset",
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x20000,
+ .fast_io = true,
+};
+
+static const struct qcom_pdc_reset_map sdm845_pdc_resets[] = {
+ [PDC_APPS_SYNC_RESET] = {0},
+ [PDC_SP_SYNC_RESET] = {1},
+ [PDC_AUDIO_SYNC_RESET] = {2},
+ [PDC_SENSORS_SYNC_RESET] = {3},
+ [PDC_AOP_SYNC_RESET] = {4},
+ [PDC_DEBUG_SYNC_RESET] = {5},
+ [PDC_GPU_SYNC_RESET] = {6},
+ [PDC_DISPLAY_SYNC_RESET] = {7},
+ [PDC_COMPUTE_SYNC_RESET] = {8},
+ [PDC_MODEM_SYNC_RESET] = {9},
+};
+
+static inline struct qcom_pdc_reset_data *to_qcom_pdc_reset_data(
+ struct reset_controller_dev *rcdev)
+{
+ return container_of(rcdev, struct qcom_pdc_reset_data, rcdev);
+}
+
+static int qcom_pdc_control_assert(struct reset_controller_dev *rcdev,
+ unsigned long idx)
+{
+ struct qcom_pdc_reset_data *data = to_qcom_pdc_reset_data(rcdev);
+
+ return regmap_update_bits(data->regmap, RPMH_PDC_SYNC_RESET,
+ BIT(sdm845_pdc_resets[idx].bit),
+ BIT(sdm845_pdc_resets[idx].bit));
+}
+
+static int qcom_pdc_control_deassert(struct reset_controller_dev *rcdev,
+ unsigned long idx)
+{
+ struct qcom_pdc_reset_data *data = to_qcom_pdc_reset_data(rcdev);
+
+ return regmap_update_bits(data->regmap, RPMH_PDC_SYNC_RESET,
+ BIT(sdm845_pdc_resets[idx].bit), 0);
+}
+
+static const struct reset_control_ops qcom_pdc_reset_ops = {
+ .assert = qcom_pdc_control_assert,
+ .deassert = qcom_pdc_control_deassert,
+};
+
+static int qcom_pdc_reset_probe(struct platform_device *pdev)
+{
+ struct qcom_pdc_reset_data *data;
+ struct device *dev = &pdev->dev;
+ void __iomem *base;
+ struct resource *res;
+
+ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ data->regmap = devm_regmap_init_mmio(dev, base,
+ &sdm845_pdc_regmap_config);
+ if (IS_ERR(data->regmap)) {
+ dev_err(dev, "Unable to initialize regmap\n");
+ return PTR_ERR(data->regmap);
+ }
+
+ data->rcdev.owner = THIS_MODULE;
+ data->rcdev.ops = &qcom_pdc_reset_ops;
+ data->rcdev.nr_resets = ARRAY_SIZE(sdm845_pdc_resets);
+ data->rcdev.of_node = dev->of_node;
+
+ return devm_reset_controller_register(dev, &data->rcdev);
+}
+
+static const struct of_device_id qcom_pdc_reset_of_match[] = {
+ { .compatible = "qcom,sdm845-pdc-global" },
+ {}
+};
+MODULE_DEVICE_TABLE(of, qcom_pdc_reset_of_match);
+
+static struct platform_driver qcom_pdc_reset_driver = {
+ .probe = qcom_pdc_reset_probe,
+ .driver = {
+ .name = "qcom_pdc_reset",
+ .of_match_table = qcom_pdc_reset_of_match,
+ },
+};
+module_platform_driver(qcom_pdc_reset_driver);
+
+MODULE_DESCRIPTION("Qualcomm PDC Reset Driver");
+MODULE_LICENSE("GPL v2");
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 17%]
* [PATCH v3 3/6] dt-bindings: remoteproc: qcom: Remove additional definition tag
2018-08-29 19:12 13% [PATCH v3 0/6] Add support for PDC Global on SDM845 SoCs Sibi Sankar
2018-08-29 19:12 19% ` [PATCH v3 1/6] dt-bindings: reset: Add PDC Global binding for " Sibi Sankar
2018-08-29 19:12 17% ` [PATCH v3 2/6] reset: qcom: PDC Global (Power Domain Controller) reset controller Sibi Sankar
@ 2018-08-29 19:12 21% ` Sibi Sankar
2018-09-03 19:32 0% ` Bjorn Andersson
2018-09-10 18:28 0% ` Rob Herring
2018-08-29 19:12 20% ` [PATCH v3 4/6] dt-bindings: remoteproc: Add PDC reset binding for Q6V5 PIL Sibi Sankar
` (3 subsequent siblings)
6 siblings, 2 replies; 200+ results
From: Sibi Sankar @ 2018-08-29 19:12 UTC (permalink / raw)
To: bjorn.andersson, p.zabel, mka, robh+dt
Cc: linux-kernel, devicetree, mark.rutland, linux-arm-msm, tsoni,
Sibi Sankar
Remove the additional definition tag declared for WCSS sub-system
under reset-names.
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
index 601dd9f389aa..3a66cde5895a 100644
--- a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
+++ b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
@@ -58,8 +58,8 @@ on the Qualcomm Hexagon core.
Usage: required
Value type: <stringlist>
Definition: must be "mss_restart" for the modem sub-system
- Definition: must be "wcss_aon_reset", "wcss_reset", "wcss_q6_reset"
- for the wcss syb-system
+ must be "wcss_aon_reset", "wcss_reset", "wcss_q6_reset"
+ for the wcss sub-system
- cx-supply:
- mss-supply:
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 21%]
* [PATCH v3 4/6] dt-bindings: remoteproc: Add PDC reset binding for Q6V5 PIL
2018-08-29 19:12 13% [PATCH v3 0/6] Add support for PDC Global on SDM845 SoCs Sibi Sankar
` (2 preceding siblings ...)
2018-08-29 19:12 21% ` [PATCH v3 3/6] dt-bindings: remoteproc: qcom: Remove additional definition tag Sibi Sankar
@ 2018-08-29 19:12 20% ` Sibi Sankar
2018-08-29 19:12 21% ` [PATCH v3 5/6] remoteproc: qcom: q6v5-pil: Explicitly get mss_restart line Sibi Sankar
` (2 subsequent siblings)
6 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2018-08-29 19:12 UTC (permalink / raw)
To: bjorn.andersson, p.zabel, mka, robh+dt
Cc: linux-kernel, devicetree, mark.rutland, linux-arm-msm, tsoni,
Sibi Sankar
Add additional pdc_reset binding required for Q6V5 Modem PIL on
SDM845 SoCs.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
index 3a66cde5895a..9ff5b0309417 100644
--- a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
+++ b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
@@ -53,6 +53,8 @@ on the Qualcomm Hexagon core.
Definition: reference to the reset-controller for the modem sub-system
reference to the list of 3 reset-controllers for the
wcss sub-system
+ reference to the list of 2 reset-controllers for the modem
+ sub-system on SDM845 SoCs
- reset-names:
Usage: required
@@ -60,6 +62,8 @@ on the Qualcomm Hexagon core.
Definition: must be "mss_restart" for the modem sub-system
must be "wcss_aon_reset", "wcss_reset", "wcss_q6_reset"
for the wcss sub-system
+ must be "mss_restart", "pdc_reset" for the modem
+ sub-system on SDM845 SoCs
- cx-supply:
- mss-supply:
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 20%]
* [PATCH v3 5/6] remoteproc: qcom: q6v5-pil: Explicitly get mss_restart line
2018-08-29 19:12 13% [PATCH v3 0/6] Add support for PDC Global on SDM845 SoCs Sibi Sankar
` (3 preceding siblings ...)
2018-08-29 19:12 20% ` [PATCH v3 4/6] dt-bindings: remoteproc: Add PDC reset binding for Q6V5 PIL Sibi Sankar
@ 2018-08-29 19:12 21% ` Sibi Sankar
2018-08-29 19:12 20% ` [PATCH v3 6/6] remoteproc: qcom: q6v5-pil: Add PDC reset for modem on SDM845 SoCs Sibi Sankar
6 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2018-08-29 19:12 UTC (permalink / raw)
To: bjorn.andersson, p.zabel, mka, robh+dt
Cc: linux-kernel, devicetree, mark.rutland, linux-arm-msm, tsoni,
Sibi Sankar
Explicitly get mss_restart to facilitate adding PDC reset line
for modem on SDM845 SoCs
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
drivers/remoteproc/qcom_q6v5_pil.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
index b1296d614b8b..968413edf0c8 100644
--- a/drivers/remoteproc/qcom_q6v5_pil.c
+++ b/drivers/remoteproc/qcom_q6v5_pil.c
@@ -1177,7 +1177,7 @@ static int q6v5_init_clocks(struct device *dev, struct clk **clks,
static int q6v5_init_reset(struct q6v5 *qproc)
{
qproc->mss_restart = devm_reset_control_get_exclusive(qproc->dev,
- NULL);
+ "mss_restart");
if (IS_ERR(qproc->mss_restart)) {
dev_err(qproc->dev, "failed to acquire mss restart\n");
return PTR_ERR(qproc->mss_restart);
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 21%]
* [PATCH v3 6/6] remoteproc: qcom: q6v5-pil: Add PDC reset for modem on SDM845 SoCs
2018-08-29 19:12 13% [PATCH v3 0/6] Add support for PDC Global on SDM845 SoCs Sibi Sankar
` (4 preceding siblings ...)
2018-08-29 19:12 21% ` [PATCH v3 5/6] remoteproc: qcom: q6v5-pil: Explicitly get mss_restart line Sibi Sankar
@ 2018-08-29 19:12 20% ` Sibi Sankar
6 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2018-08-29 19:12 UTC (permalink / raw)
To: bjorn.andersson, p.zabel, mka, robh+dt
Cc: linux-kernel, devicetree, mark.rutland, linux-arm-msm, tsoni,
Sibi Sankar
In the presence of a PDC block working with subsystem RSC, assert/deassert
PDC reset in modem start/stop path.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
drivers/remoteproc/qcom_q6v5_pil.c | 29 ++++++++++++++++++++++++-----
1 file changed, 24 insertions(+), 5 deletions(-)
diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
index 968413edf0c8..835fa005fe3e 100644
--- a/drivers/remoteproc/qcom_q6v5_pil.c
+++ b/drivers/remoteproc/qcom_q6v5_pil.c
@@ -149,6 +149,7 @@ struct q6v5 {
u32 halt_nc;
struct reset_control *mss_restart;
+ struct reset_control *pdc_reset;
struct qcom_q6v5 q6v5;
@@ -349,10 +350,17 @@ static int q6v5_load(struct rproc *rproc, const struct firmware *fw)
static int q6v5_reset_assert(struct q6v5 *qproc)
{
- if (qproc->has_alt_reset)
- return reset_control_reset(qproc->mss_restart);
- else
- return reset_control_assert(qproc->mss_restart);
+ int ret;
+
+ if (qproc->has_alt_reset) {
+ reset_control_assert(qproc->pdc_reset);
+ ret = reset_control_reset(qproc->mss_restart);
+ reset_control_deassert(qproc->pdc_reset);
+ } else {
+ ret = reset_control_assert(qproc->mss_restart);
+ }
+
+ return ret;
}
static int q6v5_reset_deassert(struct q6v5 *qproc)
@@ -360,9 +368,11 @@ static int q6v5_reset_deassert(struct q6v5 *qproc)
int ret;
if (qproc->has_alt_reset) {
+ reset_control_assert(qproc->pdc_reset);
writel(1, qproc->rmb_base + RMB_MBA_ALT_RESET);
ret = reset_control_reset(qproc->mss_restart);
writel(0, qproc->rmb_base + RMB_MBA_ALT_RESET);
+ reset_control_deassert(qproc->pdc_reset);
} else {
ret = reset_control_deassert(qproc->mss_restart);
}
@@ -1183,6 +1193,15 @@ static int q6v5_init_reset(struct q6v5 *qproc)
return PTR_ERR(qproc->mss_restart);
}
+ if (qproc->has_alt_reset) {
+ qproc->pdc_reset = devm_reset_control_get_exclusive(qproc->dev,
+ "pdc_reset");
+ if (IS_ERR(qproc->pdc_reset)) {
+ dev_err(qproc->dev, "failed to acquire pdc reset\n");
+ return PTR_ERR(qproc->pdc_reset);
+ }
+ }
+
return 0;
}
@@ -1303,12 +1322,12 @@ static int q6v5_probe(struct platform_device *pdev)
}
qproc->active_reg_count = ret;
+ qproc->has_alt_reset = desc->has_alt_reset;
ret = q6v5_init_reset(qproc);
if (ret)
goto free_rproc;
qproc->version = desc->version;
- qproc->has_alt_reset = desc->has_alt_reset;
qproc->need_mem_protection = desc->need_mem_protection;
ret = qcom_q6v5_init(&qproc->q6v5, pdev, rproc, MPSS_CRASH_REASON_SMEM,
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 20%]
* [PATCH] arm64: dts: qcom: Add AOSS reset driver node for SDM845
@ 2018-09-01 22:23 8% Bjorn Andersson
2018-09-06 16:00 0% ` Doug Anderson
0 siblings, 1 reply; 200+ results
From: Bjorn Andersson @ 2018-09-01 22:23 UTC (permalink / raw)
To: Andy Gross, David Brown
Cc: Rob Herring, Mark Rutland, linux-arm-msm, linux-soc, devicetree,
linux-kernel
From: Sibi Sankar <sibis@codeaurora.org>
This patch adds the node to support AOSS reset driver on
SDM845
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
[bjorn: Updated addresses to match the binding that was merged]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 0c9a2aa6a1b5..077760792cf0 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -9,6 +9,7 @@
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+#include <dt-bindings/reset/qcom,sdm845-aoss.h>
/ {
interrupt-parent = <&intc>;
@@ -978,6 +979,12 @@
#thermal-sensor-cells = <1>;
};
+ aoss_reset: reset-controller@c2a0000 {
+ compatible = "qcom,sdm845-aoss-cc";
+ reg = <0xc2a0000 0x31000>;
+ #reset-cells = <1>;
+ };
+
spmi_bus: spmi@c440000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0xc440000 0x1100>,
--
2.18.0
^ permalink raw reply related [relevance 8%]
* Re: [PATCH v3 2/6] reset: qcom: PDC Global (Power Domain Controller) reset controller
2018-08-29 19:12 17% ` [PATCH v3 2/6] reset: qcom: PDC Global (Power Domain Controller) reset controller Sibi Sankar
@ 2018-09-03 19:31 0% ` Bjorn Andersson
0 siblings, 0 replies; 200+ results
From: Bjorn Andersson @ 2018-09-03 19:31 UTC (permalink / raw)
To: Sibi Sankar
Cc: p.zabel, mka, robh+dt, linux-kernel, devicetree, mark.rutland,
linux-arm-msm, tsoni
On Wed 29 Aug 12:12 PDT 2018, Sibi Sankar wrote:
> Add reset controller for SDM845 SoCs to control reset signals provided
> by PDC Global for Modem, Compute, Display, GPU, Debug, AOP, Sensors,
> Audio, SP and APPS
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Regards,
Bjorn
> ---
> drivers/reset/Kconfig | 9 +++
> drivers/reset/Makefile | 1 +
> drivers/reset/reset-qcom-pdc.c | 124 +++++++++++++++++++++++++++++++++
> 3 files changed, 134 insertions(+)
> create mode 100644 drivers/reset/reset-qcom-pdc.c
>
> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
> index 13d28fdbdbb5..c21da9fe51ec 100644
> --- a/drivers/reset/Kconfig
> +++ b/drivers/reset/Kconfig
> @@ -98,6 +98,15 @@ config RESET_QCOM_AOSS
> reset signals provided by AOSS for Modem, Venus, ADSP,
> GPU, Camera, Wireless, Display subsystem. Otherwise, say N.
>
> +config RESET_QCOM_PDC
> + tristate "Qualcomm PDC Reset Driver"
> + depends on ARCH_QCOM || COMPILE_TEST
> + help
> + This enables the PDC (Power Domain Controller) reset driver
> + for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want
> + to control reset signals provided by PDC for Modem, Compute,
> + Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS.
> +
> config RESET_SIMPLE
> bool "Simple Reset Controller Driver" if COMPILE_TEST
> default ARCH_SOCFPGA || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED
> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
> index 4243c38228e2..d08e8b90046a 100644
> --- a/drivers/reset/Makefile
> +++ b/drivers/reset/Makefile
> @@ -16,6 +16,7 @@ obj-$(CONFIG_RESET_MESON_AUDIO_ARB) += reset-meson-audio-arb.o
> obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
> obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o
> obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o
> +obj-$(CONFIG_RESET_QCOM_PDC) += reset-qcom-pdc.o
> obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
> obj-$(CONFIG_RESET_STM32MP157) += reset-stm32mp1.o
> obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
> diff --git a/drivers/reset/reset-qcom-pdc.c b/drivers/reset/reset-qcom-pdc.c
> new file mode 100644
> index 000000000000..ab74bccd4a5b
> --- /dev/null
> +++ b/drivers/reset/reset-qcom-pdc.c
> @@ -0,0 +1,124 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2018 The Linux Foundation. All rights reserved.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +#include <linux/reset-controller.h>
> +
> +#include <dt-bindings/reset/qcom,sdm845-pdc.h>
> +
> +#define RPMH_PDC_SYNC_RESET 0x100
> +
> +struct qcom_pdc_reset_map {
> + u8 bit;
> +};
> +
> +struct qcom_pdc_reset_data {
> + struct reset_controller_dev rcdev;
> + struct regmap *regmap;
> +};
> +
> +static const struct regmap_config sdm845_pdc_regmap_config = {
> + .name = "pdc-reset",
> + .reg_bits = 32,
> + .reg_stride = 4,
> + .val_bits = 32,
> + .max_register = 0x20000,
> + .fast_io = true,
> +};
> +
> +static const struct qcom_pdc_reset_map sdm845_pdc_resets[] = {
> + [PDC_APPS_SYNC_RESET] = {0},
> + [PDC_SP_SYNC_RESET] = {1},
> + [PDC_AUDIO_SYNC_RESET] = {2},
> + [PDC_SENSORS_SYNC_RESET] = {3},
> + [PDC_AOP_SYNC_RESET] = {4},
> + [PDC_DEBUG_SYNC_RESET] = {5},
> + [PDC_GPU_SYNC_RESET] = {6},
> + [PDC_DISPLAY_SYNC_RESET] = {7},
> + [PDC_COMPUTE_SYNC_RESET] = {8},
> + [PDC_MODEM_SYNC_RESET] = {9},
> +};
> +
> +static inline struct qcom_pdc_reset_data *to_qcom_pdc_reset_data(
> + struct reset_controller_dev *rcdev)
> +{
> + return container_of(rcdev, struct qcom_pdc_reset_data, rcdev);
> +}
> +
> +static int qcom_pdc_control_assert(struct reset_controller_dev *rcdev,
> + unsigned long idx)
> +{
> + struct qcom_pdc_reset_data *data = to_qcom_pdc_reset_data(rcdev);
> +
> + return regmap_update_bits(data->regmap, RPMH_PDC_SYNC_RESET,
> + BIT(sdm845_pdc_resets[idx].bit),
> + BIT(sdm845_pdc_resets[idx].bit));
> +}
> +
> +static int qcom_pdc_control_deassert(struct reset_controller_dev *rcdev,
> + unsigned long idx)
> +{
> + struct qcom_pdc_reset_data *data = to_qcom_pdc_reset_data(rcdev);
> +
> + return regmap_update_bits(data->regmap, RPMH_PDC_SYNC_RESET,
> + BIT(sdm845_pdc_resets[idx].bit), 0);
> +}
> +
> +static const struct reset_control_ops qcom_pdc_reset_ops = {
> + .assert = qcom_pdc_control_assert,
> + .deassert = qcom_pdc_control_deassert,
> +};
> +
> +static int qcom_pdc_reset_probe(struct platform_device *pdev)
> +{
> + struct qcom_pdc_reset_data *data;
> + struct device *dev = &pdev->dev;
> + void __iomem *base;
> + struct resource *res;
> +
> + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
> + if (!data)
> + return -ENOMEM;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + base = devm_ioremap_resource(dev, res);
> + if (IS_ERR(base))
> + return PTR_ERR(base);
> +
> + data->regmap = devm_regmap_init_mmio(dev, base,
> + &sdm845_pdc_regmap_config);
> + if (IS_ERR(data->regmap)) {
> + dev_err(dev, "Unable to initialize regmap\n");
> + return PTR_ERR(data->regmap);
> + }
> +
> + data->rcdev.owner = THIS_MODULE;
> + data->rcdev.ops = &qcom_pdc_reset_ops;
> + data->rcdev.nr_resets = ARRAY_SIZE(sdm845_pdc_resets);
> + data->rcdev.of_node = dev->of_node;
> +
> + return devm_reset_controller_register(dev, &data->rcdev);
> +}
> +
> +static const struct of_device_id qcom_pdc_reset_of_match[] = {
> + { .compatible = "qcom,sdm845-pdc-global" },
> + {}
> +};
> +MODULE_DEVICE_TABLE(of, qcom_pdc_reset_of_match);
> +
> +static struct platform_driver qcom_pdc_reset_driver = {
> + .probe = qcom_pdc_reset_probe,
> + .driver = {
> + .name = "qcom_pdc_reset",
> + .of_match_table = qcom_pdc_reset_of_match,
> + },
> +};
> +module_platform_driver(qcom_pdc_reset_driver);
> +
> +MODULE_DESCRIPTION("Qualcomm PDC Reset Driver");
> +MODULE_LICENSE("GPL v2");
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
^ permalink raw reply [relevance 0%]
* Re: [PATCH v3 3/6] dt-bindings: remoteproc: qcom: Remove additional definition tag
2018-08-29 19:12 21% ` [PATCH v3 3/6] dt-bindings: remoteproc: qcom: Remove additional definition tag Sibi Sankar
@ 2018-09-03 19:32 0% ` Bjorn Andersson
2018-09-10 18:28 0% ` Rob Herring
1 sibling, 0 replies; 200+ results
From: Bjorn Andersson @ 2018-09-03 19:32 UTC (permalink / raw)
To: Sibi Sankar
Cc: p.zabel, mka, robh+dt, linux-kernel, devicetree, mark.rutland,
linux-arm-msm, tsoni
On Wed 29 Aug 12:12 PDT 2018, Sibi Sankar wrote:
> Remove the additional definition tag declared for WCSS sub-system
> under reset-names.
>
> Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Regards,
Bjorn
> ---
> Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
> index 601dd9f389aa..3a66cde5895a 100644
> --- a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
> +++ b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
> @@ -58,8 +58,8 @@ on the Qualcomm Hexagon core.
> Usage: required
> Value type: <stringlist>
> Definition: must be "mss_restart" for the modem sub-system
> - Definition: must be "wcss_aon_reset", "wcss_reset", "wcss_q6_reset"
> - for the wcss syb-system
> + must be "wcss_aon_reset", "wcss_reset", "wcss_q6_reset"
> + for the wcss sub-system
>
> - cx-supply:
> - mss-supply:
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
^ permalink raw reply [relevance 0%]
* Re: [PATCH] arm64: dts: qcom: Add AOSS reset driver node for SDM845
2018-09-01 22:23 8% [PATCH] arm64: dts: qcom: Add AOSS reset driver node for SDM845 Bjorn Andersson
@ 2018-09-06 16:00 0% ` Doug Anderson
0 siblings, 0 replies; 200+ results
From: Doug Anderson @ 2018-09-06 16:00 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Andy Gross, David Brown, Rob Herring, Mark Rutland,
linux-arm-msm, open list:ARM/QUALCOMM SUPPORT, devicetree, LKML
Hi,
On Sat, Sep 1, 2018 at 3:23 PM, Bjorn Andersson
<bjorn.andersson@linaro.org> wrote:
> From: Sibi Sankar <sibis@codeaurora.org>
>
> This patch adds the node to support AOSS reset driver on
> SDM845
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> [bjorn: Updated addresses to match the binding that was merged]
> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/sdm845.dtsi | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> index 0c9a2aa6a1b5..077760792cf0 100644
> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> @@ -9,6 +9,7 @@
> #include <dt-bindings/clock/qcom,rpmh.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/soc/qcom,rpmh-rsc.h>
> +#include <dt-bindings/reset/qcom,sdm845-aoss.h>
nit: please sort alphabetically. "reset" comes before "soc"
...other than that this looks sane to me. Feel free to add my Reviewed-by tag.
-Doug
^ permalink raw reply [relevance 0%]
* Re: [PATCH v3 3/6] dt-bindings: remoteproc: qcom: Remove additional definition tag
2018-08-29 19:12 21% ` [PATCH v3 3/6] dt-bindings: remoteproc: qcom: Remove additional definition tag Sibi Sankar
2018-09-03 19:32 0% ` Bjorn Andersson
@ 2018-09-10 18:28 0% ` Rob Herring
1 sibling, 0 replies; 200+ results
From: Rob Herring @ 2018-09-10 18:28 UTC (permalink / raw)
To: Sibi Sankar
Cc: bjorn.andersson, p.zabel, mka, robh+dt, linux-kernel, devicetree,
mark.rutland, linux-arm-msm, tsoni, Sibi Sankar
On Thu, 30 Aug 2018 00:42:12 +0530, Sibi Sankar wrote:
> Remove the additional definition tag declared for WCSS sub-system
> under reset-names.
>
> Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
> Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [relevance 0%]
* Re: [PATCH v3 1/2] PM / devfreq: Generic CPU frequency to device frequency mapping governor
@ 2018-09-10 18:45 6% ` Sibi Sankar
0 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2018-09-10 18:45 UTC (permalink / raw)
To: skannan
Cc: myungjoo.ham, Kyungmin Park, Chanwoo Choi, Rob Herring,
Mark Rutland, georgi.djakov, vincent.guittot, daidavid1,
bjorn.andersson, linux-pm, devicetree, linux-kernel,
linux-kernel-owner, viresh.kumar
Hi Saravana,
On 2018-08-07 11:19, skannan@codeaurora.org wrote:
> On 2018-08-02 14:00, skannan@codeaurora.org wrote:
>> On 2018-08-02 02:56, MyungJoo Ham wrote:
>>>> Many CPU architectures have caches that can scale independent of the
>>>> CPUs.
>>>> Frequency scaling of the caches is necessary to make sure the cache
>>>> is not
>>>> a performance bottleneck that leads to poor performance and power.
>>>> The same
>>>> idea applies for RAM/DDR.
>>>>
>>>> To achieve this, this patch adds a generic devfreq governor that
>>>> takes the
>>>> current frequency of each CPU frequency domain and then adjusts the
>>>> frequency of the cache (or any devfreq device) based on the
>>>> frequency of
>>>> the CPUs. It listens to CPU frequency transition notifiers to keep
>>>> itself
>>>> up to date on the current CPU frequency.
>>>>
With the cpu-freq driver for SDM845 SoC supporting fast_switch and
schedutil supporting
dynamic switching wouldn't this governor be incompatible due to its
reliance on transition
notifiers? Is it planned to be used only with ondemand/performance
governors?
>>>> To decide the frequency of the device, the governor does one of the
>>>> following:
>>>
>>> This exactly has the same purpose with "passive" governor except for
>>> the
>>> single part: passive governor depends on another devfreq driver, not
>>> cpufreq driver.
>>>
>>> If both governors have many features in common, can you merge them
>>> into one?
>>> Passive governor also has "get_target_freq", which allows driver
>>> authors
>>> to define the mapping.
>>
>> Thanks for the review and pointing me to the passive governor. I agree
>> that at a high level they are both doing the same. I can certainly
>> stuff this CPU freq to dev freq mapping into passive governor, but I
>> think it'll just make one huge set of code that's harder to understand
>> and maintain because it trying to do different things under the hood.
>>
>> There are also a bunch of complexities and optimizations that come
>> with the cpufreq-map governor that don't fit with the passive
>> governor.
>>
>> 1. It's not one CPU who's frequency we have to listen to. There are
>> multiple CPUs/policies we have to aggregate across.
>> 2. We have to deal with big vs little having different needs/mappings.
>> 3. Since it's always just CPUfreq, I can optimize the handling in the
>> transition notifiers. If I have 4 different devices that are scaled
>> based on CPU freq, I still use only 1 transition notifier. It becomes
>> a bit harder to do with the passive governor.
>> 4. It requires that the device explicitly support the passive governor
>> and pick a mapping function. With cpufreq-map governor, the device
>> drivers don't need to make any changes. Whoever is making a
>> device/board can choose what devices to scale up base on CPU freq
>> based on their board and their needs. Even an end user can say, scale
>> the GPU based on my CPU based on interpolation if they choose to.
>> 5. If a device has some other use for the private data, it can't work
>> with passive governor, but can work with cpufreq-map governor.
>> 6. I also want to improve cpufreq-map governor to handle hotplug
>> correctly in later patches (needs more discussion) and that'll add
>> more complexity.
>>
>> I think for these reasons we shouldn't combine these two governors.
>> Let me know what you think.
>
> Friendly reminder.
>
> Thanks,
> Saravana
--
-- Sibi Sankar --
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
^ permalink raw reply [relevance 6%]
* Re: [PATCH v3 2/2] PM / devfreq: Add devfreq driver for interconnect bandwidth voting
@ 2018-09-10 18:55 6% ` Sibi Sankar
0 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2018-09-10 18:55 UTC (permalink / raw)
To: Georgi Djakov
Cc: Saravana Kannan, MyungJoo Ham, Kyungmin Park, Chanwoo Choi,
Rob Herring, Mark Rutland, vincent.guittot, daidavid1,
bjorn.andersson, linux-pm, devicetree, linux-kernel,
linux-kernel-owner
Hi Georgi,
This driver uses of_icc_get which is very likely to fail if it probes
before the interconnect provider. Would it be possible for icc_get to
return/differentiate both -EPROBE_DEFER and other errors to prevent the
driver to continually probe defer if the path doesn't actually exist
or just error out if it probes before the interconnect provider.
On 2018-08-23 18:30, Georgi Djakov wrote:
> Hi Saravana,
>
> On 08/02/2018 03:57 AM, Saravana Kannan wrote:
>> This driver registers itself as a devfreq device that allows devfreq
>> governors to make bandwidth votes for an interconnect path. This
>> allows
>> applying various policies for different interconnect paths using
>> devfreq
>> governors.
>>
>> Example uses:
>> * Use the devfreq performance governor to set the CPU to DDR
>> interconnect
>> path for maximum performance.
>> * Use the devfreq performance governor to set the GPU to DDR
>> interconnect
>> path for maximum performance.
>> * Use the CPU frequency to device frequency mapping governor to scale
>> the
>> DDR frequency based on the needs of the CPUs' current frequency.
>
> Usually CPUs and GPUs have dedicated cpufreq/devfreq drivers and i was
> wondering if the interconnect support could be put into these drivers
> directly?
>
>>
>> Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
>> ---
>> Documentation/devicetree/bindings/devfreq/icbw.txt | 21 ++++
>> drivers/devfreq/Kconfig | 13 +++
>> drivers/devfreq/Makefile | 1 +
>> drivers/devfreq/devfreq_icbw.c | 116
>> +++++++++++++++++++++
>> 4 files changed, 151 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/devfreq/icbw.txt
>> create mode 100644 drivers/devfreq/devfreq_icbw.c
>>
>> diff --git a/Documentation/devicetree/bindings/devfreq/icbw.txt
>> b/Documentation/devicetree/bindings/devfreq/icbw.txt
>> new file mode 100644
>> index 0000000..36cf045
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/devfreq/icbw.txt
>> @@ -0,0 +1,21 @@
>> +Interconnect bandwidth device
>> +
>> +icbw is a device that represents an interconnect path that connects
>> two
>> +devices. This device is typically used to vote for BW requirements
>> between
>> +two devices. Eg: CPU to DDR, GPU to DDR, etc
>> +
>> +Required properties:
>> +- compatible: Must be "devfreq-icbw"
>> +- interconnects: Pairs of phandles and interconnect provider
>> specifier
>> + to denote the edge source and destination ports of
>> + the interconnect path. See also:
>> + Documentation/devicetree/bindings/interconnect/interconnect.txt
>> +- interconnect-names: Must have one entry with the name "path".
>> +
>> +Example:
>> +
>> + qcom,cpubw {
>> + compatible = "devfreq-icbw";
>> + interconnects = <&snoc MASTER_APSS_1 &bimc SLAVE_EBI_CH0>;
>> + interconnect-names = "path";
>
> interconnect-names is optional when there is only a single path.
>
>> + };
>> diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
>> index 3d9ae68..590370e 100644
>> --- a/drivers/devfreq/Kconfig
>> +++ b/drivers/devfreq/Kconfig
>> @@ -121,6 +121,19 @@ config ARM_RK3399_DMC_DEVFREQ
>> It sets the frequency for the memory controller and reads
>> the usage counts
>> from hardware.
>>
>> +config DEVFREQ_ICBW
>> + bool "DEVFREQ device for making bandwidth votes on interconnect
>> paths"
>
> Can this be a module?
>
>> + select DEVFREQ_GOV_PERFORMANCE
>> + select DEVFREQ_GOV_POWERSAVE
>> + select DEVFREQ_GOV_USERSPACE
>> + default n
>
> There's no need to specify this default. It is 'n' by default anyway.
> Also maybe you want to add something like:
> depends on INTERCONNECT=y
>
> Thanks,
> Georgi
>
>> + help
>> + Different devfreq governors use this devfreq device to make
>> + bandwidth votes for interconnect paths between different devices
>> + (Eg: CPU to DDR, GPU to DDR, etc). This driver provides a generic
>> + interface so that the devfreq governors can be shared across SoCs
>> + and architectures.
>> +
>> source "drivers/devfreq/event/Kconfig"
--
-- Sibi Sankar --
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
^ permalink raw reply [relevance 6%]
* Re: [PATCH v3 2/2] PM / devfreq: Add devfreq driver for interconnect bandwidth voting
@ 2018-09-14 12:53 6% ` Sibi Sankar
1 sibling, 0 replies; 200+ results
From: Sibi Sankar @ 2018-09-14 12:53 UTC (permalink / raw)
To: Saravana Kannan
Cc: MyungJoo Ham, Kyungmin Park, Chanwoo Choi, Rob Herring,
Mark Rutland, georgi.djakov, vincent.guittot, daidavid1,
bjorn.andersson, linux-pm, devicetree, linux-kernel,
linux-kernel-owner, rnayak
Hi Saravana,
On 2018-08-02 06:27, Saravana Kannan wrote:
> This driver registers itself as a devfreq device that allows devfreq
> governors to make bandwidth votes for an interconnect path. This allows
> applying various policies for different interconnect paths using
> devfreq
> governors.
>
> Example uses:
> * Use the devfreq performance governor to set the CPU to DDR
> interconnect
> path for maximum performance.
> * Use the devfreq performance governor to set the GPU to DDR
> interconnect
> path for maximum performance.
> * Use the CPU frequency to device frequency mapping governor to scale
> the
> DDR frequency based on the needs of the CPUs' current frequency.
>
> Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
> ---
> Documentation/devicetree/bindings/devfreq/icbw.txt | 21 ++++
> drivers/devfreq/Kconfig | 13 +++
> drivers/devfreq/Makefile | 1 +
> drivers/devfreq/devfreq_icbw.c | 116
> +++++++++++++++++++++
> 4 files changed, 151 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/devfreq/icbw.txt
> create mode 100644 drivers/devfreq/devfreq_icbw.c
>
> diff --git a/Documentation/devicetree/bindings/devfreq/icbw.txt
> b/Documentation/devicetree/bindings/devfreq/icbw.txt
> new file mode 100644
> index 0000000..36cf045
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/devfreq/icbw.txt
> @@ -0,0 +1,21 @@
> +Interconnect bandwidth device
> +
> +icbw is a device that represents an interconnect path that connects
> two
> +devices. This device is typically used to vote for BW requirements
> between
> +two devices. Eg: CPU to DDR, GPU to DDR, etc
> +
> +Required properties:
> +- compatible: Must be "devfreq-icbw"
> +- interconnects: Pairs of phandles and interconnect provider specifier
> + to denote the edge source and destination ports of
> + the interconnect path. See also:
> + Documentation/devicetree/bindings/interconnect/interconnect.txt
> +- interconnect-names: Must have one entry with the name "path".
> +
> +Example:
> +
> + qcom,cpubw {
> + compatible = "devfreq-icbw";
> + interconnects = <&snoc MASTER_APSS_1 &bimc SLAVE_EBI_CH0>;
> + interconnect-names = "path";
> + };
> diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
> index 3d9ae68..590370e 100644
> --- a/drivers/devfreq/Kconfig
> +++ b/drivers/devfreq/Kconfig
> @@ -121,6 +121,19 @@ config ARM_RK3399_DMC_DEVFREQ
> It sets the frequency for the memory controller and reads
> the usage counts
> from hardware.
>
> +config DEVFREQ_ICBW
> + bool "DEVFREQ device for making bandwidth votes on interconnect
> paths"
> + select DEVFREQ_GOV_PERFORMANCE
> + select DEVFREQ_GOV_POWERSAVE
> + select DEVFREQ_GOV_USERSPACE
> + default n
> + help
> + Different devfreq governors use this devfreq device to make
> + bandwidth votes for interconnect paths between different devices
> + (Eg: CPU to DDR, GPU to DDR, etc). This driver provides a generic
> + interface so that the devfreq governors can be shared across SoCs
> + and architectures.
> +
> source "drivers/devfreq/event/Kconfig"
>
> endif # PM_DEVFREQ
> diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile
> index e9dc3e9..b302c5cf 100644
> --- a/drivers/devfreq/Makefile
> +++ b/drivers/devfreq/Makefile
> @@ -12,6 +12,7 @@ obj-$(CONFIG_DEVFREQ_GOV_CPUFREQ_MAP) +=
> governor_cpufreq_map.o
> obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ) += exynos-bus.o
> obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o
> obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra-devfreq.o
> +obj-$(CONFIG_DEVFREQ_ICBW) += devfreq_icbw.o
>
> # DEVFREQ Event Drivers
> obj-$(CONFIG_PM_DEVFREQ_EVENT) += event/
> diff --git a/drivers/devfreq/devfreq_icbw.c
> b/drivers/devfreq/devfreq_icbw.c
> new file mode 100644
> index 0000000..231fb21
> --- /dev/null
> +++ b/drivers/devfreq/devfreq_icbw.c
> @@ -0,0 +1,116 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2013-2014, 2018, The Linux Foundation. All rights
> reserved.
> + */
> +
> +#define pr_fmt(fmt) "icbw: " fmt
> +
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/init.h>
> +#include <linux/err.h>
> +#include <linux/errno.h>
> +#include <linux/mutex.h>
> +#include <linux/devfreq.h>
> +#include <linux/platform_device.h>
> +#include <linux/of.h>
> +#include <linux/interconnect.h>
> +
> +struct dev_data {
> + struct icc_path *path;
> + u32 cur_ab;
> + u32 cur_pb;
> + unsigned long gov_ab;
> + struct devfreq *df;
> + struct devfreq_dev_profile dp;
> +};
> +
> +static int icbw_target(struct device *dev, unsigned long *freq, u32
> flags)
> +{
> + struct dev_data *d = dev_get_drvdata(dev);
> + int ret;
> + u32 new_pb = *freq, new_ab = d->gov_ab;
> +
> + if (d->cur_pb == new_pb && d->cur_ab == new_ab)
> + return 0;
> +
> + dev_dbg(dev, "BW KBps: AB: %u PB: %u\n", new_ab, new_pb);
> +
> + ret = icc_set(d->path, new_ab, new_pb);
> + if (ret) {
> + dev_err(dev, "bandwidth request failed (%d)\n", ret);
> + } else {
> + d->cur_pb = new_pb;
> + d->cur_ab = new_ab;
> + }
> +
> + return ret;
> +}
> +
> +static int icbw_get_dev_status(struct device *dev,
> + struct devfreq_dev_status *stat)
> +{
> + struct dev_data *d = dev_get_drvdata(dev);
> +
> + stat->private_data = &d->gov_ab;
> + return 0;
> +}
> +
> +static int devfreq_icbw_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct dev_data *d;
> + struct devfreq_dev_profile *p;
> +
> + d = devm_kzalloc(dev, sizeof(*d), GFP_KERNEL);
> + if (!d)
> + return -ENOMEM;
> + dev_set_drvdata(dev, d);
> +
> + p = &d->dp;
> + p->polling_ms = 50;
> + p->target = icbw_target;
> + p->get_dev_status = icbw_get_dev_status;
> +
> + d->path = of_icc_get(dev, "path");
> + if (IS_ERR(d->path)) {
> + dev_err(dev, "Unable to register interconnect path\n");
> + return -ENODEV;
> + }
The probe fails if the provider is not registered yet. Worked around it
using -EPROBE_DEFER
but this should probably come from of_icc_get itself.
> +
> + d->df = devfreq_add_device(dev, p, "performance", NULL);
> + if (IS_ERR(d->df)) {
> + icc_put(d->path);
> + return PTR_ERR(d->df);
> + }
devfreq_add_device will fail with -EINVAL for set_table_freq,
find_available_min_freq and
find_available_max_freq. If you end up working your way around it, I
still ended up getting
multiple errors like "Couldn't update frequency transition information"
after probing.
> +
> + return 0;
> +}
> +
> +static int devfreq_icbw_remove(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct dev_data *d = dev_get_drvdata(dev);
> +
> + devfreq_remove_device(d->df);
> + icc_put(d->path);
> + return 0;
> +}
> +
> +static const struct of_device_id icbw_match_table[] = {
> + { .compatible = "devfreq-icbw" },
> + {}
> +};
> +
> +static struct platform_driver icbw_driver = {
> + .probe = devfreq_icbw_probe,
> + .remove = devfreq_icbw_remove,
> + .driver = {
> + .name = "devfreq-icbw",
> + .of_match_table = icbw_match_table,
> + },
> +};
> +
> +module_platform_driver(icbw_driver);
> +MODULE_DESCRIPTION("Interconnect bandwidth voting driver");
> +MODULE_LICENSE("GPL v2");
--
-- Sibi Sankar --
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
^ permalink raw reply [relevance 6%]
* [PATCH AUTOSEL 4.18 74/92] remoteproc: qcom: q6v5-pil: fix modem hang on SDM845 after axis2 clk unvote
@ 2018-09-15 1:30 8% ` Sasha Levin
0 siblings, 0 replies; 200+ results
From: Sasha Levin @ 2018-09-15 1:30 UTC (permalink / raw)
To: stable, linux-kernel; +Cc: Sibi Sankar, Bjorn Andersson, Sasha Levin
From: Sibi Sankar <sibis@codeaurora.org>
[ Upstream commit 7cbb540a3a68e4d4a8bef2d9451afb1635b5d2d3 ]
GCC_MSS_AXIS2 clock is used for disabling boot IMEM (a part of
AP boot up). With Boot IMEM disable now a part TZ/ATF, AXIS2
clock is no longer required post AP boot up and expected to
remain untouched. However if the clock is turned ON after Q6
is brought out of reset and later turned off, it results in
modem hang. When Q6 attempts a power collapse the internal
handshaking to check if AXIS2 is idle never goes through since
it is turned off preventing the RSC from getting triggered,
leaving modem in a funky state. Hence removing AXIS2 clk
enable/disable from the driver.
Reported-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
---
drivers/remoteproc/qcom_q6v5_pil.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
index 2bf8e7c49f2a..e5ec59102b01 100644
--- a/drivers/remoteproc/qcom_q6v5_pil.c
+++ b/drivers/remoteproc/qcom_q6v5_pil.c
@@ -1370,7 +1370,6 @@ static const struct rproc_hexagon_res sdm845_mss = {
.hexagon_mba_image = "mba.mbn",
.proxy_clk_names = (char*[]){
"xo",
- "axis2",
"prng",
NULL
},
--
2.17.1
^ permalink raw reply related [relevance 8%]
* Re: [PATCH v3 2/2] remoteproc: qcom: Introduce Non-PAS ADSP PIL driver
@ 2018-09-21 19:41 6% ` Sibi Sankar
0 siblings, 1 reply; 200+ results
From: Sibi Sankar @ 2018-09-21 19:41 UTC (permalink / raw)
To: Rohit kumar
Cc: ohad, bjorn.andersson, robh+dt, mark.rutland, linux-remoteproc,
devicetree, linux-kernel, plai, bgoswami, srinivas.kandagatla,
linux-kernel-owner
Hi Rohit,
On 2018-09-03 17:22, Rohit kumar wrote:
> This adds Non PAS ADSP PIL driver for Qualcomm
> Technologies Inc SoCs.
> Added initial support for SDM845 with ADSP bootup and
> shutdown operation handled from Application Processor
> SubSystem(APSS).
>
> Signed-off-by: Rohit kumar <rohitkr@codeaurora.org>
> ---
....
> + select QCOM_MDT_LOADER
> + select QCOM_Q6V5_COMMON
> + select QCOM_RPROC_COMMON
> + help
> + Say y here to support the Peripherial Image Loader
replace Peripherial/Peripheral.
....
> +#include <linux/clk.h>
> +#include <linux/firmware.h>
> +#include <linux/interrupt.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +#include <linux/reset.h>
> +#include <linux/iopoll.h>
> +#include <linux/pm_domain.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/regmap.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/of_address.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/remoteproc.h>
> +#include <linux/soc/qcom/mdt_loader.h>
> +#include <linux/soc/qcom/smem.h>
> +#include <linux/soc/qcom/smem_state.h>
> +
The headers should be in alphabetical order.
....
> + struct reset_control *pdc_sync_reset;
> + struct reset_control *cc_lpass_restart;
> +
> + struct regmap *halt_map;
> + unsigned int halt_lpass;
remove the double spaces above.
....
> + if (ret || val)
> + goto reset;
> +
> + regmap_write(adsp->halt_map,
> + adsp->halt_lpass + LPASS_HALTREQ_REG, 1);
> +
> + /* Wait for halt ACK from QDSP6 */
Minor nit, please remove the double spaces in the comment above.
> + timeout = jiffies + msecs_to_jiffies(ACK_TIMEOUT);
> + for (;;) {
> + ret = regmap_read(adsp->halt_map,
> + adsp->halt_lpass + LPASS_HALTACK_REG, &val);
> + if (ret || val || time_after(jiffies, timeout))
> + break;
> +
> + udelay(1000);
According to Documentation/timers/timers-howto.txt please use
usleep_range()
when the delay range is between(10us - 20ms).
> + }
> +
> + ret = regmap_read(adsp->halt_map,
> + adsp->halt_lpass + LPASS_MASTER_IDLE_REG, &val);
....
> + /* wait after asserting subsystem restart from AOSS */
> + udelay(200);
ditto
> +
> + /* Clear the halt request for the AXIM and AHBM for Q6 */
> + regmap_write(adsp->halt_map, adsp->halt_lpass + LPASS_HALTREQ_REG,
> 0);
> +
> + /* De-assert the LPASS PDC Reset */
> + reset_control_deassert(adsp->pdc_sync_reset);
> + /* Remove the LPASS reset */
> + reset_control_deassert(adsp->cc_lpass_restart);
> + /* wait after de-asserting subsystem restart from AOSS */
> + udelay(200);
ditto
> +
> + return 0;
> +}
....
> +static int adsp_start(struct rproc *rproc)
> +{
> + struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv;
> + int ret;
> + unsigned int val;
> +
> + qcom_q6v5_prepare(&adsp->q6v5);
> +
> + ret = clk_prepare_enable(adsp->xo);
> + if (ret)
> + return ret;
please call qcom_q6v5_unprepare on clk_prepare_enable failure to
disable_irqs
> +
> + dev_pm_genpd_set_performance_state(adsp->dev, INT_MAX);
> + ret = pm_runtime_get_sync(adsp->dev);
> + if (ret)
> + goto disable_xo_clk;
> +
....
> +static int adsp_init_reset(struct qcom_adsp *adsp)
> +{
> + adsp->pdc_sync_reset = devm_reset_control_get_exclusive(adsp->dev,
> + "pdc_sync");
> + if (IS_ERR(adsp->pdc_sync_reset)) {
> + dev_err(adsp->dev, "failed to acquire pdc_sync reset\n");
> + return PTR_ERR(adsp->pdc_sync_reset);
> + }
Bjorn, should we return EPROBE_DEFER here since PDC global reset
controller can be a module?
> +
> + adsp->cc_lpass_restart = devm_reset_control_get_exclusive(adsp->dev,
> + "cc_lpass");
> + if (IS_ERR(adsp->cc_lpass_restart)) {
> + dev_err(adsp->dev, "failed to acquire cc_lpass restart\n");
> + return PTR_ERR(adsp->cc_lpass_restart);
> + }
> +
> + return 0;
....
> +static int adsp_remove(struct platform_device *pdev)
> +{
> + struct qcom_adsp *adsp = platform_get_drvdata(pdev);
> +
> + rproc_del(adsp->rproc);
> +
> + qcom_remove_glink_subdev(adsp->rproc, &adsp->glink_subdev);
> + qcom_remove_sysmon_subdev(adsp->sysmon);
> + qcom_remove_ssr_subdev(adsp->rproc, &adsp->ssr_subdev);
> + rproc_free(adsp->rproc);
> + pm_runtime_disable(adsp->dev);
> +
rmmod of the driver resulted in the following kernel panic:
having a pm_runtime_disable after rproc_free seems to be the cause of
the kernel panic.
Please call pm_runtime_disable before rproc_free.
do_raw_spin_lock+0x28/0x118
__raw_spin_lock_irq+0x30/0x3c
__pm_runtime_disable+0x28/0xf4
adsp_remove+0x4c/0x5c [qcom_adsp_pil]
platform_drv_remove+0x28/0x50
device_release_driver_internal+0x124/0x1c8
driver_detach+0x44/0x80
bus_remove_driver+0x78/0x9c
driver_unregister+0x34/0x54
platform_driver_unregister+0x1c/0x28
cleanup_module+0x14/0x6bc [qcom_adsp_pil]
SyS_delete_module+0x1c4/0x214
> + return 0;
> +}
> +
> +static const struct adsp_pil_data adsp_resource_init = {
> + .crash_reason_smem = 423,
> + .firmware_name = "adsp.mdt",
> + .ssr_name = "lpass",
> + .sysmon_name = "adsp",
> + .ssctl_id = 0x14,
> +};
....
> +module_platform_driver(adsp_pil_driver);
> +MODULE_DESCRIPTION("QTi SDM845 ADSP Peripherial Image Loader");
replace QTi/QTI and Peripherial/Peripheral.
....
Also I see the following warns on stopping the adsp remoteproc, couldn't
root cause it though:
device_del+0x84/0x29c
platform_device_del+0x2c/0x88
platform_device_unregister+0x1c/0x30
of_platform_device_destroy+0x98/0xa8
device_for_each_child+0x54/0xa4
of_platform_depopulate+0x38/0x54
q6asm_remove+0x1c/0x2c
apr_device_remove+0x38/0x70
device_release_driver_internal+0x124/0x1c8
device_release_driver+0x24/0x30
bus_remove_device+0xcc/0xe4
device_del+0x1f8/0x29c
device_unregister+0x1c/0x30
apr_remove_device+0x1c/0x2c
device_for_each_child+0x54/0xa4
apr_remove+0x28/0x34
rpmsg_dev_remove+0x48/0x70
device_release_driver_internal+0x124/0x1c8
device_release_driver+0x24/0x30
bus_remove_device+0xcc/0xe4
device_del+0x1f8/0x29c
device_unregister+0x1c/0x30
qcom_glink_remove_device+0x1c/0x2c
device_for_each_child+0x54/0xa4
qcom_glink_native_remove+0x54/0x15c
qcom_glink_smem_unregister+0x1c/0x30
glink_subdev_stop+0x1c/0x2c [qcom_common]
rproc_stop+0x40/0xc0
rproc_shutdown+0x6c/0xc0
rproc_del+0x28/0xa0
adsp_remove+0x20/0x5c [qcom_adsp_pil]
platform_drv_remove+0x28/0x50
device_release_driver_internal+0x124/0x1c8
driver_detach+0x44/0x80
bus_remove_driver+0x78/0x9c
driver_unregister+0x34/0x54
platform_driver_unregister+0x1c/0x28
cleanup_module+0x14/0x6bc [qcom_adsp_pil]
SyS_delete_module+0x1c4/0x214
--
-- Sibi Sankar --
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
^ permalink raw reply [relevance 6%]
* Re: [PATCH v3 2/2] remoteproc: qcom: Introduce Non-PAS ADSP PIL driver
@ 2018-09-24 12:02 6% ` Sibi Sankar
0 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2018-09-24 12:02 UTC (permalink / raw)
To: Rohit Kumar
Cc: ohad, bjorn.andersson, robh+dt, mark.rutland, linux-remoteproc,
devicetree, linux-kernel, plai, bgoswami, srinivas.kandagatla,
linux-kernel-owner
On 2018-09-24 12:38, Rohit Kumar wrote:
> On 9/24/2018 12:19 PM, Rohit Kumar wrote:
>> Thanks Sibi for reviewing.
>>
>>
>> On 9/22/2018 1:11 AM, Sibi Sankar wrote:
>>> Hi Rohit,
>>>
>>> On 2018-09-03 17:22, Rohit kumar wrote:
>>>> This adds Non PAS ADSP PIL driver for Qualcomm
>>>> Technologies Inc SoCs.
>>>> Added initial support for SDM845 with ADSP bootup and
>>>> shutdown operation handled from Application Processor
>>>> SubSystem(APSS).
>>>>
>>>> Signed-off-by: Rohit kumar <rohitkr@codeaurora.org>
>>>> ---
>>> ....
> ...
>>> ....
>>> Also I see the following warns on stopping the adsp remoteproc,
>>> couldn't root cause it though:
>>
>> It should be issue in Q6 drivers. I will check and update q6 drivers.
>> Thanks for reporting.
>>
>
> Checked this warning. This is a core driver issue fixed with
> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/drivers/base/core.c?h=next-20180924&id=2ec16150179888b81717d1d3ce84e634f4736af2
>
Thanks for pointing this out.
>>> device_del+0x84/0x29c
>>> platform_device_del+0x2c/0x88
>>> platform_device_unregister+0x1c/0x30
>>> of_platform_device_destroy+0x98/0xa8
>>> device_for_each_child+0x54/0xa4
>>> of_platform_depopulate+0x38/0x54
>>> q6asm_remove+0x1c/0x2c
>>> apr_device_remove+0x38/0x70
>>> device_release_driver_internal+0x124/0x1c8
>>> device_release_driver+0x24/0x30
>>> bus_remove_device+0xcc/0xe4
>>> device_del+0x1f8/0x29c
>>> device_unregister+0x1c/0x30
>>> apr_remove_device+0x1c/0x2c
>>> device_for_each_child+0x54/0xa4
>>> apr_remove+0x28/0x34
>>> rpmsg_dev_remove+0x48/0x70
>>> device_release_driver_internal+0x124/0x1c8
>>> device_release_driver+0x24/0x30
>>> bus_remove_device+0xcc/0xe4
>>> device_del+0x1f8/0x29c
>>> device_unregister+0x1c/0x30
>>> qcom_glink_remove_device+0x1c/0x2c
>>> device_for_each_child+0x54/0xa4
>>> qcom_glink_native_remove+0x54/0x15c
>>> qcom_glink_smem_unregister+0x1c/0x30
>>> glink_subdev_stop+0x1c/0x2c [qcom_common]
>>> rproc_stop+0x40/0xc0
>>> rproc_shutdown+0x6c/0xc0
>>> rproc_del+0x28/0xa0
>>> adsp_remove+0x20/0x5c [qcom_adsp_pil]
>>> platform_drv_remove+0x28/0x50
>>> device_release_driver_internal+0x124/0x1c8
>>> driver_detach+0x44/0x80
>>> bus_remove_driver+0x78/0x9c
>>> driver_unregister+0x34/0x54
>>> platform_driver_unregister+0x1c/0x28
>>> cleanup_module+0x14/0x6bc [qcom_adsp_pil]
>>> SyS_delete_module+0x1c4/0x214
>>>
>>
>> Thanks,
>> Rohit
> Thanks
--
-- Sibi Sankar --
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
^ permalink raw reply [relevance 6%]
* Re: [PATCH v3 2/2] remoteproc: qcom: Introduce Non-PAS ADSP PIL driver
@ 2018-09-24 12:04 6% ` Sibi Sankar
1 sibling, 0 replies; 200+ results
From: Sibi Sankar @ 2018-09-24 12:04 UTC (permalink / raw)
To: Rohit Kumar
Cc: ohad, bjorn.andersson, robh+dt, mark.rutland, linux-remoteproc,
devicetree, linux-kernel, plai, bgoswami, srinivas.kandagatla,
linux-kernel-owner, linux-remoteproc-owner
On 2018-09-24 12:19, Rohit Kumar wrote:
> Thanks Sibi for reviewing.
>
>
> On 9/22/2018 1:11 AM, Sibi Sankar wrote:
>> Hi Rohit,
>>
>> On 2018-09-03 17:22, Rohit kumar wrote:
>>> This adds Non PAS ADSP PIL driver for Qualcomm
>>> Technologies Inc SoCs.
>>> Added initial support for SDM845 with ADSP bootup and
>>> shutdown operation handled from Application Processor
>>> SubSystem(APSS).
>>>
>>> Signed-off-by: Rohit kumar <rohitkr@codeaurora.org>
>>> ---
>> ....
>>> + select QCOM_MDT_LOADER
>>> + select QCOM_Q6V5_COMMON
>>> + select QCOM_RPROC_COMMON
>>> + help
>>> + Say y here to support the Peripherial Image Loader
>>
>> replace Peripherial/Peripheral.
>
> sure
>> ....
>>> +#include <linux/clk.h>
>>> +#include <linux/firmware.h>
>>> +#include <linux/interrupt.h>
>>> +#include <linux/kernel.h>
>>> +#include <linux/module.h>
>>> +#include <linux/delay.h>
>>> +#include <linux/io.h>
>>> +#include <linux/reset.h>
>>> +#include <linux/iopoll.h>
>>> +#include <linux/pm_domain.h>
>>> +#include <linux/pm_runtime.h>
>>> +#include <linux/regmap.h>
>>> +#include <linux/mfd/syscon.h>
>>> +#include <linux/of_address.h>
>>> +#include <linux/of_device.h>
>>> +#include <linux/platform_device.h>
>>> +#include <linux/remoteproc.h>
>>> +#include <linux/soc/qcom/mdt_loader.h>
>>> +#include <linux/soc/qcom/smem.h>
>>> +#include <linux/soc/qcom/smem_state.h>
>>> +
>>
>> The headers should be in alphabetical order.
>>
>
> ok, will do
>> ....
>>> + struct reset_control *pdc_sync_reset;
>>> + struct reset_control *cc_lpass_restart;
>>> +
>>> + struct regmap *halt_map;
>>> + unsigned int halt_lpass;
>>
>> remove the double spaces above.
>
> ok
>> ....
>>> + if (ret || val)
>>> + goto reset;
>>> +
>>> + regmap_write(adsp->halt_map,
>>> + adsp->halt_lpass + LPASS_HALTREQ_REG, 1);
>>> +
>>> + /* Wait for halt ACK from QDSP6 */
>>
>> Minor nit, please remove the double spaces in the comment above.
>
> ok
>>
>>> + timeout = jiffies + msecs_to_jiffies(ACK_TIMEOUT);
>>> + for (;;) {
>>> + ret = regmap_read(adsp->halt_map,
>>> + adsp->halt_lpass + LPASS_HALTACK_REG, &val);
>>> + if (ret || val || time_after(jiffies, timeout))
>>> + break;
>>> +
>>> + udelay(1000);
>>
>> According to Documentation/timers/timers-howto.txt please use
>> usleep_range()
>> when the delay range is between(10us - 20ms).
>
> okay, will update in next spin.
>>
>>> + }
>>> +
>>> + ret = regmap_read(adsp->halt_map,
>>> + adsp->halt_lpass + LPASS_MASTER_IDLE_REG, &val);
>> ....
>>> + /* wait after asserting subsystem restart from AOSS */
>>> + udelay(200);
>>
>> ditto
>
> ok
>>
>>> +
>>> + /* Clear the halt request for the AXIM and AHBM for Q6 */
>>> + regmap_write(adsp->halt_map, adsp->halt_lpass +
>>> LPASS_HALTREQ_REG, 0);
>>> +
>>> + /* De-assert the LPASS PDC Reset */
>>> + reset_control_deassert(adsp->pdc_sync_reset);
>>> + /* Remove the LPASS reset */
>>> + reset_control_deassert(adsp->cc_lpass_restart);
>>> + /* wait after de-asserting subsystem restart from AOSS */
>>> + udelay(200);
>>
>> ditto
>>
>>> +
>>> + return 0;
>>> +}
>> ....
>>> +static int adsp_start(struct rproc *rproc)
>>> +{
>>> + struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv;
>>> + int ret;
>>> + unsigned int val;
>>> +
>>> + qcom_q6v5_prepare(&adsp->q6v5);
>>> +
>>> + ret = clk_prepare_enable(adsp->xo);
>>> + if (ret)
>>> + return ret;
>>
>> please call qcom_q6v5_unprepare on clk_prepare_enable failure to
>> disable_irqs
>>
>
> sure, will do that
>>> +
>>> + dev_pm_genpd_set_performance_state(adsp->dev, INT_MAX);
>>> + ret = pm_runtime_get_sync(adsp->dev);
>>> + if (ret)
>>> + goto disable_xo_clk;
>>> +
>> ....
>>> +static int adsp_init_reset(struct qcom_adsp *adsp)
>>> +{
>>> + adsp->pdc_sync_reset =
>>> devm_reset_control_get_exclusive(adsp->dev,
>>> + "pdc_sync");
>>> + if (IS_ERR(adsp->pdc_sync_reset)) {
>>> + dev_err(adsp->dev, "failed to acquire pdc_sync reset\n");
>>> + return PTR_ERR(adsp->pdc_sync_reset);
>>> + }
>>
>> Bjorn, should we return EPROBE_DEFER here since PDC global reset
>> controller can be a module?
>>
>
> devm_reset_control_get_exclusive itself returns EPROBE_DEFER until PDC
> reset driver is probed.
> return PTR_ERR(adsp->pdc_sync_reset) handles this case.
>
Thanks for pointing this out, missed this.
>>> +
>>> + adsp->cc_lpass_restart =
>>> devm_reset_control_get_exclusive(adsp->dev,
>>> + "cc_lpass");
>>> + if (IS_ERR(adsp->cc_lpass_restart)) {
>>> + dev_err(adsp->dev, "failed to acquire cc_lpass restart\n");
>>> + return PTR_ERR(adsp->cc_lpass_restart);
>>> + }
>>> +
>>> + return 0;
>> ....
>>> +static int adsp_remove(struct platform_device *pdev)
>>> +{
>>> + struct qcom_adsp *adsp = platform_get_drvdata(pdev);
>>> +
>>> + rproc_del(adsp->rproc);
>>> +
>>> + qcom_remove_glink_subdev(adsp->rproc, &adsp->glink_subdev);
>>> + qcom_remove_sysmon_subdev(adsp->sysmon);
>>> + qcom_remove_ssr_subdev(adsp->rproc, &adsp->ssr_subdev);
>>> + rproc_free(adsp->rproc);
>>> + pm_runtime_disable(adsp->dev);
>>> +
>>
>> rmmod of the driver resulted in the following kernel panic:
>> having a pm_runtime_disable after rproc_free seems to be the cause of
>> the kernel panic.
>> Please call pm_runtime_disable before rproc_free.
>>
>
> Thanks for pointing out, will update.
>> do_raw_spin_lock+0x28/0x118
>> __raw_spin_lock_irq+0x30/0x3c
>> __pm_runtime_disable+0x28/0xf4
>> adsp_remove+0x4c/0x5c [qcom_adsp_pil]
>> platform_drv_remove+0x28/0x50
>> device_release_driver_internal+0x124/0x1c8
>> driver_detach+0x44/0x80
>> bus_remove_driver+0x78/0x9c
>> driver_unregister+0x34/0x54
>> platform_driver_unregister+0x1c/0x28
>> cleanup_module+0x14/0x6bc [qcom_adsp_pil]
>> SyS_delete_module+0x1c4/0x214
>>
>>> + return 0;
>>> +}
>>> +
>>> +static const struct adsp_pil_data adsp_resource_init = {
>>> + .crash_reason_smem = 423,
>>> + .firmware_name = "adsp.mdt",
>>> + .ssr_name = "lpass",
>>> + .sysmon_name = "adsp",
>>> + .ssctl_id = 0x14,
>>> +};
>> ....
>>> +module_platform_driver(adsp_pil_driver);
>>> +MODULE_DESCRIPTION("QTi SDM845 ADSP Peripherial Image Loader");
>>
>> replace QTi/QTI and Peripherial/Peripheral.
>>
> ok
>> ....
>> Also I see the following warns on stopping the adsp remoteproc,
>> couldn't root cause it though:
>
> It should be issue in Q6 drivers. I will check and update q6 drivers.
> Thanks for reporting.
>
>> device_del+0x84/0x29c
>> platform_device_del+0x2c/0x88
>> platform_device_unregister+0x1c/0x30
>> of_platform_device_destroy+0x98/0xa8
>> device_for_each_child+0x54/0xa4
>> of_platform_depopulate+0x38/0x54
>> q6asm_remove+0x1c/0x2c
>> apr_device_remove+0x38/0x70
>> device_release_driver_internal+0x124/0x1c8
>> device_release_driver+0x24/0x30
>> bus_remove_device+0xcc/0xe4
>> device_del+0x1f8/0x29c
>> device_unregister+0x1c/0x30
>> apr_remove_device+0x1c/0x2c
>> device_for_each_child+0x54/0xa4
>> apr_remove+0x28/0x34
>> rpmsg_dev_remove+0x48/0x70
>> device_release_driver_internal+0x124/0x1c8
>> device_release_driver+0x24/0x30
>> bus_remove_device+0xcc/0xe4
>> device_del+0x1f8/0x29c
>> device_unregister+0x1c/0x30
>> qcom_glink_remove_device+0x1c/0x2c
>> device_for_each_child+0x54/0xa4
>> qcom_glink_native_remove+0x54/0x15c
>> qcom_glink_smem_unregister+0x1c/0x30
>> glink_subdev_stop+0x1c/0x2c [qcom_common]
>> rproc_stop+0x40/0xc0
>> rproc_shutdown+0x6c/0xc0
>> rproc_del+0x28/0xa0
>> adsp_remove+0x20/0x5c [qcom_adsp_pil]
>> platform_drv_remove+0x28/0x50
>> device_release_driver_internal+0x124/0x1c8
>> driver_detach+0x44/0x80
>> bus_remove_driver+0x78/0x9c
>> driver_unregister+0x34/0x54
>> platform_driver_unregister+0x1c/0x28
>> cleanup_module+0x14/0x6bc [qcom_adsp_pil]
>> SyS_delete_module+0x1c4/0x214
>>
>
> Thanks,
> Rohit
--
-- Sibi Sankar --
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
^ permalink raw reply [relevance 6%]
* Re: [PATCH v4] remoteproc: qcom: Introduce Non-PAS ADSP PIL driver
@ 2018-09-24 12:08 14% ` Sibi Sankar
0 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2018-09-24 12:08 UTC (permalink / raw)
To: Rohit kumar
Cc: ohad, bjorn.andersson, robh+dt, mark.rutland, linux-remoteproc,
devicetree, linux-kernel, plai, bgoswami, rohkumar,
linux-kernel-owner
Hi Rohit,
Thanks for the quick turnaround, the patches look fine.
Reviewed-by: Sibi Sankar <sibis@codeaurora.org>
Tested-by: Sibi Sankar <sibis@codeaurora.org>
On 2018-09-24 16:37, Rohit kumar wrote:
> This adds Non PAS ADSP PIL driver for Qualcomm
> Technologies Inc SoCs.
> Added initial support for SDM845 with ADSP bootup and
> shutdown operation handled from Application Processor
> SubSystem(APSS).
>
> Signed-off-by: Rohit kumar <rohitkr@codeaurora.org>
> ---
> Changes since v3:
> Addressed comments posted by Sibi
>
> This patch is dependent on the rpmh powerdomain driver
> https://lkml.org/lkml/2018/6/27/7
> and renaming of Hexagon v5 PAS driver
> https://patchwork.kernel.org/patch/10601119/ .
>
> drivers/remoteproc/Kconfig | 14 ++
> drivers/remoteproc/Makefile | 1 +
> drivers/remoteproc/qcom_adsp_pil.c | 502
> +++++++++++++++++++++++++++++++++++++
> 3 files changed, 517 insertions(+)
> create mode 100644 drivers/remoteproc/qcom_adsp_pil.c
>
> diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig
> index 8894935..f554669 100644
> --- a/drivers/remoteproc/Kconfig
> +++ b/drivers/remoteproc/Kconfig
> @@ -140,6 +140,20 @@ config QCOM_Q6V5_WCSS
> Say y here to support the Qualcomm Peripheral Image Loader for the
> Hexagon V5 based WCSS remote processors.
>
> +config QCOM_ADSP_PIL
> + tristate "Qualcomm Technology Inc ADSP Peripheral Image Loader"
> + depends on OF && ARCH_QCOM
> + depends on QCOM_SMEM
> + depends on RPMSG_QCOM_GLINK_SMEM || RPMSG_QCOM_GLINK_SMEM=n
> + depends on QCOM_SYSMON || QCOM_SYSMON=n
> + select MFD_SYSCON
> + select QCOM_MDT_LOADER
> + select QCOM_Q6V5_COMMON
> + select QCOM_RPROC_COMMON
> + help
> + Say y here to support the Peripheral Image Loader
> + for the Qualcomm Technology Inc. ADSP remote processors.
> +
> config QCOM_SYSMON
> tristate "Qualcomm sysmon driver"
> depends on RPMSG
> diff --git a/drivers/remoteproc/Makefile b/drivers/remoteproc/Makefile
> index 050f41a..0e1b89c 100644
> --- a/drivers/remoteproc/Makefile
> +++ b/drivers/remoteproc/Makefile
> @@ -19,6 +19,7 @@ obj-$(CONFIG_QCOM_Q6V5_COMMON) += qcom_q6v5.o
> obj-$(CONFIG_QCOM_Q6V5_MSS) += qcom_q6v5_mss.o
> obj-$(CONFIG_QCOM_Q6V5_PAS) += qcom_q6v5_pas.o
> obj-$(CONFIG_QCOM_Q6V5_WCSS) += qcom_q6v5_wcss.o
> +obj-$(CONFIG_QCOM_ADSP_PIL) += qcom_adsp_pil.o
> obj-$(CONFIG_QCOM_SYSMON) += qcom_sysmon.o
> obj-$(CONFIG_QCOM_WCNSS_PIL) += qcom_wcnss_pil.o
> qcom_wcnss_pil-y += qcom_wcnss.o
> diff --git a/drivers/remoteproc/qcom_adsp_pil.c
> b/drivers/remoteproc/qcom_adsp_pil.c
> new file mode 100644
> index 0000000..f2f5e56
> --- /dev/null
> +++ b/drivers/remoteproc/qcom_adsp_pil.c
> @@ -0,0 +1,502 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Qualcomm Technology Inc. ADSP Peripheral Image Loader for SDM845.
> + * Copyright (c) 2018, The Linux Foundation. All rights reserved.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/firmware.h>
> +#include <linux/interrupt.h>
> +#include <linux/io.h>
> +#include <linux/iopoll.h>
> +#include <linux/kernel.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/of_address.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_domain.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/regmap.h>
> +#include <linux/remoteproc.h>
> +#include <linux/reset.h>
> +#include <linux/soc/qcom/mdt_loader.h>
> +#include <linux/soc/qcom/smem.h>
> +#include <linux/soc/qcom/smem_state.h>
> +
> +#include "qcom_common.h"
> +#include "qcom_q6v5.h"
> +#include "remoteproc_internal.h"
> +
> +/* time out value */
> +#define ACK_TIMEOUT 1000
> +#define BOOT_FSM_TIMEOUT 10000
> +/* mask values */
> +#define EVB_MASK GENMASK(27, 4)
> +/*QDSP6SS register offsets*/
> +#define RST_EVB_REG 0x10
> +#define CORE_START_REG 0x400
> +#define BOOT_CMD_REG 0x404
> +#define BOOT_STATUS_REG 0x408
> +#define RET_CFG_REG 0x1C
> +/*TCSR register offsets*/
> +#define LPASS_MASTER_IDLE_REG 0x8
> +#define LPASS_HALTACK_REG 0x4
> +#define LPASS_PWR_ON_REG 0x10
> +#define LPASS_HALTREQ_REG 0x0
> +
> +/* list of clocks required by ADSP PIL */
> +static const char * const adsp_clk_id[] = {
> + "sway_cbcr", "lpass_aon", "lpass_ahbs_aon_cbcr",
> "lpass_ahbm_aon_cbcr",
> + "qdsp6ss_xo", "qdsp6ss_sleep", "qdsp6ss_core",
> +};
> +
> +struct adsp_pil_data {
> + int crash_reason_smem;
> + const char *firmware_name;
> +
> + const char *ssr_name;
> + const char *sysmon_name;
> + int ssctl_id;
> +};
> +
> +struct qcom_adsp {
> + struct device *dev;
> + struct rproc *rproc;
> +
> + struct qcom_q6v5 q6v5;
> +
> + struct clk *xo;
> +
> + int num_clks;
> + struct clk_bulk_data *clks;
> +
> + void __iomem *qdsp6ss_base;
> +
> + struct reset_control *pdc_sync_reset;
> + struct reset_control *cc_lpass_restart;
> +
> + struct regmap *halt_map;
> + unsigned int halt_lpass;
> +
> + int crash_reason_smem;
> +
> + struct completion start_done;
> + struct completion stop_done;
> +
> + phys_addr_t mem_phys;
> + phys_addr_t mem_reloc;
> + void *mem_region;
> + size_t mem_size;
> +
> + struct qcom_rproc_glink glink_subdev;
> + struct qcom_rproc_ssr ssr_subdev;
> + struct qcom_sysmon *sysmon;
> +};
> +
> +static int qcom_adsp_shutdown(struct qcom_adsp *adsp)
> +{
> + unsigned long timeout;
> + unsigned int val;
> + int ret;
> +
> + /* Reset the retention logic */
> + val = readl(adsp->qdsp6ss_base + RET_CFG_REG);
> + val |= 0x1;
> + writel(val, adsp->qdsp6ss_base + RET_CFG_REG);
> +
> + clk_bulk_disable_unprepare(adsp->num_clks, adsp->clks);
> +
> + /* QDSP6 master port needs to be explicitly halted */
> + ret = regmap_read(adsp->halt_map,
> + adsp->halt_lpass + LPASS_PWR_ON_REG, &val);
> + if (ret || !val)
> + goto reset;
> +
> + ret = regmap_read(adsp->halt_map,
> + adsp->halt_lpass + LPASS_MASTER_IDLE_REG,
> + &val);
> + if (ret || val)
> + goto reset;
> +
> + regmap_write(adsp->halt_map,
> + adsp->halt_lpass + LPASS_HALTREQ_REG, 1);
> +
> + /* Wait for halt ACK from QDSP6 */
> + timeout = jiffies + msecs_to_jiffies(ACK_TIMEOUT);
> + for (;;) {
> + ret = regmap_read(adsp->halt_map,
> + adsp->halt_lpass + LPASS_HALTACK_REG, &val);
> + if (ret || val || time_after(jiffies, timeout))
> + break;
> +
> + usleep_range(1000, 1100);
> + }
> +
> + ret = regmap_read(adsp->halt_map,
> + adsp->halt_lpass + LPASS_MASTER_IDLE_REG, &val);
> + if (ret || !val)
> + dev_err(adsp->dev, "port failed halt\n");
> +
> +reset:
> + /* Assert the LPASS PDC Reset */
> + reset_control_assert(adsp->pdc_sync_reset);
> + /* Place the LPASS processor into reset */
> + reset_control_assert(adsp->cc_lpass_restart);
> + /* wait after asserting subsystem restart from AOSS */
> + usleep_range(200, 300);
> +
> + /* Clear the halt request for the AXIM and AHBM for Q6 */
> + regmap_write(adsp->halt_map, adsp->halt_lpass + LPASS_HALTREQ_REG,
> 0);
> +
> + /* De-assert the LPASS PDC Reset */
> + reset_control_deassert(adsp->pdc_sync_reset);
> + /* Remove the LPASS reset */
> + reset_control_deassert(adsp->cc_lpass_restart);
> + /* wait after de-asserting subsystem restart from AOSS */
> + usleep_range(200, 300);
> +
> + return 0;
> +}
> +
> +static int adsp_load(struct rproc *rproc, const struct firmware *fw)
> +{
> + struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv;
> +
> + return qcom_mdt_load_no_init(adsp->dev, fw, rproc->firmware, 0,
> + adsp->mem_region, adsp->mem_phys, adsp->mem_size,
> + &adsp->mem_reloc);
> +}
> +
> +static int adsp_start(struct rproc *rproc)
> +{
> + struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv;
> + int ret;
> + unsigned int val;
> +
> + qcom_q6v5_prepare(&adsp->q6v5);
> +
> + ret = clk_prepare_enable(adsp->xo);
> + if (ret)
> + goto disable_irqs;
> +
> + dev_pm_genpd_set_performance_state(adsp->dev, INT_MAX);
> + ret = pm_runtime_get_sync(adsp->dev);
> + if (ret)
> + goto disable_xo_clk;
> +
> + ret = clk_bulk_prepare_enable(adsp->num_clks, adsp->clks);
> + if (ret) {
> + dev_err(adsp->dev, "adsp clk_enable failed\n");
> + goto disable_power_domain;
> + }
> +
> + /* Program boot address */
> + writel(adsp->mem_phys >> 4, adsp->qdsp6ss_base + RST_EVB_REG);
> +
> + /* De-assert QDSP6 stop core. QDSP6 will execute after out of reset
> */
> + writel(0x1, adsp->qdsp6ss_base + CORE_START_REG);
> +
> + /* Trigger boot FSM to start QDSP6 */
> + writel(0x1, adsp->qdsp6ss_base + BOOT_CMD_REG);
> +
> + /* Wait for core to come out of reset */
> + ret = readl_poll_timeout(adsp->qdsp6ss_base + BOOT_STATUS_REG,
> + val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT);
> + if (ret) {
> + dev_err(adsp->dev, "failed to bootup adsp\n");
> + goto disable_adsp_clks;
> + }
> +
> + ret = qcom_q6v5_wait_for_start(&adsp->q6v5, msecs_to_jiffies(5 *
> HZ));
> + if (ret == -ETIMEDOUT) {
> + dev_err(adsp->dev, "start timed out\n");
> + goto disable_adsp_clks;
> + }
> +
> + return 0;
> +
> +disable_adsp_clks:
> + clk_bulk_disable_unprepare(adsp->num_clks, adsp->clks);
> +disable_power_domain:
> + dev_pm_genpd_set_performance_state(adsp->dev, 0);
> + pm_runtime_put(adsp->dev);
> +disable_xo_clk:
> + clk_disable_unprepare(adsp->xo);
> +disable_irqs:
> + qcom_q6v5_unprepare(&adsp->q6v5);
> +
> + return ret;
> +}
> +
> +static void qcom_adsp_pil_handover(struct qcom_q6v5 *q6v5)
> +{
> + struct qcom_adsp *adsp = container_of(q6v5, struct qcom_adsp, q6v5);
> +
> + clk_disable_unprepare(adsp->xo);
> + dev_pm_genpd_set_performance_state(adsp->dev, 0);
> + pm_runtime_put(adsp->dev);
> +}
> +
> +static int adsp_stop(struct rproc *rproc)
> +{
> + struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv;
> + int handover;
> + int ret;
> +
> + ret = qcom_q6v5_request_stop(&adsp->q6v5);
> + if (ret == -ETIMEDOUT)
> + dev_err(adsp->dev, "timed out on wait\n");
> +
> + ret = qcom_adsp_shutdown(adsp);
> + if (ret)
> + dev_err(adsp->dev, "failed to shutdown: %d\n", ret);
> +
> + handover = qcom_q6v5_unprepare(&adsp->q6v5);
> + if (handover)
> + qcom_adsp_pil_handover(&adsp->q6v5);
> +
> + return ret;
> +}
> +
> +static void *adsp_da_to_va(struct rproc *rproc, u64 da, int len)
> +{
> + struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv;
> + int offset;
> +
> + offset = da - adsp->mem_reloc;
> + if (offset < 0 || offset + len > adsp->mem_size)
> + return NULL;
> +
> + return adsp->mem_region + offset;
> +}
> +
> +static const struct rproc_ops adsp_ops = {
> + .start = adsp_start,
> + .stop = adsp_stop,
> + .da_to_va = adsp_da_to_va,
> + .parse_fw = qcom_register_dump_segments,
> + .load = adsp_load,
> +};
> +
> +static int adsp_init_clock(struct qcom_adsp *adsp)
> +{
> + int i, ret;
> +
> + adsp->xo = devm_clk_get(adsp->dev, "xo");
> + if (IS_ERR(adsp->xo)) {
> + ret = PTR_ERR(adsp->xo);
> + if (ret != -EPROBE_DEFER)
> + dev_err(adsp->dev, "failed to get xo clock");
> + return ret;
> + }
> +
> + adsp->num_clks = ARRAY_SIZE(adsp_clk_id);
> + adsp->clks = devm_kcalloc(adsp->dev, adsp->num_clks,
> + sizeof(*adsp->clks), GFP_KERNEL);
> + if (IS_ERR(adsp->clks)) {
> + ret = PTR_ERR(adsp->clks);
> + if (ret != -EPROBE_DEFER)
> + dev_err(adsp->dev, "failed to get adsp clock");
> + return ret;
> + }
> +
> + for (i = 0; i < adsp->num_clks; i++)
> + adsp->clks[i].id = adsp_clk_id[i];
> +
> + return devm_clk_bulk_get(adsp->dev, adsp->num_clks, adsp->clks);
> +}
> +
> +static int adsp_init_reset(struct qcom_adsp *adsp)
> +{
> + adsp->pdc_sync_reset = devm_reset_control_get_exclusive(adsp->dev,
> + "pdc_sync");
> + if (IS_ERR(adsp->pdc_sync_reset)) {
> + dev_err(adsp->dev, "failed to acquire pdc_sync reset\n");
> + return PTR_ERR(adsp->pdc_sync_reset);
> + }
> +
> + adsp->cc_lpass_restart = devm_reset_control_get_exclusive(adsp->dev,
> + "cc_lpass");
> + if (IS_ERR(adsp->cc_lpass_restart)) {
> + dev_err(adsp->dev, "failed to acquire cc_lpass restart\n");
> + return PTR_ERR(adsp->cc_lpass_restart);
> + }
> +
> + return 0;
> +}
> +
> +static int adsp_init_mmio(struct qcom_adsp *adsp,
> + struct platform_device *pdev)
> +{
> + struct device_node *syscon;
> + struct resource *res;
> + int ret;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + adsp->qdsp6ss_base = devm_ioremap(&pdev->dev, res->start,
> + resource_size(res));
> + if (IS_ERR(adsp->qdsp6ss_base)) {
> + dev_err(adsp->dev, "failed to map QDSP6SS registers\n");
> + return PTR_ERR(adsp->qdsp6ss_base);
> + }
> +
> + syscon = of_parse_phandle(pdev->dev.of_node, "qcom,halt-regs", 0);
> + if (!syscon) {
> + dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n");
> + return -EINVAL;
> + }
> +
> + adsp->halt_map = syscon_node_to_regmap(syscon);
> + of_node_put(syscon);
> + if (IS_ERR(adsp->halt_map))
> + return PTR_ERR(adsp->halt_map);
> +
> + ret = of_property_read_u32_index(pdev->dev.of_node, "qcom,halt-regs",
> + 1, &adsp->halt_lpass);
> + if (ret < 0) {
> + dev_err(&pdev->dev, "no offset in syscon\n");
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static int adsp_alloc_memory_region(struct qcom_adsp *adsp)
> +{
> + struct device_node *node;
> + struct resource r;
> + int ret;
> +
> + node = of_parse_phandle(adsp->dev->of_node, "memory-region", 0);
> + if (!node) {
> + dev_err(adsp->dev, "no memory-region specified\n");
> + return -EINVAL;
> + }
> +
> + ret = of_address_to_resource(node, 0, &r);
> + if (ret)
> + return ret;
> +
> + adsp->mem_phys = adsp->mem_reloc = r.start;
> + adsp->mem_size = resource_size(&r);
> + adsp->mem_region = devm_ioremap_wc(adsp->dev,
> + adsp->mem_phys, adsp->mem_size);
> + if (!adsp->mem_region) {
> + dev_err(adsp->dev, "unable to map memory region: %pa+%zx\n",
> + &r.start, adsp->mem_size);
> + return -EBUSY;
> + }
> +
> + return 0;
> +}
> +
> +static int adsp_probe(struct platform_device *pdev)
> +{
> + const struct adsp_pil_data *desc;
> + struct qcom_adsp *adsp;
> + struct rproc *rproc;
> + int ret;
> +
> + desc = of_device_get_match_data(&pdev->dev);
> + if (!desc)
> + return -EINVAL;
> +
> + rproc = rproc_alloc(&pdev->dev, pdev->name, &adsp_ops,
> + desc->firmware_name, sizeof(*adsp));
> + if (!rproc) {
> + dev_err(&pdev->dev, "unable to allocate remoteproc\n");
> + return -ENOMEM;
> + }
> +
> + adsp = (struct qcom_adsp *)rproc->priv;
> + adsp->dev = &pdev->dev;
> + adsp->rproc = rproc;
> + platform_set_drvdata(pdev, adsp);
> +
> + ret = adsp_alloc_memory_region(adsp);
> + if (ret)
> + goto free_rproc;
> +
> + ret = adsp_init_clock(adsp);
> + if (ret)
> + goto free_rproc;
> +
> + pm_runtime_enable(adsp->dev);
> +
> + ret = adsp_init_reset(adsp);
> + if (ret)
> + goto disable_pm;
> +
> + ret = adsp_init_mmio(adsp, pdev);
> + if (ret)
> + goto disable_pm;
> +
> + ret = qcom_q6v5_init(&adsp->q6v5, pdev, rproc,
> desc->crash_reason_smem,
> + qcom_adsp_pil_handover);
> + if (ret)
> + goto disable_pm;
> +
> + qcom_add_glink_subdev(rproc, &adsp->glink_subdev);
> + qcom_add_ssr_subdev(rproc, &adsp->ssr_subdev, desc->ssr_name);
> + adsp->sysmon = qcom_add_sysmon_subdev(rproc,
> + desc->sysmon_name,
> + desc->ssctl_id);
> +
> + ret = rproc_add(rproc);
> + if (ret)
> + goto disable_pm;
> +
> + return 0;
> +
> +disable_pm:
> + pm_runtime_disable(adsp->dev);
> +free_rproc:
> + rproc_free(rproc);
> +
> + return ret;
> +}
> +
> +static int adsp_remove(struct platform_device *pdev)
> +{
> + struct qcom_adsp *adsp = platform_get_drvdata(pdev);
> +
> + rproc_del(adsp->rproc);
> +
> + qcom_remove_glink_subdev(adsp->rproc, &adsp->glink_subdev);
> + qcom_remove_sysmon_subdev(adsp->sysmon);
> + qcom_remove_ssr_subdev(adsp->rproc, &adsp->ssr_subdev);
> + pm_runtime_disable(adsp->dev);
> + rproc_free(adsp->rproc);
> +
> + return 0;
> +}
> +
> +static const struct adsp_pil_data adsp_resource_init = {
> + .crash_reason_smem = 423,
> + .firmware_name = "adsp.mdt",
> + .ssr_name = "lpass",
> + .sysmon_name = "adsp",
> + .ssctl_id = 0x14,
> +};
> +
> +static const struct of_device_id adsp_of_match[] = {
> + { .compatible = "qcom,sdm845-adsp-pil",
> + .data = &adsp_resource_init},
> + { },
> +};
> +MODULE_DEVICE_TABLE(of, adsp_of_match);
> +
> +static struct platform_driver adsp_pil_driver = {
> + .probe = adsp_probe,
> + .remove = adsp_remove,
> + .driver = {
> + .name = "qcom_adsp_pil",
> + .of_match_table = adsp_of_match,
> + },
> +};
> +
> +module_platform_driver(adsp_pil_driver);
> +MODULE_DESCRIPTION("QTI SDM845 ADSP Peripheral Image Loader");
> +MODULE_LICENSE("GPL v2");
--
-- Sibi Sankar --
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
^ permalink raw reply [relevance 14%]
* [PATCH 4.18 000/235] 4.18.10-stable review
@ 2018-09-24 11:49 2% Greg Kroah-Hartman
2018-09-24 11:53 8% ` [PATCH 4.18 217/235] remoteproc: qcom: q6v5-pil: fix modem hang on SDM845 after axis2 clk unvote Greg Kroah-Hartman
0 siblings, 1 reply; 200+ results
From: Greg Kroah-Hartman @ 2018-09-24 11:49 UTC (permalink / raw)
To: linux-kernel
Cc: Greg Kroah-Hartman, torvalds, akpm, linux, shuah, patches,
ben.hutchings, lkft-triage, stable
This is the start of the stable review cycle for the 4.18.10 release.
There are 235 patches in this series, all will be posted as a response
to this one. If anyone has any issues with these being applied, please
let me know.
Responses should be made by Wed Sep 26 11:30:01 UTC 2018.
Anything received after that time might be too late.
The whole patch series can be found in one patch at:
https://www.kernel.org/pub/linux/kernel/v4.x/stable-review/patch-4.18.10-rc1.gz
or in the git tree and branch at:
git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable-rc.git linux-4.18.y
and the diffstat can be found below.
thanks,
greg k-h
-------------
Pseudo-Shortlog of commits:
Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Linux 4.18.10-rc1
Brijesh Singh <brijesh.singh@amd.com>
crypto: ccp - add timeout support in the SEV command
Dan Carpenter <dan.carpenter@oracle.com>
mei: bus: type promotion bug in mei_nfc_if_version()
Mikko Perttunen <mperttunen@nvidia.com>
clk: tegra: bpmp: Don't crash when a clock fails to register
Douglas Anderson <dianders@chromium.org>
pinctrl: qcom: spmi-gpio: Fix pmic_gpio_config_get() to be compliant
Douglas Anderson <dianders@chromium.org>
pinctrl: msm: Fix msm_config_group_get() to be compliant
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
gpiolib: Respect error code of ->get_direction()
Ming Lei <ming.lei@redhat.com>
blk-mq: avoid to synchronize rcu inside blk_cleanup_queue()
Ming Lei <ming.lei@redhat.com>
blk-mq: only attempt to merge bio if there is rq in sw queue
Jann Horn <jannh@google.com>
IB/mlx5: fix uaccess beyond "count" in debugfs read/write handlers
Randy Dunlap <rdunlap@infradead.org>
block/DAC960.c: fix defined but not used build warnings
Bart Van Assche <bart.vanassche@wdc.com>
IB/nes: Fix a compiler warning
Ioana Radulescu <ruxandra.radulescu@nxp.com>
staging: fsl-dpaa2/eth: Fix DMA mapping direction
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
dmaengine: sh: rcar-dmac: avoid to write CHCR.TE to 1 if TCR is set to 0
Harry Wentland <harry.wentland@amd.com>
drm/amd/pp: Send khz clock values to DC for smu7/8
Suzuki K Poulose <suzuki.poulose@arm.com>
arm64: perf: Disable PMU while processing counter overflows
Dan Carpenter <dan.carpenter@oracle.com>
drm/panel: type promotion bug in s6e8aa0_read_mtp_id()
Hans de Goede <hdegoede@redhat.com>
ASoC: rt5651: Fix workqueue cancel vs irq free race on remove
John Stultz <john.stultz@linaro.org>
selftest: timers: Tweak raw_skew to SKIP when ADJ_OFFSET/other clock adjustments are in progress
Sibi Sankar <sibis@codeaurora.org>
remoteproc: qcom: q6v5-pil: fix modem hang on SDM845 after axis2 clk unvote
James Smart <jsmart2021@gmail.com>
scsi: lpfc: Fix panic if driver unloaded when port is offline
James Smart <jsmart2021@gmail.com>
scsi: lpfc: Fix NVME Target crash in defer rcv logic
Hannes Reinecke <hare@suse.de>
scsi: libfc: fixup 'sleeping function called from invalid context'
Timo Wischer <twischer@de.adit-jv.com>
ALSA: pcm: Fix snd_interval_refine first/last with open min/max
Li Zhijian <lizhijian@cn.fujitsu.com>
selftests/android: initialize heap_type to avoid compiling warning
Shuah Khan (Samsung OSG) <shuah@kernel.org>
selftests: vDSO - fix to return KSFT_SKIP when test couldn't be run
Zhouyang Jia <jiazhouyang09@gmail.com>
rtc: bq4802: add error handling for devm_ioremap
Wei Lu <wei.lu2@amd.com>
drm/amdkfd: Fix error codes in kfd_get_process
Shaoyun Liu <Shaoyun.Liu@amd.com>
drm/amdkfd: Fix kernel queue 64 bit doorbell offset calculation
Paul E. McKenney <paulmck@linux.vnet.ibm.com>
rcu: Fix grace-period hangs due to race with CPU offline
Peter Rosin <peda@axentia.se>
input: rohm_bu21023: switch to i2c_lock_bus(..., I2C_LOCK_SEGMENT)
Peter Rosin <peda@axentia.se>
mfd: 88pm860x-i2c: switch to i2c_lock_bus(..., I2C_LOCK_SEGMENT)
Arnd Bergmann <arnd@arndb.de>
rcutorture: Use monotonic timestamp for stall detection
Maxime Chevallier <maxime.chevallier@bootlin.com>
net: mvpp2: make sure we use single queue mode on PPv2.1
Linus Walleij <linus.walleij@linaro.org>
net: gemini: Allow multiple ports to instantiate
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
gpiolib: Mark gpio_suffixes array with __maybe_unused
Wei Yongjun <weiyongjun1@huawei.com>
gpio: pxa: Fix potential NULL dereference
Tuomas Tynkkynen <tuomas@tuxera.com>
staging: bcm2835-audio: Don't leak workqueue if open fails
Matias Bjørling <mb@lightnvm.io>
lightnvm: pblk: enable line minor version detection
Hans Holmberg <hans.holmberg@cnexlabs.com>
lightnvm: pblk: assume that chunks are closed on 1.2 devices
Dan Carpenter <dan.carpenter@oracle.com>
ASoC: qdsp6: q6afe-dai: fix a range check in of_q6afe_parse_dai_data()
Eric Yang <Eric.Yang2@amd.com>
drm/amd/display: support access ddc for mst branch
Dan Williams <dan.j.williams@intel.com>
tools/testing/nvdimm: Fix support for emulating controller temperature
Jaegeuk Kim <jaegeuk@kernel.org>
f2fs: do checkpoint in kill_sb
Suzuki K Poulose <suzuki.poulose@arm.com>
coresight: ETM: Add support for Arm Cortex-A73 and Cortex-A35
Robin Murphy <robin.murphy@arm.com>
coresight: tpiu: Fix disabling timeouts
Suzuki K Poulose <suzuki.poulose@arm.com>
coresight: Handle errors in finding input/output ports
Quentin Perret <quentin.perret@arm.com>
sched/fair: Fix util_avg of new tasks for asymmetric systems
Julia Lawall <Julia.Lawall@lip6.fr>
parport: sunbpp: fix error return code
Boris Pismenny <borisp@mellanox.com>
tls: Fix zerocopy_from_iter iov handling
Thierry Reding <treding@nvidia.com>
drm/nouveau: tegra: Detach from ARM DMA/IOMMU mapping
Karol Herbst <karolherbst@gmail.com>
drm/nouveau/debugfs: Wake up GPU before doing any reclocking
Lyude Paul <lyude@redhat.com>
drm/nouveau: Fix runtime PM leak in drm_open()
Stefan Agner <stefan@agner.ch>
mmc: sdhci: do not try to use 3.3V signaling if not supported
Stefan Agner <stefan@agner.ch>
mmc: tegra: prevent HS200 on Tegra 3
Laurentiu Tudor <laurentiu.tudor@nxp.com>
mmc: sdhci-of-esdhc: set proper dma mask for ls104x chips
Johan Hovold <johan@kernel.org>
tty: fix termios input-speed encoding
Johan Hovold <johan@kernel.org>
tty: fix termios input-speed encoding when using BOTHER
Alexander Sverdlin <alexander.sverdlin@nokia.com>
serial: 8250: of: Correct of_platform_serial_setup() error handling
Bartosz Golaszewski <brgl@bgdev.pl>
gpiolib: don't allow userspace to set values of input lines
Russell King <rmk+kernel@armlinux.org.uk>
ASoC: hdmi-codec: fix routing
Enrico Scholz <enrico.scholz@sigma-chemnitz.de>
gpu: ipu-v3: csi: pass back mbus_code_to_bus_cfg error codes
Rick Farrington <ricardo.farrington@cavium.com>
liquidio: fix hang when re-binding VF host drv after running DPDK VF driver
Nicholas Mc Guire <hofrat@osadl.org>
ARM: hisi: check of_iomap and fix missing of_node_put
Huazhong Tan <tanhuazhong@huawei.com>
net: hns3: Fix return value error in hns3_reset_notify_down_enet
Nicholas Mc Guire <hofrat@osadl.org>
ARM: hisi: fix error handling and missing of_node_put
Nicholas Mc Guire <hofrat@osadl.org>
ARM: hisi: handle of_iomap and fix missing of_node_put
Yunsheng Lin <linyunsheng@huawei.com>
net: hns3: Fix for reset_level default assignment probelm
Huazhong Tan <tanhuazhong@huawei.com>
net: hns3: Reset net device with rtnl_lock
Ard Biesheuvel <ard.biesheuvel@linaro.org>
efi/esrt: Only call efi_mem_reserve() for boot services memory
Andrea Parri <andrea.parri@amarulasolutions.com>
sched/core: Use smp_mb() in wake_woken_function()
Ryder Lee <ryder.lee@mediatek.com>
arm64: dts: mt7622: update a clock property for UART0
Tony Lindgren <tony@atomide.com>
pinctrl: pinmux: Return selector to the pinctrl driver
Tony Lindgren <tony@atomide.com>
pinctrl: rza1: Fix selector use for groups and functions
Sean Wang <sean.wang@mediatek.com>
pinctrl: mt7622: Fix probe fail by misuse the selector
Mike Christie <mchristi@redhat.com>
configfs: fix registered group removal
Paul Burton <paul.burton@mips.com>
MIPS: loongson64: cs5536: Fix PCI_OHCI_INT_REG reads
Alexey Kardashevskiy <aik@ozlabs.ru>
KVM: PPC: Book3S: Fix matching of hardware and emulated TCE tables
Arvind Yadav <arvind.yadav.cs@gmail.com>
PM / devfreq: use put_device() instead of kfree()
Eric Biggers <ebiggers@google.com>
security: check for kstrdup() failure in lsm_append()
Nicholas Mc Guire <hofrat@osadl.org>
KVM: PPC: Book3S HV: Add of_node_put() in success path
Matthew Garrett <mjg59@google.com>
evm: Don't deadlock if a crypto algorithm is unavailable
Philipp Puschmann <pp@emlix.com>
Bluetooth: Use lock_sock_nested in bt_accept_enqueue
Alexandre Belloni <alexandre.belloni@bootlin.com>
spi: dw: fix possible race condition
Roman Gushchin <guro@fb.com>
bpf: fix rcu annotations in compute_effective_progs()
Miklos Szeredi <mszeredi@redhat.com>
vfs: fix freeze protection in mnt_want_write_file() for overlayfs
Jann Horn <jannh@google.com>
mtdchar: fix overflows in adjustment of `count`
Ronny Chevalier <ronny.chevalier@hp.com>
audit: fix use-after-free in audit_add_watch
Viresh Kumar <viresh.kumar@linaro.org>
arm64: dts: uniphier: Add missing cooling device properties for CPUs
Noa Osherovich <noaos@mellanox.com>
net/mlx5: Add missing SET_DRIVER_VERSION command translation
Maciej W. Rozycki <macro@mips.com>
binfmt_elf: Respect error return from `regset->active'
Johan Hovold <johan@kernel.org>
mmc: meson-mx-sdio: fix OF child-node lookup
Johan Hovold <johan@kernel.org>
of: add helper to lookup compatible child node
Trond Myklebust <trondmy@gmail.com>
NFSv4.1 fix infinite loop on I/O.
Trond Myklebust <trondmy@gmail.com>
NFSv4: Fix a tracepoint Oops in initiate_file_draining()
Boris Ostrovsky <boris.ostrovsky@oracle.com>
x86/EISA: Don't probe EISA bus for Xen PV guests
Rob Herring <robh@kernel.org>
of: fix phandle cache creation for DTs with no phandles
Adrian Hunter <adrian.hunter@intel.com>
perf tools: Fix maps__find_symbol_by_name()
Yabin Cui <yabinc@google.com>
perf/core: Force USER_DS when recording user stack data
Max Filippov <jcmvbkbc@gmail.com>
xtensa: ISS: don't allocate memory in platform_setup
Dan Carpenter <dan.carpenter@oracle.com>
cifs: integer overflow in in SMB2_ioctl()
Dan Carpenter <dan.carpenter@oracle.com>
CIFS: fix wrapping bugs in num_entries()
Dan Carpenter <dan.carpenter@oracle.com>
cifs: prevent integer overflow in nxt_dir_entry()
Oliver Neukum <oneukum@suse.com>
Revert "cdc-acm: implement put_char() and flush_chars()"
Jia-Ju Bai <baijiaju1990@gmail.com>
usb: cdc-wdm: Fix a sleep-in-atomic-context bug in service_outstanding_interrupt()
Ben Hutchings <ben.hutchings@codethink.co.uk>
USB: yurex: Fix buffer over-read in yurex_write()
Johan Hovold <johan@kernel.org>
USB: serial: ti_usb_3410_5052: fix array underflow in completion handler
Jia-Ju Bai <baijiaju1990@gmail.com>
usb: misc: uss720: Fix two sleep-in-atomic-context bugs
Johan Hovold <johan@kernel.org>
USB: serial: io_ti: fix array underflow in completion handler
Alan Stern <stern@rowland.harvard.edu>
USB: net2280: Fix erroneous synchronization change
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
usb: gadget: udc: renesas_usb3: fix maxpacket size of ep0
Maxence Duprès <xpros64@hotmail.fr>
USB: add quirk for WORLDE Controller KS49 or Prodipe MIDI 49C USB controller
Jia-Ju Bai <baijiaju1990@gmail.com>
usb: host: u132-hcd: Fix a sleep-in-atomic-context bug in u132_get_frame()
Mathias Nyman <mathias.nyman@linux.intel.com>
usb: Avoid use-after-free by flushing endpoints early in usb_set_interface()
Oliver Neukum <oneukum@suse.com>
usb: uas: add support for more quirk flags
Tim Anderson <tsa@biglakesoftware.com>
USB: Add quirk to support DJI CineSSD
Mikulas Patocka <mpatocka@redhat.com>
dm verity: fix crash on bufio buffer that was allocated with vmalloc
Tomas Winkler <tomas.winkler@intel.com>
mei: bus: need to unlink client before freeing
Tomas Winkler <tomas.winkler@intel.com>
mei: bus: fix hw module get/put balance
Alexander Usyskin <alexander.usyskin@intel.com>
mei: ignore not found client in the enumeration
Chunfeng Yun <chunfeng.yun@mediatek.com>
usb: mtu3: fix error of xhci port id when enable U3 dual role
Chunfeng Yun <chunfeng.yun@mediatek.com>
usb: xhci: fix interrupt transfer error happened on MTK platforms
Mathias Nyman <mathias.nyman@linux.intel.com>
usb: Don't die twice if PCI xhci host is not responding in resume
Mathias Nyman <mathias.nyman@linux.intel.com>
xhci: Fix use after free for URB cancellation on a reallocated endpoint
Gustavo A. R. Silva <gustavo@embeddedor.com>
misc: hmc6352: fix potential Spectre v1
Bryant G. Ly <bryantly@linux.ibm.com>
misc: ibmvsm: Fix wrong assignment of return code
K. Y. Srinivasan <kys@microsoft.com>
Tools: hv: Fix a bug in the key delete code
Stephen Hemminger <stephen@networkplumber.org>
vmbus: don't return values for uninitalized channels
Miklos Szeredi <mszeredi@redhat.com>
ovl: fix oopses in ovl_fill_super() failure paths
Corey Minyard <cminyard@mvista.com>
ipmi: Fix I2C client removal in the SSIF driver
Corey Minyard <cminyard@mvista.com>
ipmi: Move BT capabilities detection to the detect call
Corey Minyard <cminyard@mvista.com>
ipmi: Rework SMI registration failure
Andreas Kemnade <andreas@kemnade.info>
mmc: omap_hsmmc: fix wakeirq handling on removal
Ingo Franzki <ifranzki@linux.ibm.com>
s390/crypto: Fix return code checking in cbc_paes_crypt()
Aaron Knister <aaron.s.knister@nasa.gov>
IB/ipoib: Avoid a race condition between start_xmit and cm_rep_handler
Juergen Gross <jgross@suse.com>
xen/netfront: fix waiting for xenbus state change
Bin Yang <bin.yang@intel.com>
pstore: Fix incorrect persistent ram buffer mapping
Parav Pandit <parav@mellanox.com>
RDMA/cma: Protect cma dev list with lock
Xiao Liang <xiliang@redhat.com>
xen-netfront: fix warn message as irq device name has '/'
Alexandru Gagniuc <mr.nuke.me@gmail.com>
PCI/AER: Honor "pcie_ports=native" even if HEST sets FIRMWARE_FIRST
Joerg Roedel <jroedel@suse.de>
x86/mm/pti: Add an overflow check to pti_clone_pmds()
Jiang Biao <jiang.biao2@zte.com.cn>
x86/pti: Check the return value of pti_user_pagetable_walk_pmd()
Jiang Biao <jiang.biao2@zte.com.cn>
x86/pti: Check the return value of pti_user_pagetable_walk_p4d()
Michael Müller <michael@fds-team.de>
crypto: sharah - Unregister correct algorithms for SAHARA 3
Hanna Hawa <hannah@marvell.com>
dmaengine: mv_xor_v2: kill the tasklets upon exit
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
iommu/ipmmu-vmsa: IMUCTRn.TTSEL needs a special usage on R-Car Gen3
Niklas Cassel <niklas.cassel@linaro.org>
regulator: qcom_spmi: Fix warning Bad of_node_put()
Niklas Cassel <niklas.cassel@linaro.org>
regulator: qcom_spmi: Use correct regmap when checking for error
Rex Zhu <rex.zhu@amd.com>
drm/amd/pp: Set Max clock level to display by default
Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
i2c: aspeed: Fix initial values of master and slave state
Pingfan Liu <kernelfans@gmail.com>
drivers/base: stop new probing during shutdown
Christoffer Dall <christoffer.dall@arm.com>
KVM: arm/arm64: Fix vgic init race
Randy Dunlap <rdunlap@infradead.org>
platform/x86: toshiba_acpi: Fix defined but not used build warnings
Julian Wiedmann <jwi@linux.ibm.com>
s390/qeth: reset layer2 attribute on layer switch
Julian Wiedmann <jwi@linux.ibm.com>
s390/qeth: fix race in used-buffer accounting
Bjorn Andersson <bjorn.andersson@linaro.org>
soc: qcom: smem: Correct check for global partition
Bhushan Shah <bshah@kde.org>
ARM: dts: qcom: msm8974-hammerhead: increase load on l20 for sdhci
Loic Poulain <loic.poulain@linaro.org>
arm64: dts: qcom: db410c: Fix Bluetooth LED trigger
Vitaly Kuznetsov <vkuznets@redhat.com>
xen-netfront: fix queue name setting
Jakub Kicinski <jakub.kicinski@netronome.com>
nfp: avoid buffer leak when FW communication fails
Yue Wang <yuleopen@gmail.com>
ALSA: usb-audio: Generic DSD detection for Thesycon-based implementations
Ard Biesheuvel <ard.biesheuvel@linaro.org>
efi/arm: preserve early mapping of UEFI memory map longer for BGRT
Leonard Crestez <leonard.crestez@nxp.com>
reset: imx7: Fix always writing bits as 0
Mark Rutland <mark.rutland@arm.com>
arm64: fix possible spectre-v1 write in ptrace_hbp_set_event()
YueHaibing <yuehaibing@huawei.com>
wan/fsl_ucc_hdlc: use IS_ERR_VALUE() to check return value of qe_muram_alloc
Piotr Sawicki <p.sawicki2@partner.samsung.com>
Smack: Fix handling of IPv4 traffic received by PF_INET6 sockets
Manikanta Pubbisetty <mpubbise@codeaurora.org>
mac80211: restrict delayed tailroom needed decrement
Paul Cercueil <paul@crapouillou.net>
MIPS: jz4740: Bump zload address
Oder Chiou <oder_chiou@realtek.com>
ASoC: rt5514: Fix the issue of the delay volume applied
Nicholas Mc Guire <hofrat@osadl.org>
staging: bcm2835-camera: handle wait_for_completion_timeout return properly
Nicholas Mc Guire <hofrat@osadl.org>
staging: bcm2835-camera: fix timeout handling in wait_for_completion_timeout
Sandipan Das <sandipan@linux.ibm.com>
perf script: Show correct offsets for DWARF-based unwinding
Nicholas Piggin <npiggin@gmail.com>
powerpc/powernv: opal_put_chars partial write fix
Mark Rutland <mark.rutland@arm.com>
KVM: arm/arm64: vgic: Fix possible spectre-v1 write in vgic_mmio_write_apr()
Sagi Grimberg <sagi@grimberg.me>
nvme-rdma: unquiesce queues when deleting the controller
Sagi Grimberg <sagi@grimberg.me>
nvmet: fix file discard return status
Sandipan Das <sandipan@linux.ibm.com>
perf powerpc: Fix callchain ip filtering
Krzysztof Kozlowski <krzk@kernel.org>
ARM: exynos: Clear global variable on init error path
Arnd Bergmann <arnd@arndb.de>
omapfb: rename omap2 module to omap2fb.ko
Fredrik Noring <noring@nocrew.org>
fbdev: Distinguish between interlaced and progressive modes
Daniel Mack <daniel@zonque.org>
video: fbdev: pxafb: clear allocated memory for video modes
Sandipan Das <sandipan@linux.ibm.com>
perf powerpc: Fix callchain ip filtering when return address is in a register
Randy Dunlap <rdunlap@infradead.org>
fbdev/via: fix defined but not used warning
Anton Vasilyev <vasilyev@ispras.ru>
video: goldfishfb: fix memory leak on driver remove
Jiri Olsa <jolsa@redhat.com>
perf tools: Fix struct comm_str removal crash
Dan Carpenter <dan.carpenter@oracle.com>
fbdev: omapfb: off by one in omapfb_register_client()
Sandipan Das <sandipan@linux.ibm.com>
perf tests: Fix record+probe_libc_inet_pton.sh to ensure cleanups
Sandipan Das <sandipan@linux.ibm.com>
perf tests: Fix record+probe_libc_inet_pton.sh when event exists
Sandipan Das <sandipan@linux.ibm.com>
perf tests: Fix record+probe_libc_inet_pton.sh for powerpc64
Jiri Olsa <jolsa@kernel.org>
perf tools: Synthesize GROUP_DESC feature in pipe mode
Bob Peterson <rpeterso@redhat.com>
gfs2: Don't reject a supposedly full bitmap if we have blocks reserved
Thomas Richter <tmricht@linux.ibm.com>
perf test: Fix subtest number when showing results
Todor Tomov <todor.tomov@linaro.org>
media: ov5645: Supported external clock is 24MHz
Randy Dunlap <rdunlap@infradead.org>
mtd/maps: fix solutionengine.c printk format warnings
Wei Yongjun <weiyongjun1@huawei.com>
IB/ipoib: Fix error return code in ipoib_dev_init()
Mike Snitzer <snitzer@redhat.com>
block: allow max_discard_segments to be stacked
Zhu Yanjun <yanjun.zhu@oracle.com>
IB/rxe: Drop QP0 silently
Hans Verkuil <hverkuil@xs4all.nl>
media: videobuf2-core: check for q->error in vb2_core_qbuf()
Felix Fietkau <nbd@nbd.name>
MIPS: ath79: fix system restart
John Keeping <john@metanate.com>
dmaengine: pl330: fix irq race with terminate_all
Krzysztof Ha?asa <khalasa@piap.pl>
media: tw686x: Fix oops on buffer alloc failure
Masahiro Yamada <yamada.masahiro@socionext.com>
kbuild: do not update config when running install targets
Masahiro Yamada <yamada.masahiro@socionext.com>
kbuild: add .DELETE_ON_ERROR special target
Rajan Vaja <rajan.vaja@xilinx.com>
clk: clk-fixed-factor: Clear OF_POPULATED flag in case of failure
Mikko Perttunen <mperttunen@nvidia.com>
clk: core: Potentially free connection id
Dmitry Torokhov <dmitry.torokhov@gmail.com>
Input: pxrc - fix freeing URB on device teardown
Gregory CLEMENT <gregory.clement@bootlin.com>
clk: mvebu: armada-37xx-periph: Fix wrong return value in get_parent
Nicholas Mc Guire <hofrat@osadl.org>
clk: imx6sll: fix missing of_node_put()
Nicholas Mc Guire <hofrat@osadl.org>
clk: imx6ul: fix missing of_node_put()
Andreas Gruenbacher <agruenba@redhat.com>
gfs2: Special-case rindex for gfs2_grow
Golan Ben Ami <golan.ben.ami@intel.com>
iwlwifi: cancel the injective function between hw pointers to tfd entry index
Jakub Kicinski <jakub.kicinski@netronome.com>
nfp: don't fail probe on pci_sriov_set_totalvfs() errors
YueHaibing <yuehaibing@huawei.com>
amd-xgbe: use dma_mapping_error to check map errors
YueHaibing <yuehaibing@huawei.com>
xfrm: fix 'passing zero to ERR_PTR()' warning
Takashi Iwai <tiwai@suse.de>
ALSA: usb-audio: Fix multiple definitions in AU0828_DEVICE() macro
Jeff Crukley <jcrukley@gmail.com>
ALSA: usb-audio: Add support for Encore mDSD USB DAC
Takashi Iwai <tiwai@suse.de>
ALSA: msnd: Fix the default sample sizes
Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
iommu/io-pgtable-arm: Fix pgtable allocation in selftest
Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
iommu/io-pgtable-arm-v7s: Abort allocation when table address overflows the PTE
Miao Zhong <zhongmiao@hisilicon.com>
iommu/arm-smmu-v3: sync the OVACKFLG to PRIQ consumer register
Erich E. Hoover <ehoover@sweptlaser.com>
usb: dwc3: change stream event enable bit back to 13
Tariq Toukan <tariqt@mellanox.com>
net/mlx5: Use u16 for Work Queue buffer fragment size
Roi Dayan <roid@mellanox.com>
net/mlx5: Fix possible deadlock from lockdep when adding fte to fg
Roi Dayan <roid@mellanox.com>
net/mlx5: Fix not releasing read lock when adding flow rules
Vincent Whitchurch <vincent.whitchurch@axis.com>
tcp: really ignore MSG_ZEROCOPY if no SO_ZEROCOPY
Haishuang Yan <yanhaishuang@cmss.chinamobile.com>
erspan: return PACKET_REJECT when the appropriate tunnel is not found
Haishuang Yan <yanhaishuang@cmss.chinamobile.com>
erspan: fix error handling for erspan tunnel
Jack Morgenstein <jackm@dev.mellanox.co.il>
net/mlx5: Fix debugfs cleanup in the device init/remove flow
Huy Nguyen <huyn@mellanox.com>
net/mlx5: Check for error in mlx5_attach_interface
Vakul Garg <vakul.garg@nxp.com>
net/tls: Set count of SG entries if sk_alloc_sg returns -ENOSPC
Raed Salem <raeds@mellanox.com>
net/mlx5: E-Switch, Fix memory leak when creating switchdev mode FDB tables
Cong Wang <xiyou.wangcong@gmail.com>
tipc: orphan sock in tipc_release()
Cong Wang <xiyou.wangcong@gmail.com>
rds: fix two RCU related problems
Stefan Wahren <stefan.wahren@i2se.com>
net: qca_spi: Fix race condition in spi transfers
Jack Morgenstein <jackm@dev.mellanox.co.il>
net/mlx5: Fix use-after-free in self-healing flow
Petr Oros <poros@redhat.com>
be2net: Fix memory leak in be_cmd_get_profile_config()
-------------
Diffstat:
Makefile | 31 ++++--
.../dts/qcom-msm8974-lge-nexus5-hammerhead.dts | 2 +
arch/arm/mach-exynos/suspend.c | 1 +
arch/arm/mach-hisi/hotplug.c | 41 +++++---
arch/arm64/boot/dts/mediatek/mt7622.dtsi | 2 +-
arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi | 2 +-
arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 2 +
arch/arm64/kernel/perf_event.c | 50 +++++-----
arch/arm64/kernel/ptrace.c | 19 ++--
arch/mips/ath79/setup.c | 1 +
arch/mips/include/asm/mach-ath79/ath79.h | 1 +
arch/mips/jz4740/Platform | 2 +-
arch/mips/loongson64/common/cs5536/cs5536_ohci.c | 2 +-
arch/powerpc/kvm/book3s_64_vio.c | 5 +-
arch/powerpc/kvm/book3s_hv.c | 2 +
arch/powerpc/platforms/powernv/opal.c | 2 +-
arch/s390/crypto/paes_s390.c | 2 +-
arch/x86/kernel/eisa.c | 10 +-
arch/x86/mm/pti.c | 25 ++++-
arch/xtensa/platforms/iss/setup.c | 25 +++--
block/blk-core.c | 8 +-
block/blk-mq-sched.c | 3 +-
block/blk-settings.c | 2 +-
crypto/api.c | 2 +-
drivers/base/core.c | 3 +
drivers/block/DAC960.c | 9 +-
drivers/char/ipmi/ipmi_bt_sm.c | 92 ++++++++---------
drivers/char/ipmi/ipmi_msghandler.c | 53 +++++-----
drivers/char/ipmi/ipmi_si_intf.c | 17 +---
drivers/char/ipmi/ipmi_ssif.c | 30 ++----
drivers/clk/clk-fixed-factor.c | 9 +-
drivers/clk/clk.c | 3 +
drivers/clk/imx/clk-imx6sll.c | 1 +
drivers/clk/imx/clk-imx6ul.c | 1 +
drivers/clk/mvebu/armada-37xx-periph.c | 3 -
drivers/clk/tegra/clk-bpmp.c | 12 ++-
drivers/crypto/ccp/psp-dev.c | 46 ++++++++-
drivers/crypto/sahara.c | 4 +-
drivers/devfreq/devfreq.c | 4 +-
drivers/dma/mv_xor_v2.c | 2 +
drivers/dma/pl330.c | 5 +-
drivers/dma/sh/rcar-dmac.c | 5 +-
drivers/firmware/efi/arm-init.c | 1 -
drivers/firmware/efi/arm-runtime.c | 4 +-
drivers/firmware/efi/esrt.c | 3 +-
drivers/gpio/gpio-pxa.c | 2 +
drivers/gpio/gpiolib.c | 14 ++-
drivers/gpio/gpiolib.h | 2 +-
drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c | 9 +-
drivers/gpu/drm/amd/amdkfd/kfd_process.c | 2 +
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 +
drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 9 +-
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 8 +-
drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c | 6 +-
drivers/gpu/drm/nouveau/nouveau_debugfs.c | 4 +
drivers/gpu/drm/nouveau/nouveau_drm.c | 6 +-
drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c | 13 +++
drivers/gpu/drm/panel/panel-samsung-s6e8aa0.c | 2 +-
drivers/gpu/ipu-v3/ipu-csi.c | 20 +++-
drivers/hv/vmbus_drv.c | 3 +
drivers/hwtracing/coresight/coresight-etm4x.c | 31 +++---
drivers/hwtracing/coresight/coresight-tpiu.c | 7 +-
drivers/hwtracing/coresight/coresight.c | 7 +-
drivers/i2c/busses/i2c-aspeed.c | 4 +-
drivers/infiniband/core/cma.c | 12 ++-
drivers/infiniband/hw/mlx5/cong.c | 9 +-
drivers/infiniband/hw/mlx5/mr.c | 32 ++----
drivers/infiniband/hw/nes/nes.h | 2 +-
drivers/infiniband/sw/rxe/rxe_recv.c | 9 +-
drivers/infiniband/ulp/ipoib/ipoib_cm.c | 2 +
drivers/infiniband/ulp/ipoib/ipoib_main.c | 3 +-
drivers/input/joystick/pxrc.c | 66 ++++++-------
drivers/input/touchscreen/rohm_bu21023.c | 4 +-
drivers/iommu/arm-smmu-v3.c | 1 +
drivers/iommu/io-pgtable-arm-v7s.c | 7 +-
drivers/iommu/io-pgtable-arm.c | 3 +-
drivers/iommu/ipmmu-vmsa.c | 8 ++
drivers/lightnvm/pblk-init.c | 5 +-
drivers/lightnvm/pblk-recovery.c | 5 +-
drivers/md/dm-verity-target.c | 24 ++++-
drivers/media/common/videobuf2/videobuf2-core.c | 5 +
drivers/media/i2c/ov5645.c | 13 +--
drivers/media/pci/tw686x/tw686x-video.c | 11 ++-
drivers/mfd/88pm860x-i2c.c | 8 +-
drivers/misc/hmc6352.c | 2 +
drivers/misc/ibmvmc.c | 2 +-
drivers/misc/mei/bus-fixup.c | 2 +-
drivers/misc/mei/bus.c | 12 +--
drivers/misc/mei/hbm.c | 9 +-
drivers/mmc/host/meson-mx-sdio.c | 8 +-
drivers/mmc/host/omap_hsmmc.c | 1 +
drivers/mmc/host/sdhci-of-esdhc.c | 6 ++
drivers/mmc/host/sdhci-tegra.c | 3 +-
drivers/mmc/host/sdhci.c | 9 +-
drivers/mtd/maps/solutionengine.c | 6 +-
drivers/mtd/mtdchar.c | 10 +-
drivers/net/ethernet/amd/xgbe/xgbe-desc.c | 7 +-
.../ethernet/cavium/liquidio/cn23xx_pf_device.c | 3 +
.../ethernet/cavium/liquidio/cn23xx_vf_device.c | 3 +
drivers/net/ethernet/cortina/gemini.c | 5 +-
drivers/net/ethernet/emulex/benet/be_cmds.c | 2 +-
drivers/net/ethernet/hisilicon/hns3/hns3_enet.c | 8 +-
.../ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 5 +-
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 6 ++
drivers/net/ethernet/mellanox/mlx5/core/cmd.c | 1 +
drivers/net/ethernet/mellanox/mlx5/core/dev.c | 15 ++-
.../ethernet/mellanox/mlx5/core/eswitch_offloads.c | 1 +
drivers/net/ethernet/mellanox/mlx5/core/fs_core.c | 76 +++++++-------
drivers/net/ethernet/mellanox/mlx5/core/health.c | 10 +-
drivers/net/ethernet/mellanox/mlx5/core/main.c | 12 ++-
drivers/net/ethernet/mellanox/mlx5/core/wq.c | 4 +-
drivers/net/ethernet/mellanox/mlx5/core/wq.h | 2 +-
drivers/net/ethernet/netronome/nfp/nfp_main.c | 20 ++--
.../net/ethernet/netronome/nfp/nfp_net_common.c | 13 ++-
drivers/net/ethernet/qualcomm/qca_7k.c | 76 +++++++-------
drivers/net/ethernet/qualcomm/qca_spi.c | 110 +++++++++++----------
drivers/net/ethernet/qualcomm/qca_spi.h | 5 -
drivers/net/wan/fsl_ucc_hdlc.c | 6 +-
drivers/net/wireless/intel/iwlwifi/pcie/internal.h | 12 ++-
drivers/net/wireless/intel/iwlwifi/pcie/tx.c | 11 ++-
drivers/net/xen-netfront.c | 30 +++---
drivers/nvme/host/rdma.c | 2 +
drivers/nvme/target/io-cmd-file.c | 18 ++--
drivers/of/base.c | 28 ++++++
drivers/parport/parport_sunbpp.c | 8 +-
drivers/pci/pcie/aer.c | 6 ++
drivers/pinctrl/mediatek/pinctrl-mt7622.c | 4 +-
drivers/pinctrl/pinctrl-rza1.c | 24 ++---
drivers/pinctrl/pinmux.c | 16 ++-
drivers/pinctrl/qcom/pinctrl-msm.c | 14 ++-
drivers/pinctrl/qcom/pinctrl-spmi-gpio.c | 32 ++++--
drivers/platform/x86/toshiba_acpi.c | 3 +-
drivers/regulator/qcom_spmi-regulator.c | 34 ++++---
drivers/remoteproc/qcom_q6v5_pil.c | 1 -
drivers/reset/reset-imx7.c | 2 +-
drivers/rtc/rtc-bq4802.c | 4 +
drivers/s390/net/qeth_core_main.c | 3 +-
drivers/s390/net/qeth_core_sys.c | 1 +
drivers/scsi/libfc/fc_disc.c | 7 +-
drivers/scsi/lpfc/lpfc_nvme.c | 5 +-
drivers/scsi/lpfc/lpfc_nvmet.c | 12 ++-
drivers/soc/qcom/smem.c | 10 +-
drivers/spi/spi-dw.c | 3 +-
drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.c | 2 +-
.../vc04_services/bcm2835-audio/bcm2835-vchiq.c | 16 +--
.../vc04_services/bcm2835-camera/bcm2835-camera.c | 7 +-
.../vc04_services/bcm2835-camera/mmal-vchiq.c | 11 ++-
drivers/tty/serial/8250/8250_of.c | 2 +-
drivers/tty/tty_baudrate.c | 13 ++-
drivers/usb/class/cdc-acm.c | 73 --------------
drivers/usb/class/cdc-acm.h | 1 -
drivers/usb/class/cdc-wdm.c | 2 +-
drivers/usb/core/hcd-pci.c | 2 -
drivers/usb/core/message.c | 11 +++
drivers/usb/core/quirks.c | 7 ++
drivers/usb/dwc3/gadget.h | 2 +-
drivers/usb/gadget/udc/net2280.c | 16 ++-
drivers/usb/gadget/udc/renesas_usb3.c | 5 +-
drivers/usb/host/u132-hcd.c | 2 +-
drivers/usb/host/xhci-mem.c | 4 +
drivers/usb/host/xhci.c | 30 ++++++
drivers/usb/misc/uss720.c | 4 +-
drivers/usb/misc/yurex.c | 5 +-
drivers/usb/mtu3/mtu3_core.c | 6 +-
drivers/usb/mtu3/mtu3_hw_regs.h | 1 +
drivers/usb/serial/io_ti.h | 2 +-
drivers/usb/serial/ti_usb_3410_5052.c | 2 +-
drivers/usb/storage/scsiglue.c | 9 ++
drivers/usb/storage/uas.c | 21 ++++
drivers/usb/storage/unusual_devs.h | 7 ++
drivers/video/fbdev/core/modedb.c | 41 +++++---
drivers/video/fbdev/goldfishfb.c | 1 +
drivers/video/fbdev/omap/omapfb_main.c | 2 +-
drivers/video/fbdev/omap2/omapfb/Makefile | 4 +-
drivers/video/fbdev/pxafb.c | 4 +-
drivers/video/fbdev/via/viafbdev.c | 3 +-
fs/binfmt_elf.c | 2 +-
fs/cifs/readdir.c | 11 ++-
fs/cifs/smb2pdu.c | 29 +++---
fs/configfs/dir.c | 11 +++
fs/f2fs/super.c | 16 ++-
fs/gfs2/bmap.c | 2 +-
fs/gfs2/rgrp.c | 3 +-
fs/namespace.c | 7 +-
fs/nfs/nfs4proc.c | 10 +-
fs/nfs/nfs4state.c | 2 +
fs/nfs/nfs4trace.h | 2 +-
fs/overlayfs/super.c | 26 ++---
fs/pstore/ram_core.c | 17 +++-
include/linux/crypto.h | 5 +
include/linux/mlx5/driver.h | 4 +-
include/linux/of.h | 8 ++
kernel/audit_watch.c | 12 ++-
kernel/bpf/cgroup.c | 7 +-
kernel/events/core.c | 4 +
kernel/rcu/rcutorture.c | 5 +-
kernel/rcu/tree.c | 6 ++
kernel/rcu/tree.h | 4 +
kernel/sched/fair.c | 10 +-
kernel/sched/wait.c | 47 ++++-----
net/bluetooth/af_bluetooth.c | 2 +-
net/core/skbuff.c | 3 -
net/ipv4/ip_gre.c | 5 +
net/ipv4/tcp.c | 2 +-
net/mac80211/cfg.c | 2 +-
net/mac80211/key.c | 24 +++--
net/rds/bind.c | 5 +-
net/tipc/socket.c | 1 +
net/tls/tls_sw.c | 14 ++-
net/xfrm/xfrm_policy.c | 5 +-
scripts/Kbuild.include | 3 +
security/integrity/evm/evm_crypto.c | 3 +-
security/security.c | 2 +
security/smack/smack_lsm.c | 14 ++-
sound/core/pcm_lib.c | 14 ++-
sound/isa/msnd/msnd_pinnacle.c | 4 +-
sound/soc/codecs/hdmi-codec.c | 21 ++--
sound/soc/codecs/rt5514.c | 8 +-
sound/soc/codecs/rt5651.c | 22 +++--
sound/soc/qcom/qdsp6/q6afe-dai.c | 2 +-
sound/usb/quirks-table.h | 3 +-
sound/usb/quirks.c | 2 +
tools/hv/hv_kvp_daemon.c | 2 +-
tools/perf/arch/powerpc/util/skip-callchain-idx.c | 10 +-
tools/perf/tests/builtin-test.c | 2 +-
.../tests/shell/record+probe_libc_inet_pton.sh | 36 ++++++-
tools/perf/util/comm.c | 16 ++-
tools/perf/util/header.c | 2 +-
tools/perf/util/machine.c | 9 +-
tools/perf/util/map.c | 11 +++
tools/perf/util/unwind-libdw.c | 2 +-
tools/perf/util/unwind-libunwind-local.c | 2 +-
tools/testing/nvdimm/test/nfit.c | 3 +-
.../testing/selftests/android/ion/ionapp_export.c | 1 +
tools/testing/selftests/timers/raw_skew.c | 5 +
tools/testing/selftests/vDSO/vdso_test.c | 7 +-
virt/kvm/arm/vgic/vgic-init.c | 4 +
virt/kvm/arm/vgic/vgic-mmio-v2.c | 3 +
238 files changed, 1599 insertions(+), 926 deletions(-)
^ permalink raw reply [relevance 2%]
* [PATCH 4.18 217/235] remoteproc: qcom: q6v5-pil: fix modem hang on SDM845 after axis2 clk unvote
2018-09-24 11:49 2% [PATCH 4.18 000/235] 4.18.10-stable review Greg Kroah-Hartman
@ 2018-09-24 11:53 8% ` Greg Kroah-Hartman
0 siblings, 0 replies; 200+ results
From: Greg Kroah-Hartman @ 2018-09-24 11:53 UTC (permalink / raw)
To: linux-kernel
Cc: Greg Kroah-Hartman, stable, Bjorn Andersson, Sibi Sankar, Sasha Levin
4.18-stable review patch. If anyone has any objections, please let me know.
------------------
From: Sibi Sankar <sibis@codeaurora.org>
[ Upstream commit 7cbb540a3a68e4d4a8bef2d9451afb1635b5d2d3 ]
GCC_MSS_AXIS2 clock is used for disabling boot IMEM (a part of
AP boot up). With Boot IMEM disable now a part TZ/ATF, AXIS2
clock is no longer required post AP boot up and expected to
remain untouched. However if the clock is turned ON after Q6
is brought out of reset and later turned off, it results in
modem hang. When Q6 attempts a power collapse the internal
handshaking to check if AXIS2 is idle never goes through since
it is turned off preventing the RSC from getting triggered,
leaving modem in a funky state. Hence removing AXIS2 clk
enable/disable from the driver.
Reported-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
drivers/remoteproc/qcom_q6v5_pil.c | 1 -
1 file changed, 1 deletion(-)
--- a/drivers/remoteproc/qcom_q6v5_pil.c
+++ b/drivers/remoteproc/qcom_q6v5_pil.c
@@ -1370,7 +1370,6 @@ static const struct rproc_hexagon_res sd
.hexagon_mba_image = "mba.mbn",
.proxy_clk_names = (char*[]){
"xo",
- "axis2",
"prng",
NULL
},
^ permalink raw reply [relevance 8%]
* Re: [PATCH] remoteproc: qcom: q6v5: Propagate EPROBE_DEFER
@ 2018-09-25 6:50 13% ` Sibi Sankar
2018-10-06 6:39 0% ` Bjorn Andersson
0 siblings, 1 reply; 200+ results
From: Sibi Sankar @ 2018-09-25 6:50 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Ohad Ben-Cohen, linux-remoteproc, linux-kernel, linux-arm-msm,
stable, linux-arm-msm-owner
On 2018-09-20 07:21, Bjorn Andersson wrote:
> In the case that the interrupts fail to result because of the
> interrupt-controller not yet being registered the
> platform_get_irq_byname() call will fail with -EPROBE_DEFER, but
> passing
> this into devm_request_threaded_irq() will result in -EINVAL being
> returned, the driver is therefor not reprobed later.
>
The patch looks fine.
Reviewed-by: Sibi Sankar <sibis@codeaurora.org>
> Fixes: 3b415c8fb263 ("remoteproc: q6v5: Extract common resource
> handling")
> Cc: stable@vger.kernel.org
> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> ---
> drivers/remoteproc/qcom_q6v5.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/drivers/remoteproc/qcom_q6v5.c
> b/drivers/remoteproc/qcom_q6v5.c
> index 61a760ee4aac..e9ab90c19304 100644
> --- a/drivers/remoteproc/qcom_q6v5.c
> +++ b/drivers/remoteproc/qcom_q6v5.c
> @@ -198,6 +198,9 @@ int qcom_q6v5_init(struct qcom_q6v5 *q6v5, struct
> platform_device *pdev,
> }
>
> q6v5->fatal_irq = platform_get_irq_byname(pdev, "fatal");
> + if (q6v5->fatal_irq == -EPROBE_DEFER)
> + return -EPROBE_DEFER;
> +
> ret = devm_request_threaded_irq(&pdev->dev, q6v5->fatal_irq,
> NULL, q6v5_fatal_interrupt,
> IRQF_TRIGGER_RISING | IRQF_ONESHOT,
> @@ -208,6 +211,9 @@ int qcom_q6v5_init(struct qcom_q6v5 *q6v5, struct
> platform_device *pdev,
> }
>
> q6v5->ready_irq = platform_get_irq_byname(pdev, "ready");
> + if (q6v5->ready_irq == -EPROBE_DEFER)
> + return -EPROBE_DEFER;
> +
> ret = devm_request_threaded_irq(&pdev->dev, q6v5->ready_irq,
> NULL, q6v5_ready_interrupt,
> IRQF_TRIGGER_RISING | IRQF_ONESHOT,
> @@ -218,6 +224,9 @@ int qcom_q6v5_init(struct qcom_q6v5 *q6v5, struct
> platform_device *pdev,
> }
>
> q6v5->handover_irq = platform_get_irq_byname(pdev, "handover");
> + if (q6v5->handover_irq == -EPROBE_DEFER)
> + return -EPROBE_DEFER;
> +
> ret = devm_request_threaded_irq(&pdev->dev, q6v5->handover_irq,
> NULL, q6v5_handover_interrupt,
> IRQF_TRIGGER_RISING | IRQF_ONESHOT,
> @@ -229,6 +238,9 @@ int qcom_q6v5_init(struct qcom_q6v5 *q6v5, struct
> platform_device *pdev,
> disable_irq(q6v5->handover_irq);
>
> q6v5->stop_irq = platform_get_irq_byname(pdev, "stop-ack");
> + if (q6v5->stop_irq == -EPROBE_DEFER)
> + return -EPROBE_DEFER;
> +
> ret = devm_request_threaded_irq(&pdev->dev, q6v5->stop_irq,
> NULL, q6v5_stop_interrupt,
> IRQF_TRIGGER_RISING | IRQF_ONESHOT,
--
-- Sibi Sankar --
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
^ permalink raw reply [relevance 13%]
* Re: [PATCH] remoteproc: qcom: pas: Add QCS404 remoteprocs
@ 2018-09-25 10:18 6% ` Sibi Sankar
0 siblings, 1 reply; 200+ results
From: Sibi Sankar @ 2018-09-25 10:18 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Ohad Ben-Cohen, Rob Herring, Mark Rutland, linux-remoteproc,
devicetree, linux-kernel, linux-arm-msm, linux-kernel-owner
Hi Bjorn,
On 2018-09-20 22:52, Bjorn Andersson wrote:
> From: Govind Singh <govinds@codeaurora.org>
>
> Add compatibles for the three PAS based remote processors found in
> QCS404.
>
> Signed-off-by: Govind Singh <govinds@codeaurora.org>
> [bjorn: Added adsp and cdsp to the patch]
> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> ---
> .../devicetree/bindings/remoteproc/qcom,adsp.txt | 3 +++
> drivers/remoteproc/qcom_adsp_pil.c | 12 ++++++++++++
> 2 files changed, 15 insertions(+)
>
> diff --git
> a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.txt
> b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.txt
> index b7d058228185..9c0cff3a5ed8 100644
> --- a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.txt
> +++ b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.txt
> @@ -10,6 +10,9 @@ on the Qualcomm ADSP Hexagon core.
> "qcom,msm8974-adsp-pil"
> "qcom,msm8996-adsp-pil"
> "qcom,msm8996-slpi-pil"
> + "qcom,qcs404-adsp-pas"
> + "qcom,qcs404-cdsp-pas"
> + "qcom,qcs404-wcss-pas"
> "qcom,sdm845-adsp-pas"
> "qcom,sdm845-cdsp-pas"
>
> diff --git a/drivers/remoteproc/qcom_adsp_pil.c
> b/drivers/remoteproc/qcom_adsp_pil.c
> index da2254ea1135..fcbb816a9698 100644
> --- a/drivers/remoteproc/qcom_adsp_pil.c
> +++ b/drivers/remoteproc/qcom_adsp_pil.c
> @@ -362,10 +362,22 @@ static const struct adsp_data slpi_resource_init
> = {
> .ssctl_id = 0x16,
> };
>
> +static const struct adsp_data wcss_resource_init = {
> + .crash_reason_smem = 421,
> + .firmware_name = "wcnss.mdt",
> + .pas_id = 6,
> + .ssr_name = "mpss",
> + .sysmon_name = "wlan",
Shouldn't the sysmon name be "wcnss" instead of "wlan"?
> + .ssctl_id = 0x12,
> +};
> +
> static const struct of_device_id adsp_of_match[] = {
> { .compatible = "qcom,msm8974-adsp-pil", .data =
> &adsp_resource_init},
> { .compatible = "qcom,msm8996-adsp-pil", .data =
> &adsp_resource_init},
> { .compatible = "qcom,msm8996-slpi-pil", .data =
> &slpi_resource_init},
> + { .compatible = "qcom,qcs404-adsp-pas", .data = &adsp_resource_init
> },
> + { .compatible = "qcom,qcs404-cdsp-pas", .data = &cdsp_resource_init
> },
> + { .compatible = "qcom,qcs404-wcss-pas", .data = &wcss_resource_init
> },
> { .compatible = "qcom,sdm845-adsp-pas", .data = &adsp_resource_init},
> { .compatible = "qcom,sdm845-cdsp-pas", .data = &cdsp_resource_init},
> { },
--
-- Sibi Sankar --
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
^ permalink raw reply [relevance 6%]
* Re: [PATCH] remoteproc: qcom: pas: Add QCS404 remoteprocs
@ 2018-09-26 15:48 6% ` Sibi Sankar
0 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2018-09-26 15:48 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Ohad Ben-Cohen, Rob Herring, Mark Rutland, linux-remoteproc,
devicetree, linux-kernel, linux-arm-msm, linux-kernel-owner,
linux-remoteproc-owner
On 2018-09-26 05:05, Bjorn Andersson wrote:
> On Tue 25 Sep 03:18 PDT 2018, Sibi Sankar wrote:
>> On 2018-09-20 22:52, Bjorn Andersson wrote:
>> > diff --git a/drivers/remoteproc/qcom_adsp_pil.c
>> > b/drivers/remoteproc/qcom_adsp_pil.c
>> > index da2254ea1135..fcbb816a9698 100644
>> > --- a/drivers/remoteproc/qcom_adsp_pil.c
>> > +++ b/drivers/remoteproc/qcom_adsp_pil.c
>> > @@ -362,10 +362,22 @@ static const struct adsp_data slpi_resource_init =
>> > {
>> > .ssctl_id = 0x16,
>> > };
>> >
>> > +static const struct adsp_data wcss_resource_init = {
>> > + .crash_reason_smem = 421,
>> > + .firmware_name = "wcnss.mdt",
>> > + .pas_id = 6,
>> > + .ssr_name = "mpss",
>> > + .sysmon_name = "wlan",
>>
>> Shouldn't the sysmon name be "wcnss" instead of "wlan"?
>>
>
> I derived this from the downstream kernel, perhaps I got it wrong?
>
I could see that the label is "wcnss" and glink-label is "mpss"
downstream.
> Regards,
> Bjorn
--
-- Sibi Sankar --
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
^ permalink raw reply [relevance 6%]
* Re: [PATCH v2] remoteproc: qcom: pas: Add QCS404 remoteprocs
@ 2018-09-28 6:27 13% ` Sibi Sankar
2018-10-06 6:38 0% ` Bjorn Andersson
0 siblings, 1 reply; 200+ results
From: Sibi Sankar @ 2018-09-28 6:27 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Ohad Ben-Cohen, Rob Herring, Mark Rutland, linux-remoteproc,
devicetree, linux-kernel, linux-kernel-owner
On 2018-09-28 00:33, Bjorn Andersson wrote:
> Add compatibles for the three PAS based remote processors found in
> QCS404.
>
> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> ---
>
Reviewed-by: Sibi Sankar <sibis@codeaurora.org>
> Changes since v1:
> - Fixed incorrect sysmon_name, as pointed out by Sibi.
>
> .../devicetree/bindings/remoteproc/qcom,adsp.txt | 3 +++
> drivers/remoteproc/qcom_adsp_pil.c | 12 ++++++++++++
> 2 files changed, 15 insertions(+)
>
> diff --git
> a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.txt
> b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.txt
> index b7d058228185..9c0cff3a5ed8 100644
> --- a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.txt
> +++ b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.txt
> @@ -10,6 +10,9 @@ on the Qualcomm ADSP Hexagon core.
> "qcom,msm8974-adsp-pil"
> "qcom,msm8996-adsp-pil"
> "qcom,msm8996-slpi-pil"
> + "qcom,qcs404-adsp-pas"
> + "qcom,qcs404-cdsp-pas"
> + "qcom,qcs404-wcss-pas"
> "qcom,sdm845-adsp-pas"
> "qcom,sdm845-cdsp-pas"
>
> diff --git a/drivers/remoteproc/qcom_adsp_pil.c
> b/drivers/remoteproc/qcom_adsp_pil.c
> index da2254ea1135..d5e58235e83a 100644
> --- a/drivers/remoteproc/qcom_adsp_pil.c
> +++ b/drivers/remoteproc/qcom_adsp_pil.c
> @@ -362,10 +362,22 @@ static const struct adsp_data slpi_resource_init
> = {
> .ssctl_id = 0x16,
> };
>
> +static const struct adsp_data wcss_resource_init = {
> + .crash_reason_smem = 421,
> + .firmware_name = "wcnss.mdt",
> + .pas_id = 6,
> + .ssr_name = "mpss",
> + .sysmon_name = "wcnss",
> + .ssctl_id = 0x12,
> +};
> +
> static const struct of_device_id adsp_of_match[] = {
> { .compatible = "qcom,msm8974-adsp-pil", .data =
> &adsp_resource_init},
> { .compatible = "qcom,msm8996-adsp-pil", .data =
> &adsp_resource_init},
> { .compatible = "qcom,msm8996-slpi-pil", .data =
> &slpi_resource_init},
> + { .compatible = "qcom,qcs404-adsp-pas", .data = &adsp_resource_init
> },
> + { .compatible = "qcom,qcs404-cdsp-pas", .data = &cdsp_resource_init
> },
> + { .compatible = "qcom,qcs404-wcss-pas", .data = &wcss_resource_init
> },
> { .compatible = "qcom,sdm845-adsp-pas", .data = &adsp_resource_init},
> { .compatible = "qcom,sdm845-cdsp-pas", .data = &cdsp_resource_init},
> { },
--
-- Sibi Sankar --
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
^ permalink raw reply [relevance 13%]
* Re: [RFC PATCH] soc: qcom: rmtfs_mem: Control remoteproc from rmtfs_mem
@ 2018-09-30 15:28 6% ` Sibi Sankar
0 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2018-09-30 15:28 UTC (permalink / raw)
To: Brian Norris, Bjorn Andersson
Cc: Rob Herring, Mark Rutland, Andy Gross, David Brown,
Avaneesh Kumar Dwivedi, devicetree, linux-kernel, linux-arm-msm,
linux-soc, linux-arm-msm-owner
On 2018-09-25 22:59, Brian Norris wrote:
> Hi Bjorn,
>
> On Tue, Sep 25, 2018 at 01:06:07AM -0700, Bjorn Andersson wrote:
>> rmtfs_mem provides access to physical storage and is crucial for the
>> operation of the Qualcomm modem subsystem.
>>
>> The rmtfs_mem implementation must be available before the modem
>> subsystem is booted and a solution where the modem remoteproc will
>> verify that the rmtfs_mem is available has been discussed in the past.
>> But this would not handle the case where the rmtfs_mem provider is
>> restarted, which would cause fatal loss of access to the storage
>> device
>> for the modem.
>>
>> The suggestion is therefor to link the rmtfs_mem to its associated
>> remote processor instance and control it based on the availability of
>> the rmtfs_mem implementation.
>
> But what does "availability" mean? If I'm reading your rmtfs daemon
> properly, "availability" should mean that the daemon is up and has
> registered a RMTFS_QMI_SERVICE. But in this patch, you're keying off of
> the open() call, which sounds like you're introducing a race condition
> -- we might have open()ed the RMTFS memory but we're not actually
> completely ready to service requests.
>
> So rather than looking for open(), I think somebody needs to be looking
> for the appearance and disappearance of the RMTFS_QMI_SERVICE. (Looking
> for disappearance would resolve the daemon restart issue, no?) That
> "somebody" could be the remoteproc driver I suppose
> (qmi_add_lookup()?),
> or...couldn't it just be the modem itself? Do you actually need to
> restart the entire modem when the RMTFS service goes away, or do you
> just need to pause storage activity?
>
Hi Brian,
It might be more logical to make that "somebody" the rmtfs_mem driver
itself, since
the modem as such does not have any direct functional dependency on
rmtfs_mem i.e
the firmware can be configured to run on rmtfs_mem or internal fs. So in
such cases
where the modem is running on internal fs, it would be undesirable to
have a hard
coded dependency for rmtfs_mem in remoteproc modem itself.
Wouldn't it be simpler/quicker to fix this in kernel than churning out
new firmware
releases. A fix in firmware will also mean that this becomes one-off fix
for dragon
boards diverging the firmware branch from whats used in android for
8916/8974/8996.
>> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
>> ---
>>
>> The currently implemented workaround in the Linaro QCOMLT releases is
>> to
>> blacklist the qcom_q6v5_pil kernel module and load this explicitly
>> after rmtfs
>> has been started.
>>
>> With this patch the modem module can be loaded automatically by the
>> platform_bus and will only be booted as the rmtfs becomes available.
>> Performing
>> actions such as upgrading (and restarting) the rmtfs service will
>> cause the
>> modem to automatically restart and hence continue to function after
>> the
>> upgrade.
>>
>> .../reserved-memory/qcom,rmtfs-mem.txt | 7 ++++++
>> drivers/remoteproc/qcom_q6v5_pil.c | 1 +
>> drivers/soc/qcom/Kconfig | 1 +
>> drivers/soc/qcom/rmtfs_mem.c | 23
>> ++++++++++++++++++-
>> 4 files changed, 31 insertions(+), 1 deletion(-)
>>
> ...
>> diff --git a/drivers/soc/qcom/rmtfs_mem.c
>> b/drivers/soc/qcom/rmtfs_mem.c
>> index 8a3678c2e83c..8b08be310397 100644
>> --- a/drivers/soc/qcom/rmtfs_mem.c
>> +++ b/drivers/soc/qcom/rmtfs_mem.c
>> @@ -18,6 +18,7 @@
>> #include <linux/platform_device.h>
>> #include <linux/of.h>
>> #include <linux/of_reserved_mem.h>
>> +#include <linux/remoteproc.h>
>> #include <linux/dma-mapping.h>
>> #include <linux/slab.h>
>> #include <linux/uaccess.h>
>> @@ -39,6 +40,8 @@ struct qcom_rmtfs_mem {
>> unsigned int client_id;
>>
>> unsigned int perms;
>> +
>> + struct rproc *rproc;
>> };
>>
>> static ssize_t qcom_rmtfs_mem_show(struct device *dev,
>> @@ -80,11 +83,18 @@ static int qcom_rmtfs_mem_open(struct inode
>> *inode, struct file *filp)
>> struct qcom_rmtfs_mem *rmtfs_mem = container_of(inode->i_cdev,
>> struct qcom_rmtfs_mem,
>> cdev);
>> + int ret = 0;
>>
>> get_device(&rmtfs_mem->dev);
>> filp->private_data = rmtfs_mem;
>>
>> - return 0;
>> + if (rmtfs_mem->rproc) {
>> + ret = rproc_boot(rmtfs_mem->rproc);
>> + if (ret)
>> + put_device(&rmtfs_mem->dev);
>> + }
>> +
>> + return ret;
>> }
>> static ssize_t qcom_rmtfs_mem_read(struct file *filp,
>> char __user *buf, size_t count, loff_t *f_pos)
>> @@ -127,6 +137,9 @@ static int qcom_rmtfs_mem_release(struct inode
>> *inode, struct file *filp)
>> {
>> struct qcom_rmtfs_mem *rmtfs_mem = filp->private_data;
>>
>> + if (rmtfs_mem->rproc)
>> + rproc_shutdown(rmtfs_mem->rproc);
>> +
>> put_device(&rmtfs_mem->dev);
>>
>> return 0;
>> @@ -156,6 +169,7 @@ static int qcom_rmtfs_mem_probe(struct
>> platform_device *pdev)
>> struct qcom_scm_vmperm perms[2];
>> struct reserved_mem *rmem;
>> struct qcom_rmtfs_mem *rmtfs_mem;
>> + phandle rproc_phandle;
>> u32 client_id;
>> u32 vmid;
>> int ret;
>> @@ -181,6 +195,13 @@ static int qcom_rmtfs_mem_probe(struct
>> platform_device *pdev)
>> rmtfs_mem->client_id = client_id;
>> rmtfs_mem->size = rmem->size;
>>
>> + ret = of_property_read_u32(node, "rproc", &rproc_phandle);
>> + if (!ret) {
>> + rmtfs_mem->rproc = rproc_get_by_phandle(rproc_phandle);
>
> You're doing an rproc_get(), so you need to do a rproc_put() in
> remove().
>
> Brian
>
>> + if (!rmtfs_mem->rproc)
>> + return -EPROBE_DEFER;
>> + }
>> +
>> device_initialize(&rmtfs_mem->dev);
>> rmtfs_mem->dev.parent = &pdev->dev;
>> rmtfs_mem->dev.groups = qcom_rmtfs_mem_groups;
--
-- Sibi Sankar --
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
^ permalink raw reply [relevance 6%]
* [RFC PATCH v2] soc: qcom: rmtfs_mem: Control remoteproc from rmtfs_mem
@ 2018-09-30 15:56 16% Sibi Sankar
0 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2018-09-30 15:56 UTC (permalink / raw)
To: bjorn.andersson, briannorris, david.brown, robh+dt, mark.rutland,
andy.gross
Cc: akdwived, clew, linux-kernel, linux-arm-msm, linux-soc,
linux-arm-msm-owner, Sibi Sankar
From: Bjorn Andersson <bjorn.andersson@linaro.org>
rmtfs_mem provides access to physical storage and is crucial for the
operation of the Qualcomm modem subsystem.
The rmtfs_mem implementation must be available before the modem
subsystem is booted and a solution where the modem remoteproc will
verify that the rmtfs_mem is available has been discussed in the past.
But this would not handle the case where the rmtfs_mem provider is
restarted, which would cause fatal loss of access to the storage device
for the modem.
The suggestion is therefore to link the rmtfs_mem to its associated
remote processor instance and control it based on the availability of
the rmtfs_mem implementation.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
[sibis: Added qmi lookup for Remote file system service]
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
The currently implemented workaround in the Linaro QCOMLT releases is to
blacklist the qcom_q6v5_pil kernel module and load this explicitly after rmtfs
has been started.
With this patch the modem module can be loaded automatically by the
platform_bus and will only be booted as the rmtfs becomes available. Performing
actions such as upgrading (and restarting) the rmtfs service will cause the
modem to automatically restart and hence continue to function after the
upgrade.
v2:
Remove rproc_boot/shutdown from rmtfs_mem open/release and add
qmi lookup for Remote file system service to address Brian's
race concerns.
.../reserved-memory/qcom,rmtfs-mem.txt | 7 ++
drivers/remoteproc/qcom_q6v5_pil.c | 1 +
drivers/soc/qcom/Kconfig | 2 +
drivers/soc/qcom/rmtfs_mem.c | 65 ++++++++++++++++++-
4 files changed, 72 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/reserved-memory/qcom,rmtfs-mem.txt b/Documentation/devicetree/bindings/reserved-memory/qcom,rmtfs-mem.txt
index 8562ba1dce69..95b209e7f5d1 100644
--- a/Documentation/devicetree/bindings/reserved-memory/qcom,rmtfs-mem.txt
+++ b/Documentation/devicetree/bindings/reserved-memory/qcom,rmtfs-mem.txt
@@ -32,6 +32,13 @@ access block device data using the Remote Filesystem protocol.
Value type: <u32>
Definition: vmid of the remote processor, to set up memory protection.
+- rproc:
+ Usage: optional
+ Value type: <phandle>
+ Definition: reference to a remoteproc node, that should be powered up
+ while the remote file system memory instance is ready to
+ handle requests from the remote subsystem.
+
= EXAMPLE
The following example shows the remote filesystem memory setup for APQ8016,
with the rmtfs region for the Hexagon DSP (id #1) located at 0x86700000.
diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
index d7a4b9eca5d2..1445a38e8b34 100644
--- a/drivers/remoteproc/qcom_q6v5_pil.c
+++ b/drivers/remoteproc/qcom_q6v5_pil.c
@@ -1142,6 +1142,7 @@ static int q6v5_probe(struct platform_device *pdev)
qproc = (struct q6v5 *)rproc->priv;
qproc->dev = &pdev->dev;
qproc->rproc = rproc;
+ rproc->auto_boot = false;
platform_set_drvdata(pdev, qproc);
ret = q6v5_init_mem(qproc, pdev);
diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig
index 8a7b8dea6990..4e3345944325 100644
--- a/drivers/soc/qcom/Kconfig
+++ b/drivers/soc/qcom/Kconfig
@@ -86,7 +86,9 @@ config QCOM_QMI_HELPERS
config QCOM_RMTFS_MEM
tristate "Qualcomm Remote Filesystem memory driver"
depends on ARCH_QCOM
+ depends on REMOTEPROC
select QCOM_SCM
+ select QCOM_QMI_HELPERS
help
The Qualcomm remote filesystem memory driver is used for allocating
and exposing regions of shared memory with remote processors for the
diff --git a/drivers/soc/qcom/rmtfs_mem.c b/drivers/soc/qcom/rmtfs_mem.c
index 97bb5989aa21..757e30083f67 100644
--- a/drivers/soc/qcom/rmtfs_mem.c
+++ b/drivers/soc/qcom/rmtfs_mem.c
@@ -18,11 +18,13 @@
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_reserved_mem.h>
+#include <linux/remoteproc.h>
#include <linux/dma-mapping.h>
#include <linux/slab.h>
#include <linux/uaccess.h>
#include <linux/io.h>
#include <linux/qcom_scm.h>
+#include <linux/soc/qcom/qmi.h>
#define QCOM_RMTFS_MEM_DEV_MAX (MINORMASK + 1)
@@ -31,6 +33,7 @@ static dev_t qcom_rmtfs_mem_major;
struct qcom_rmtfs_mem {
struct device dev;
struct cdev cdev;
+ struct qmi_handle rmtfs_hdl;
void *base;
phys_addr_t addr;
@@ -39,6 +42,8 @@ struct qcom_rmtfs_mem {
unsigned int client_id;
unsigned int perms;
+
+ struct rproc *rproc;
};
static ssize_t qcom_rmtfs_mem_show(struct device *dev,
@@ -141,6 +146,36 @@ static const struct file_operations qcom_rmtfs_mem_fops = {
.llseek = default_llseek,
};
+static int rmtfs_new_server(struct qmi_handle *qmi,
+ struct qmi_service *service)
+{
+ int ret = 0;
+ struct qcom_rmtfs_mem *rmtfs_mem = container_of(qmi,
+ struct qcom_rmtfs_mem,
+ rmtfs_hdl);
+
+ if (rmtfs_mem->rproc)
+ ret = rproc_boot(rmtfs_mem->rproc);
+
+ return ret;
+};
+
+static void rmtfs_del_server(struct qmi_handle *qmi,
+ struct qmi_service *service)
+{
+ struct qcom_rmtfs_mem *rmtfs_mem = container_of(qmi,
+ struct qcom_rmtfs_mem,
+ rmtfs_hdl);
+
+ if (rmtfs_mem->rproc)
+ rproc_shutdown(rmtfs_mem->rproc);
+};
+
+static struct qmi_ops rmtfs_lookup_ops = {
+ .new_server = rmtfs_new_server,
+ .del_server = rmtfs_del_server,
+};
+
static void qcom_rmtfs_mem_release_device(struct device *dev)
{
struct qcom_rmtfs_mem *rmtfs_mem = container_of(dev,
@@ -156,6 +191,7 @@ static int qcom_rmtfs_mem_probe(struct platform_device *pdev)
struct qcom_scm_vmperm perms[2];
struct reserved_mem *rmem;
struct qcom_rmtfs_mem *rmtfs_mem;
+ phandle rproc_phandle;
u32 client_id;
u32 vmid;
int ret;
@@ -181,6 +217,22 @@ static int qcom_rmtfs_mem_probe(struct platform_device *pdev)
rmtfs_mem->client_id = client_id;
rmtfs_mem->size = rmem->size;
+ ret = of_property_read_u32(node, "rproc", &rproc_phandle);
+ if (!ret) {
+ rmtfs_mem->rproc = rproc_get_by_phandle(rproc_phandle);
+ if (!rmtfs_mem->rproc)
+ return -EPROBE_DEFER;
+ }
+
+ ret = qmi_handle_init(&rmtfs_mem->rmtfs_hdl, 0,
+ &rmtfs_lookup_ops, NULL);
+ if (ret < 0)
+ goto put_rproc;
+
+ ret = qmi_add_lookup(&rmtfs_mem->rmtfs_hdl, 14, 0, 0);
+ if (ret < 0)
+ goto err_release_qmi_handle;
+
device_initialize(&rmtfs_mem->dev);
rmtfs_mem->dev.parent = &pdev->dev;
rmtfs_mem->dev.groups = qcom_rmtfs_mem_groups;
@@ -191,7 +243,7 @@ static int qcom_rmtfs_mem_probe(struct platform_device *pdev)
if (IS_ERR(rmtfs_mem->base)) {
dev_err(&pdev->dev, "failed to remap rmtfs_mem region\n");
ret = PTR_ERR(rmtfs_mem->base);
- goto put_device;
+ goto err_release_qmi_handle;
}
cdev_init(&rmtfs_mem->cdev, &qcom_rmtfs_mem_fops);
@@ -204,7 +256,7 @@ static int qcom_rmtfs_mem_probe(struct platform_device *pdev)
ret = cdev_device_add(&rmtfs_mem->cdev, &rmtfs_mem->dev);
if (ret) {
dev_err(&pdev->dev, "failed to add cdev: %d\n", ret);
- goto put_device;
+ goto err_release_qmi_handle;
}
ret = of_property_read_u32(node, "qcom,vmid", &vmid);
@@ -237,7 +289,10 @@ static int qcom_rmtfs_mem_probe(struct platform_device *pdev)
remove_cdev:
cdev_device_del(&rmtfs_mem->cdev, &rmtfs_mem->dev);
-put_device:
+err_release_qmi_handle:
+ qmi_handle_release(&rmtfs_mem->rmtfs_hdl);
+put_rproc:
+ rproc_put(rmtfs_mem->rproc);
put_device(&rmtfs_mem->dev);
return ret;
@@ -257,6 +312,10 @@ static int qcom_rmtfs_mem_remove(struct platform_device *pdev)
}
cdev_device_del(&rmtfs_mem->cdev, &rmtfs_mem->dev);
+ if (rmtfs_mem->rproc) {
+ qmi_handle_release(&rmtfs_mem->rmtfs_hdl);
+ rproc_put(rmtfs_mem->rproc);
+ }
put_device(&rmtfs_mem->dev);
return 0;
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 16%]
* [PATCH] remoteproc: qcom: q6v5: Fix a race condition on fatal crash
@ 2018-10-01 14:25 19% Sibi Sankar
2018-10-06 6:35 0% ` Bjorn Andersson
0 siblings, 1 reply; 200+ results
From: Sibi Sankar @ 2018-10-01 14:25 UTC (permalink / raw)
To: bjorn.andersson
Cc: ohad, linux-remoteproc, linux-kernel, linux-arm-msm,
linux-arm-msm-owner, Sibi Sankar
Currently with GLINK_SSR enabled each fatal crash results in servicing
a crash from wdog as well. This is due to a race that occurs in setting
the running flag in the shutdown path. Fix this by moving the running
flag to the end of fatal interrupt handler.
Crash Logs:
qcom-q6v5-pil 4080000.remoteproc: fatal error without message
remoteproc remoteproc0: crash detected in 4080000.remoteproc: type fatal
error
remoteproc remoteproc0: handling crash #1 in 4080000.remoteproc
remoteproc remoteproc0: recovering 4080000.remoteproc
qcom-q6v5-pil 4080000.remoteproc: watchdog without message
remoteproc remoteproc0: crash detected in 4080000.remoteproc: type watchdog
remoteproc:glink-edge: intent request timed out
qcom_glink_ssr remoteproc:glink-edge.glink_ssr.-1.-1: failed to send
cleanup message
qcom_glink_ssr remoteproc:glink-edge.glink_ssr.-1.-1: timeout waiting
for cleanup done message
qcom-q6v5-pil 4080000.remoteproc: timed out on wait
qcom-q6v5-pil 4080000.remoteproc: port failed halt
remoteproc remoteproc0: stopped remote processor 4080000.remoteproc
qcom-q6v5-pil 4080000.remoteproc: MBA booted, loading mpss
remoteproc remoteproc0: remote processor 4080000.remoteproc is now up
remoteproc remoteproc0: handling crash #2 in 4080000.remoteproc
remoteproc remoteproc0: recovering 4080000.remoteproc
qcom-q6v5-pil 4080000.remoteproc: port failed halt
remoteproc remoteproc0: stopped remote processor 4080000.remoteproc
qcom-q6v5-pil 4080000.remoteproc: MBA booted, loading mpss
remoteproc remoteproc0: remote processor 4080000.remoteproc is now up
[bjorn: move running flag to the end of fatal interrupt handler]
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
drivers/remoteproc/qcom_q6v5.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/remoteproc/qcom_q6v5.c b/drivers/remoteproc/qcom_q6v5.c
index e9ab90c19304..edeb2e43209e 100644
--- a/drivers/remoteproc/qcom_q6v5.c
+++ b/drivers/remoteproc/qcom_q6v5.c
@@ -84,6 +84,7 @@ static irqreturn_t q6v5_fatal_interrupt(int irq, void *data)
else
dev_err(q6v5->dev, "fatal error without message\n");
+ q6v5->running = false;
rproc_report_crash(q6v5->rproc, RPROC_FATAL_ERROR);
return IRQ_HANDLED;
@@ -150,8 +151,6 @@ int qcom_q6v5_request_stop(struct qcom_q6v5 *q6v5)
{
int ret;
- q6v5->running = false;
-
qcom_smem_state_update_bits(q6v5->state,
BIT(q6v5->stop_bit), BIT(q6v5->stop_bit));
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 19%]
* Re: [PATCH v3 0/6] Add support for PDC Global on SDM845 SoCs
@ 2018-10-04 18:27 6% ` Sibi Sankar
0 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2018-10-04 18:27 UTC (permalink / raw)
To: Bjorn Andersson, p.zabel
Cc: mka, robh+dt, linux-kernel, devicetree, mark.rutland,
linux-arm-msm, tsoni
Hey Phillip,
Will the PDC driver make the cut for reset/next this time for the
4.20rc?
On 09/04/2018 01:06 AM, Bjorn Andersson wrote:
> On Wed 29 Aug 12:12 PDT 2018, Sibi Sankar wrote:
>
>> This patch series add support for PDC Global (Power Domain Controller)
>> on SDM845 SoCs and adds pdc reset lines assert/deassert to remoteproc
>> Q6v5 modem-pil. The first two patches adds PDC Global reset driver to
>> control reset signals of Modem, Compute, Display, GPU, Debug, AOP,
>> Sensors, Audio, SP and APPS. The last four patches (cleans up)/adds pdc
>> reset lines to q6v5 bindings and asserts/deasserts in modem start/stop
>> path.
>>
>> V3:
>> refactored pdc reset driver to remove unused layer of indirection
>> as suggested by Matthias
>> Other minor fixes suggested by Matthias/Bjorn
>>
>> V2:
>> Incorporated Philipp/Bjorn/Rob suggestions
>> Renamed reset binding to pdc-global.txt
>> replaced offset with #define of register name
>> replaced with devm_reset_control_get_exclusive()
>> Separted dt binding from the drivers
>>
>> Sibi Sankar (6):
>> dt-bindings: reset: Add PDC Global binding for SDM845 SoCs
>> reset: qcom: PDC Global (Power Domain Controller) reset controller
>
> Philipp, there's no compile time dependencies between the PDC and
> remoteproc patches in this series. Will you take these two through your
> tree and I'll take the remaining four through the remoteproc tree?
>
> Regards,
> Bjorn
>
>> dt-bindings: remoteproc: qcom: Remove additional definition tag
>> dt-bindings: remoteproc: Add PDC reset binding for Q6V5 PIL
>> remoteproc: qcom: q6v5-pil: Explicitly get mss_restart line
>> remoteproc: qcom: q6v5-pil: Add PDC reset for modem on SDM845 SoCs
>>
>> .../bindings/remoteproc/qcom,q6v5.txt | 8 +-
>> .../bindings/reset/qcom,pdc-global.txt | 52 ++++++++
>> drivers/remoteproc/qcom_q6v5_pil.c | 31 ++++-
>> drivers/reset/Kconfig | 9 ++
>> drivers/reset/Makefile | 1 +
>> drivers/reset/reset-qcom-pdc.c | 124 ++++++++++++++++++
>> include/dt-bindings/reset/qcom,sdm845-pdc.h | 20 +++
>> 7 files changed, 237 insertions(+), 8 deletions(-)
>> create mode 100644 Documentation/devicetree/bindings/reset/qcom,pdc-global.txt
>> create mode 100644 drivers/reset/reset-qcom-pdc.c
>> create mode 100644 include/dt-bindings/reset/qcom,sdm845-pdc.h
>>
>> --
>> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
>> a Linux Foundation Collaborative Project
>>
>
--
Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc, is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [relevance 6%]
* Re: [PATCH] remoteproc: qcom: q6v5: Fix a race condition on fatal crash
2018-10-01 14:25 19% [PATCH] remoteproc: qcom: q6v5: Fix a race condition on fatal crash Sibi Sankar
@ 2018-10-06 6:35 0% ` Bjorn Andersson
0 siblings, 0 replies; 200+ results
From: Bjorn Andersson @ 2018-10-06 6:35 UTC (permalink / raw)
To: Sibi Sankar
Cc: ohad, linux-remoteproc, linux-kernel, linux-arm-msm, linux-arm-msm-owner
On Mon 01 Oct 07:25 PDT 2018, Sibi Sankar wrote:
> Currently with GLINK_SSR enabled each fatal crash results in servicing
> a crash from wdog as well. This is due to a race that occurs in setting
> the running flag in the shutdown path. Fix this by moving the running
> flag to the end of fatal interrupt handler.
>
> Crash Logs:
> qcom-q6v5-pil 4080000.remoteproc: fatal error without message
> remoteproc remoteproc0: crash detected in 4080000.remoteproc: type fatal
> error
> remoteproc remoteproc0: handling crash #1 in 4080000.remoteproc
> remoteproc remoteproc0: recovering 4080000.remoteproc
> qcom-q6v5-pil 4080000.remoteproc: watchdog without message
> remoteproc remoteproc0: crash detected in 4080000.remoteproc: type watchdog
> remoteproc:glink-edge: intent request timed out
> qcom_glink_ssr remoteproc:glink-edge.glink_ssr.-1.-1: failed to send
> cleanup message
> qcom_glink_ssr remoteproc:glink-edge.glink_ssr.-1.-1: timeout waiting
> for cleanup done message
> qcom-q6v5-pil 4080000.remoteproc: timed out on wait
> qcom-q6v5-pil 4080000.remoteproc: port failed halt
> remoteproc remoteproc0: stopped remote processor 4080000.remoteproc
> qcom-q6v5-pil 4080000.remoteproc: MBA booted, loading mpss
> remoteproc remoteproc0: remote processor 4080000.remoteproc is now up
> remoteproc remoteproc0: handling crash #2 in 4080000.remoteproc
> remoteproc remoteproc0: recovering 4080000.remoteproc
> qcom-q6v5-pil 4080000.remoteproc: port failed halt
> remoteproc remoteproc0: stopped remote processor 4080000.remoteproc
> qcom-q6v5-pil 4080000.remoteproc: MBA booted, loading mpss
> remoteproc remoteproc0: remote processor 4080000.remoteproc is now up
>
> [bjorn: move running flag to the end of fatal interrupt handler]
Turned this line into a Suggested-by
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Applied.
Thanks,
Bjorn
> ---
> drivers/remoteproc/qcom_q6v5.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/remoteproc/qcom_q6v5.c b/drivers/remoteproc/qcom_q6v5.c
> index e9ab90c19304..edeb2e43209e 100644
> --- a/drivers/remoteproc/qcom_q6v5.c
> +++ b/drivers/remoteproc/qcom_q6v5.c
> @@ -84,6 +84,7 @@ static irqreturn_t q6v5_fatal_interrupt(int irq, void *data)
> else
> dev_err(q6v5->dev, "fatal error without message\n");
>
> + q6v5->running = false;
> rproc_report_crash(q6v5->rproc, RPROC_FATAL_ERROR);
>
> return IRQ_HANDLED;
> @@ -150,8 +151,6 @@ int qcom_q6v5_request_stop(struct qcom_q6v5 *q6v5)
> {
> int ret;
>
> - q6v5->running = false;
> -
> qcom_smem_state_update_bits(q6v5->state,
> BIT(q6v5->stop_bit), BIT(q6v5->stop_bit));
>
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
^ permalink raw reply [relevance 0%]
* Re: [PATCH v2] remoteproc: qcom: pas: Add QCS404 remoteprocs
2018-09-28 6:27 13% ` Sibi Sankar
@ 2018-10-06 6:38 0% ` Bjorn Andersson
0 siblings, 0 replies; 200+ results
From: Bjorn Andersson @ 2018-10-06 6:38 UTC (permalink / raw)
To: Sibi Sankar
Cc: Ohad Ben-Cohen, Rob Herring, Mark Rutland, linux-remoteproc,
devicetree, linux-kernel, linux-kernel-owner
On Thu 27 Sep 23:27 PDT 2018, Sibi Sankar wrote:
> On 2018-09-28 00:33, Bjorn Andersson wrote:
> > Add compatibles for the three PAS based remote processors found in
> > QCS404.
> >
> > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> > ---
> >
>
> Reviewed-by: Sibi Sankar <sibis@codeaurora.org>
>
Thanks for the review Sibi, applied the patch.
Regards,
Bjorn
> > Changes since v1:
> > - Fixed incorrect sysmon_name, as pointed out by Sibi.
> >
> > .../devicetree/bindings/remoteproc/qcom,adsp.txt | 3 +++
> > drivers/remoteproc/qcom_adsp_pil.c | 12 ++++++++++++
> > 2 files changed, 15 insertions(+)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.txt
> > b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.txt
> > index b7d058228185..9c0cff3a5ed8 100644
> > --- a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.txt
> > +++ b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.txt
> > @@ -10,6 +10,9 @@ on the Qualcomm ADSP Hexagon core.
> > "qcom,msm8974-adsp-pil"
> > "qcom,msm8996-adsp-pil"
> > "qcom,msm8996-slpi-pil"
> > + "qcom,qcs404-adsp-pas"
> > + "qcom,qcs404-cdsp-pas"
> > + "qcom,qcs404-wcss-pas"
> > "qcom,sdm845-adsp-pas"
> > "qcom,sdm845-cdsp-pas"
> >
> > diff --git a/drivers/remoteproc/qcom_adsp_pil.c
> > b/drivers/remoteproc/qcom_adsp_pil.c
> > index da2254ea1135..d5e58235e83a 100644
> > --- a/drivers/remoteproc/qcom_adsp_pil.c
> > +++ b/drivers/remoteproc/qcom_adsp_pil.c
> > @@ -362,10 +362,22 @@ static const struct adsp_data slpi_resource_init =
> > {
> > .ssctl_id = 0x16,
> > };
> >
> > +static const struct adsp_data wcss_resource_init = {
> > + .crash_reason_smem = 421,
> > + .firmware_name = "wcnss.mdt",
> > + .pas_id = 6,
> > + .ssr_name = "mpss",
> > + .sysmon_name = "wcnss",
> > + .ssctl_id = 0x12,
> > +};
> > +
> > static const struct of_device_id adsp_of_match[] = {
> > { .compatible = "qcom,msm8974-adsp-pil", .data = &adsp_resource_init},
> > { .compatible = "qcom,msm8996-adsp-pil", .data = &adsp_resource_init},
> > { .compatible = "qcom,msm8996-slpi-pil", .data = &slpi_resource_init},
> > + { .compatible = "qcom,qcs404-adsp-pas", .data = &adsp_resource_init },
> > + { .compatible = "qcom,qcs404-cdsp-pas", .data = &cdsp_resource_init },
> > + { .compatible = "qcom,qcs404-wcss-pas", .data = &wcss_resource_init },
> > { .compatible = "qcom,sdm845-adsp-pas", .data = &adsp_resource_init},
> > { .compatible = "qcom,sdm845-cdsp-pas", .data = &cdsp_resource_init},
> > { },
>
> --
> -- Sibi Sankar --
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
> a Linux Foundation Collaborative Project.
^ permalink raw reply [relevance 0%]
* Re: [PATCH] remoteproc: qcom: q6v5: Propagate EPROBE_DEFER
2018-09-25 6:50 13% ` Sibi Sankar
@ 2018-10-06 6:39 0% ` Bjorn Andersson
0 siblings, 0 replies; 200+ results
From: Bjorn Andersson @ 2018-10-06 6:39 UTC (permalink / raw)
To: Sibi Sankar
Cc: Ohad Ben-Cohen, linux-remoteproc, linux-kernel, linux-arm-msm,
stable, linux-arm-msm-owner
On Mon 24 Sep 23:50 PDT 2018, Sibi Sankar wrote:
> On 2018-09-20 07:21, Bjorn Andersson wrote:
> > In the case that the interrupts fail to result because of the
> > interrupt-controller not yet being registered the
> > platform_get_irq_byname() call will fail with -EPROBE_DEFER, but passing
> > this into devm_request_threaded_irq() will result in -EINVAL being
> > returned, the driver is therefor not reprobed later.
> >
>
> The patch looks fine.
> Reviewed-by: Sibi Sankar <sibis@codeaurora.org>
>
Thanks for the review Sibi, applied the patch.
Regards,
Bjorn
> > Fixes: 3b415c8fb263 ("remoteproc: q6v5: Extract common resource
> > handling")
> > Cc: stable@vger.kernel.org
> > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> > ---
> > drivers/remoteproc/qcom_q6v5.c | 12 ++++++++++++
> > 1 file changed, 12 insertions(+)
> >
> > diff --git a/drivers/remoteproc/qcom_q6v5.c
> > b/drivers/remoteproc/qcom_q6v5.c
> > index 61a760ee4aac..e9ab90c19304 100644
> > --- a/drivers/remoteproc/qcom_q6v5.c
> > +++ b/drivers/remoteproc/qcom_q6v5.c
> > @@ -198,6 +198,9 @@ int qcom_q6v5_init(struct qcom_q6v5 *q6v5, struct
> > platform_device *pdev,
> > }
> >
> > q6v5->fatal_irq = platform_get_irq_byname(pdev, "fatal");
> > + if (q6v5->fatal_irq == -EPROBE_DEFER)
> > + return -EPROBE_DEFER;
> > +
> > ret = devm_request_threaded_irq(&pdev->dev, q6v5->fatal_irq,
> > NULL, q6v5_fatal_interrupt,
> > IRQF_TRIGGER_RISING | IRQF_ONESHOT,
> > @@ -208,6 +211,9 @@ int qcom_q6v5_init(struct qcom_q6v5 *q6v5, struct
> > platform_device *pdev,
> > }
> >
> > q6v5->ready_irq = platform_get_irq_byname(pdev, "ready");
> > + if (q6v5->ready_irq == -EPROBE_DEFER)
> > + return -EPROBE_DEFER;
> > +
> > ret = devm_request_threaded_irq(&pdev->dev, q6v5->ready_irq,
> > NULL, q6v5_ready_interrupt,
> > IRQF_TRIGGER_RISING | IRQF_ONESHOT,
> > @@ -218,6 +224,9 @@ int qcom_q6v5_init(struct qcom_q6v5 *q6v5, struct
> > platform_device *pdev,
> > }
> >
> > q6v5->handover_irq = platform_get_irq_byname(pdev, "handover");
> > + if (q6v5->handover_irq == -EPROBE_DEFER)
> > + return -EPROBE_DEFER;
> > +
> > ret = devm_request_threaded_irq(&pdev->dev, q6v5->handover_irq,
> > NULL, q6v5_handover_interrupt,
> > IRQF_TRIGGER_RISING | IRQF_ONESHOT,
> > @@ -229,6 +238,9 @@ int qcom_q6v5_init(struct qcom_q6v5 *q6v5, struct
> > platform_device *pdev,
> > disable_irq(q6v5->handover_irq);
> >
> > q6v5->stop_irq = platform_get_irq_byname(pdev, "stop-ack");
> > + if (q6v5->stop_irq == -EPROBE_DEFER)
> > + return -EPROBE_DEFER;
> > +
> > ret = devm_request_threaded_irq(&pdev->dev, q6v5->stop_irq,
> > NULL, q6v5_stop_interrupt,
> > IRQF_TRIGGER_RISING | IRQF_ONESHOT,
>
> --
> -- Sibi Sankar --
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
> a Linux Foundation Collaborative Project.
^ permalink raw reply [relevance 0%]
* Re: [PATCH v3 1/6] remoteproc: Introduce custom dump function for each remoteproc segment
2018-07-27 15:19 20% ` [PATCH v3 1/6] remoteproc: Introduce custom dump function for each remoteproc segment Sibi Sankar
2018-08-07 6:15 0% ` Vinod
@ 2018-10-08 6:23 0% ` Bjorn Andersson
2018-10-09 16:08 6% ` Sibi Sankar
1 sibling, 1 reply; 200+ results
From: Bjorn Andersson @ 2018-10-08 6:23 UTC (permalink / raw)
To: Sibi Sankar
Cc: linux-remoteproc, linux-kernel, ohad, kyan, sricharan, akdwived,
linux-arm-msm, tsoni
On Fri 27 Jul 08:19 PDT 2018, Sibi Sankar wrote:
> Introduce custom dump function per remoteproc segment. It is responsible
> for filling the device memory segment associated with coredump
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
> drivers/remoteproc/remoteproc_core.c | 15 ++++++++++-----
> include/linux/remoteproc.h | 3 +++
> 2 files changed, 13 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/remoteproc/remoteproc_core.c b/drivers/remoteproc/remoteproc_core.c
> index 283b258f5e0f..ec56cd822b26 100644
> --- a/drivers/remoteproc/remoteproc_core.c
> +++ b/drivers/remoteproc/remoteproc_core.c
> @@ -1183,13 +1183,18 @@ static void rproc_coredump(struct rproc *rproc)
> phdr->p_align = 0;
>
> ptr = rproc_da_to_va(rproc, segment->da, segment->size);
> - if (!ptr) {
> - dev_err(&rproc->dev,
> +
> + if (segment->dump) {
> + segment->dump(rproc, ptr, segment->size, data + offset);
rproc_da_to_va() is an exported symbol, so if you pass segment to the
dump function the driver can, if it needs to, call the function itself.
A typical use case, that I see, is to use the custom dump function to
write out CPU or hardware state to the dump file, in which case the "da"
won't be valid.
So please make this call dump(rproc, segment, data + offset) and move
the rproc_da_to_va() into the else block.
> + } else {
> + if (!ptr) {
> + dev_err(&rproc->dev,
> "invalid coredump segment (%pad, %zu)\n",
> &segment->da, segment->size);
> - memset(data + offset, 0xff, segment->size);
> - } else {
> - memcpy(data + offset, ptr, segment->size);
> + memset(data + offset, 0xff, segment->size);
> + } else {
> + memcpy(data + offset, ptr, segment->size);
> + }
> }
>
> offset += phdr->p_filesz;
> diff --git a/include/linux/remoteproc.h b/include/linux/remoteproc.h
> index e3c5d856b6da..0fbb01a9955c 100644
> --- a/include/linux/remoteproc.h
> +++ b/include/linux/remoteproc.h
> @@ -399,6 +399,8 @@ enum rproc_crash_type {
> * @node: list node related to the rproc segment list
> * @da: device address of the segment
> * @size: size of the segment
> + * @dump: custom dump function to fill device memory segment associated
> + * with coredump
> */
> struct rproc_dump_segment {
> struct list_head node;
> @@ -406,6 +408,7 @@ struct rproc_dump_segment {
> dma_addr_t da;
> size_t size;
>
> + void (*dump)(struct rproc *rproc, void *ptr, size_t len, void *priv);
"priv" isn't the best name to represent the memory to which you expect
dump to write to. Please call it "dest".
> loff_t offset;
> };
Regards,
Bjorn
^ permalink raw reply [relevance 0%]
* Re: [PATCH v3 5/6] remoteproc: qcom: q6v5-pil: Register segments/dumpfn for coredump
2018-07-27 15:20 20% ` [PATCH v3 5/6] remoteproc: qcom: q6v5-pil: Register segments/dumpfn for coredump Sibi Sankar
@ 2018-10-08 6:48 0% ` Bjorn Andersson
2018-10-09 16:21 6% ` Sibi Sankar
0 siblings, 1 reply; 200+ results
From: Bjorn Andersson @ 2018-10-08 6:48 UTC (permalink / raw)
To: Sibi Sankar
Cc: linux-remoteproc, linux-kernel, ohad, kyan, sricharan, akdwived,
linux-arm-msm, tsoni
On Fri 27 Jul 08:20 PDT 2018, Sibi Sankar wrote:
> Register the MDT segments and custom dumpfn with the remoteproc core
> dump functionality.
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
> drivers/remoteproc/qcom_q6v5_pil.c | 40 ++++++++++++++++++++++++++++++
> 1 file changed, 40 insertions(+)
>
> diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
> index ac3342f9ea5a..22bb049c3e7f 100644
> --- a/drivers/remoteproc/qcom_q6v5_pil.c
> +++ b/drivers/remoteproc/qcom_q6v5_pil.c
> @@ -1058,10 +1058,50 @@ static void *q6v5_da_to_va(struct rproc *rproc, u64 da, int len)
> return qproc->mpss_region + offset;
> }
>
> +static int qcom_q6v5_register_dump_segments(struct rproc *rproc,
> + const struct firmware *fw_unused)
How about naming it mba_fw instead of unused? Just as unused, but easier
to understand why it isn't used.
> +{
> + const struct firmware *fw;
> + const struct elf32_phdr *phdrs;
> + const struct elf32_phdr *phdr;
> + const struct elf32_hdr *ehdr;
> + struct q6v5 *qproc = (struct q6v5 *)rproc->priv;
No need for an explicit typecast from void *.
The rest looks good!
Regards,
Bjorn
^ permalink raw reply [relevance 0%]
* Re: [PATCH v3 6/6] remoteproc: qcom: q6v5-pil: Assign the relocated address
2018-07-27 15:20 21% ` [PATCH v3 6/6] remoteproc: qcom: q6v5-pil: Assign the relocated address Sibi Sankar
@ 2018-10-08 6:55 0% ` Bjorn Andersson
0 siblings, 0 replies; 200+ results
From: Bjorn Andersson @ 2018-10-08 6:55 UTC (permalink / raw)
To: Sibi Sankar
Cc: linux-remoteproc, linux-kernel, ohad, kyan, sricharan, akdwived,
linux-arm-msm, tsoni
On Fri 27 Jul 08:20 PDT 2018, Sibi Sankar wrote:
> Assign the relocated base of the modem image, as the offsets
> from the virtual memory might not be based on the physical
> address.
>
In order to get this merged before the first call to rproc_da_to_va() I
applied this patch to rproc-next.
Thanks,
Bjorn
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
> drivers/remoteproc/qcom_q6v5_pil.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
> index 22bb049c3e7f..b1296d614b8b 100644
> --- a/drivers/remoteproc/qcom_q6v5_pil.c
> +++ b/drivers/remoteproc/qcom_q6v5_pil.c
> @@ -862,6 +862,7 @@ static int q6v5_mpss_load(struct q6v5 *qproc)
> }
>
> mpss_reloc = relocate ? min_addr : qproc->mpss_phys;
> + qproc->mpss_reloc = mpss_reloc;
> /* Load firmware segments */
> for (i = 0; i < ehdr->e_phnum; i++) {
> phdr = &phdrs[i];
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
^ permalink raw reply [relevance 0%]
* Re: [PATCH v3 1/6] remoteproc: Introduce custom dump function for each remoteproc segment
2018-10-08 6:23 0% ` Bjorn Andersson
@ 2018-10-09 16:08 6% ` Sibi Sankar
0 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2018-10-09 16:08 UTC (permalink / raw)
To: Bjorn Andersson
Cc: linux-remoteproc, linux-kernel, ohad, kyan, sricharan, akdwived,
linux-arm-msm, tsoni, linux-remoteproc-owner
Hi Bjorn,
Thanks for the review :)
On 2018-10-08 11:53, Bjorn Andersson wrote:
> On Fri 27 Jul 08:19 PDT 2018, Sibi Sankar wrote:
>
>> Introduce custom dump function per remoteproc segment. It is
>> responsible
>> for filling the device memory segment associated with coredump
>>
>> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
>> ---
>> drivers/remoteproc/remoteproc_core.c | 15 ++++++++++-----
>> include/linux/remoteproc.h | 3 +++
>> 2 files changed, 13 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/remoteproc/remoteproc_core.c
>> b/drivers/remoteproc/remoteproc_core.c
>> index 283b258f5e0f..ec56cd822b26 100644
>> --- a/drivers/remoteproc/remoteproc_core.c
>> +++ b/drivers/remoteproc/remoteproc_core.c
>> @@ -1183,13 +1183,18 @@ static void rproc_coredump(struct rproc
>> *rproc)
>> phdr->p_align = 0;
>>
>> ptr = rproc_da_to_va(rproc, segment->da, segment->size);
>> - if (!ptr) {
>> - dev_err(&rproc->dev,
>> +
>> + if (segment->dump) {
>> + segment->dump(rproc, ptr, segment->size, data + offset);
>
> rproc_da_to_va() is an exported symbol, so if you pass segment to the
> dump function the driver can, if it needs to, call the function itself.
>
> A typical use case, that I see, is to use the custom dump function to
> write out CPU or hardware state to the dump file, in which case the
> "da"
> won't be valid.
>
>
> So please make this call dump(rproc, segment, data + offset) and move
> the rproc_da_to_va() into the else block.
>
yup will redefine it.
>> + } else {
>> + if (!ptr) {
>> + dev_err(&rproc->dev,
>> "invalid coredump segment (%pad, %zu)\n",
>> &segment->da, segment->size);
>> - memset(data + offset, 0xff, segment->size);
>> - } else {
>> - memcpy(data + offset, ptr, segment->size);
>> + memset(data + offset, 0xff, segment->size);
>> + } else {
>> + memcpy(data + offset, ptr, segment->size);
>> + }
>> }
>>
>> offset += phdr->p_filesz;
>> diff --git a/include/linux/remoteproc.h b/include/linux/remoteproc.h
>> index e3c5d856b6da..0fbb01a9955c 100644
>> --- a/include/linux/remoteproc.h
>> +++ b/include/linux/remoteproc.h
>> @@ -399,6 +399,8 @@ enum rproc_crash_type {
>> * @node: list node related to the rproc segment list
>> * @da: device address of the segment
>> * @size: size of the segment
>> + * @dump: custom dump function to fill device memory segment
>> associated
>> + * with coredump
>> */
>> struct rproc_dump_segment {
>> struct list_head node;
>> @@ -406,6 +408,7 @@ struct rproc_dump_segment {
>> dma_addr_t da;
>> size_t size;
>>
>> + void (*dump)(struct rproc *rproc, void *ptr, size_t len, void
>> *priv);
>
> "priv" isn't the best name to represent the memory to which you expect
> dump to write to. Please call it "dest".
>
will rename it
>> loff_t offset;
>> };
>
> Regards,
> Bjorn
--
-- Sibi Sankar --
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
^ permalink raw reply [relevance 6%]
* Re: [PATCH v3 4/6] remoteproc: qcom: q6v5-pil: Add custom dump function for modem
@ 2018-10-09 16:19 6% ` Sibi Sankar
0 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2018-10-09 16:19 UTC (permalink / raw)
To: Bjorn Andersson
Cc: linux-remoteproc, linux-kernel, ohad, kyan, sricharan, akdwived,
linux-arm-msm, tsoni
Hi Bjorn,
Thanks for the review !
On 2018-10-08 12:15, Bjorn Andersson wrote:
> On Fri 27 Jul 08:20 PDT 2018, Sibi Sankar wrote:
>> diff --git a/drivers/remoteproc/qcom_q6v5_pil.c
>> b/drivers/remoteproc/qcom_q6v5_pil.c
> [..]
>> +static void qcom_q6v5_dump_segment(struct rproc *rproc, void *ptr,
>> size_t len,
>> + void *priv)
>> +{
>> + int ret = 0;
>> + struct q6v5 *qproc = (struct q6v5 *)rproc->priv;
>> + static u32 pending_mask;
>
> I dislike that this is a static variable. And it tracks the segments
> that has already been dumped, i.e. the !pending.
>
>> +
>> + /* Unlock mba before copying segments */
>> + if (!qproc->mba_loaded)
>> + ret = q6v5_mba_load(qproc);
>> +
>> + if (!ptr || ret)
>> + memset(priv, 0xff, len);
>> + else
>> + memcpy(priv, ptr, len);
>> +
>> + pending_mask++;
>
> This is a "count" and not a "mask".
>
will rename it to count in the next re-spin. We can implement this as
a mask as well, the only disadvantage I see in that case is the need
for another flag to determine if mba is loaded since the mask for the
first segment may not be zero (the first segment may not be valid).
> I can see a few different cases where one would like to be able to pass
> custom data/information from the segment-registration to the dump
> function. So how about adding a "void *priv" to the dump segment.
>
> For this particular case we could typecast segment->priv to an unsigned
> long (as this is always the same size) and use that as a bitmask, which
> we use to update pending_mask.
>
sure will do the same
>> + if (pending_mask == qproc->valid_mask) {
>> + if (qproc->mba_loaded)
>> + q6v5_mba_reclaim(qproc);
>> + pending_mask = 0;
>> + }
>
> I think it would be cleaner to reset pending_mask in the start
> function,
> and then return early in this function when we have dumped all the
> segments.
>
> If so can pending_mask == 0 and pending_mask == all be the triggers for
> loading and reclaiming the mba? So we don't have two different trackers
> for this?
>
with the private data stored per dump segment this becomes much simpler
:)
>> +}
>> +
>
> Regards,
> Bjorn
--
-- Sibi Sankar --
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
^ permalink raw reply [relevance 6%]
* Re: [PATCH v3 5/6] remoteproc: qcom: q6v5-pil: Register segments/dumpfn for coredump
2018-10-08 6:48 0% ` Bjorn Andersson
@ 2018-10-09 16:21 6% ` Sibi Sankar
0 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2018-10-09 16:21 UTC (permalink / raw)
To: Bjorn Andersson
Cc: linux-remoteproc, linux-kernel, ohad, kyan, sricharan, akdwived,
linux-arm-msm, tsoni
Hi Bjorn,
Thanks for the review !
On 2018-10-08 12:18, Bjorn Andersson wrote:
> On Fri 27 Jul 08:20 PDT 2018, Sibi Sankar wrote:
>
>> Register the MDT segments and custom dumpfn with the remoteproc core
>> dump functionality.
>>
>> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
>> ---
>> drivers/remoteproc/qcom_q6v5_pil.c | 40
>> ++++++++++++++++++++++++++++++
>> 1 file changed, 40 insertions(+)
>>
>> diff --git a/drivers/remoteproc/qcom_q6v5_pil.c
>> b/drivers/remoteproc/qcom_q6v5_pil.c
>> index ac3342f9ea5a..22bb049c3e7f 100644
>> --- a/drivers/remoteproc/qcom_q6v5_pil.c
>> +++ b/drivers/remoteproc/qcom_q6v5_pil.c
>> @@ -1058,10 +1058,50 @@ static void *q6v5_da_to_va(struct rproc
>> *rproc, u64 da, int len)
>> return qproc->mpss_region + offset;
>> }
>>
>> +static int qcom_q6v5_register_dump_segments(struct rproc *rproc,
>> + const struct firmware *fw_unused)
>
> How about naming it mba_fw instead of unused? Just as unused, but
> easier
> to understand why it isn't used.
>
sure
>> +{
>> + const struct firmware *fw;
>> + const struct elf32_phdr *phdrs;
>> + const struct elf32_phdr *phdr;
>> + const struct elf32_hdr *ehdr;
>> + struct q6v5 *qproc = (struct q6v5 *)rproc->priv;
>
> No need for an explicit typecast from void *.
>
will remove it
> The rest looks good!
>
> Regards,
> Bjorn
--
-- Sibi Sankar --
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
^ permalink raw reply [relevance 6%]
* [PATCH v4 0/5] Add coredump support for Q6v5 Modem remoteproc
@ 2018-10-09 16:23 14% Sibi Sankar
2018-10-09 16:23 20% ` [PATCH v4 1/5] remoteproc: Introduce custom dump function for each remoteproc segment Sibi Sankar
` (4 more replies)
0 siblings, 5 replies; 200+ results
From: Sibi Sankar @ 2018-10-09 16:23 UTC (permalink / raw)
To: bjorn.andersson, ohad
Cc: linux-remoteproc, linux-kernel, linux-arm-msm, tsoni, sricharan,
akdwived, kyan, Sibi Sankar
This patch series add coredump support for modem on SDM845, MSM8996
and MSM8916 SoCs. Modem requires the mba to be loaded before a
coredump can be performed and this is achieved using a custom per
segment dump function.
V4:
Addressed Bjorn's comments.
V3:
[bjorn]:replace prepare/unprepare ops with a more generalised per segment
dump function
V2:
Introduce prepare/unprepare ops for rproc coredump
Sibi Sankar (5):
remoteproc: Introduce custom dump function for each remoteproc segment
remoteproc: Add mechanism for custom dump function assignment
remoteproc: qcom: q6v5-mss: Refactor mba load/unload sequence
remoteproc: qcom: q6v5-mss: Add custom dump function for modem
remoteproc: qcom: q6v5-mss: Register segments/dumpfn for coredump
drivers/remoteproc/qcom_q6v5_mss.c | 307 ++++++++++++++++++---------
drivers/remoteproc/remoteproc_core.c | 55 ++++-
include/linux/remoteproc.h | 11 +
3 files changed, 268 insertions(+), 105 deletions(-)
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [relevance 14%]
* [PATCH v4 1/5] remoteproc: Introduce custom dump function for each remoteproc segment
2018-10-09 16:23 14% [PATCH v4 0/5] Add coredump support for Q6v5 Modem remoteproc Sibi Sankar
@ 2018-10-09 16:23 20% ` Sibi Sankar
2018-10-09 16:23 19% ` [PATCH v4 2/5] remoteproc: Add mechanism for custom dump function assignment Sibi Sankar
` (3 subsequent siblings)
4 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2018-10-09 16:23 UTC (permalink / raw)
To: bjorn.andersson, ohad
Cc: linux-remoteproc, linux-kernel, linux-arm-msm, tsoni, sricharan,
akdwived, kyan, Sibi Sankar
Introduce custom dump function and private data per remoteproc dump
segment. The dump function is responsible for filling the device memory
segment associated with coredump
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
drivers/remoteproc/remoteproc_core.c | 16 ++++++++++------
include/linux/remoteproc.h | 6 ++++++
2 files changed, 16 insertions(+), 6 deletions(-)
diff --git a/drivers/remoteproc/remoteproc_core.c b/drivers/remoteproc/remoteproc_core.c
index aa6206706fe3..afa4274b6ccd 100644
--- a/drivers/remoteproc/remoteproc_core.c
+++ b/drivers/remoteproc/remoteproc_core.c
@@ -1183,14 +1183,18 @@ static void rproc_coredump(struct rproc *rproc)
phdr->p_flags = PF_R | PF_W | PF_X;
phdr->p_align = 0;
- ptr = rproc_da_to_va(rproc, segment->da, segment->size);
- if (!ptr) {
- dev_err(&rproc->dev,
+ if (segment->dump) {
+ segment->dump(rproc, segment, data + offset);
+ } else {
+ ptr = rproc_da_to_va(rproc, segment->da, segment->size);
+ if (!ptr) {
+ dev_err(&rproc->dev,
"invalid coredump segment (%pad, %zu)\n",
&segment->da, segment->size);
- memset(data + offset, 0xff, segment->size);
- } else {
- memcpy(data + offset, ptr, segment->size);
+ memset(data + offset, 0xff, segment->size);
+ } else {
+ memcpy(data + offset, ptr, segment->size);
+ }
}
offset += phdr->p_filesz;
diff --git a/include/linux/remoteproc.h b/include/linux/remoteproc.h
index e3c5d856b6da..2a93e102d2ad 100644
--- a/include/linux/remoteproc.h
+++ b/include/linux/remoteproc.h
@@ -399,6 +399,9 @@ enum rproc_crash_type {
* @node: list node related to the rproc segment list
* @da: device address of the segment
* @size: size of the segment
+ * @priv: private data associated with the dump_segment
+ * @dump: custom dump function to fill device memory segment associated
+ * with coredump
*/
struct rproc_dump_segment {
struct list_head node;
@@ -406,6 +409,9 @@ struct rproc_dump_segment {
dma_addr_t da;
size_t size;
+ void *priv;
+ void (*dump)(struct rproc *rproc, struct rproc_dump_segment *segment,
+ void *dest);
loff_t offset;
};
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 20%]
* [PATCH v4 2/5] remoteproc: Add mechanism for custom dump function assignment
2018-10-09 16:23 14% [PATCH v4 0/5] Add coredump support for Q6v5 Modem remoteproc Sibi Sankar
2018-10-09 16:23 20% ` [PATCH v4 1/5] remoteproc: Introduce custom dump function for each remoteproc segment Sibi Sankar
@ 2018-10-09 16:23 19% ` Sibi Sankar
2018-10-09 16:23 15% ` [PATCH v4 3/5] remoteproc: qcom: q6v5-mss: Refactor mba load/unload sequence Sibi Sankar
` (2 subsequent siblings)
4 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2018-10-09 16:23 UTC (permalink / raw)
To: bjorn.andersson, ohad
Cc: linux-remoteproc, linux-kernel, linux-arm-msm, tsoni, sricharan,
akdwived, kyan, Sibi Sankar
This patch adds a mechanism for assigning each rproc dump segment with
a custom dump function and private data. The dump function is to be
called for each rproc segment during coredump if assigned.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
drivers/remoteproc/remoteproc_core.c | 39 ++++++++++++++++++++++++++++
include/linux/remoteproc.h | 5 ++++
2 files changed, 44 insertions(+)
diff --git a/drivers/remoteproc/remoteproc_core.c b/drivers/remoteproc/remoteproc_core.c
index afa4274b6ccd..076579f44c3a 100644
--- a/drivers/remoteproc/remoteproc_core.c
+++ b/drivers/remoteproc/remoteproc_core.c
@@ -1121,6 +1121,45 @@ int rproc_coredump_add_segment(struct rproc *rproc, dma_addr_t da, size_t size)
}
EXPORT_SYMBOL(rproc_coredump_add_segment);
+/**
+ * rproc_coredump_add_custom_segment() - add segment of device memory to
+ * coredump and extend it with custom
+ * dump function
+ * @rproc: handle of a remote processor
+ * @da: device address
+ * @size: size of segment
+ * @priv: private data
+ * @dumpfn: custom dump function called for each segment during coredump
+ *
+ * Add device memory to the list of segments to be included in the coredump
+ * and associate the segment with the given custom dump function and private
+ * data.
+ *
+ * Return: 0 on success, negative errno on error.
+ */
+int rproc_coredump_add_custom_segment(struct rproc *rproc,
+ dma_addr_t da, size_t size, void *priv,
+ void (*dumpfn)(struct rproc *rproc,
+ struct rproc_dump_segment *segment,
+ void *dest))
+{
+ struct rproc_dump_segment *segment;
+
+ segment = kzalloc(sizeof(*segment), GFP_KERNEL);
+ if (!segment)
+ return -ENOMEM;
+
+ segment->da = da;
+ segment->size = size;
+ segment->priv = priv;
+ segment->dump = dumpfn;
+
+ list_add_tail(&segment->node, &rproc->dump_segments);
+
+ return 0;
+}
+EXPORT_SYMBOL(rproc_coredump_add_custom_segment);
+
/**
* rproc_coredump() - perform coredump
* @rproc: rproc handle
diff --git a/include/linux/remoteproc.h b/include/linux/remoteproc.h
index 2a93e102d2ad..0003b23ab117 100644
--- a/include/linux/remoteproc.h
+++ b/include/linux/remoteproc.h
@@ -563,6 +563,11 @@ int rproc_boot(struct rproc *rproc);
void rproc_shutdown(struct rproc *rproc);
void rproc_report_crash(struct rproc *rproc, enum rproc_crash_type type);
int rproc_coredump_add_segment(struct rproc *rproc, dma_addr_t da, size_t size);
+int rproc_coredump_add_custom_segment(struct rproc *rproc,
+ dma_addr_t da, size_t size, void *priv,
+ void (*dumpfn)(struct rproc *rproc,
+ struct rproc_dump_segment *segment,
+ void *dest));
static inline struct rproc_vdev *vdev_to_rvdev(struct virtio_device *vdev)
{
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 19%]
* [PATCH v4 3/5] remoteproc: qcom: q6v5-mss: Refactor mba load/unload sequence
2018-10-09 16:23 14% [PATCH v4 0/5] Add coredump support for Q6v5 Modem remoteproc Sibi Sankar
2018-10-09 16:23 20% ` [PATCH v4 1/5] remoteproc: Introduce custom dump function for each remoteproc segment Sibi Sankar
2018-10-09 16:23 19% ` [PATCH v4 2/5] remoteproc: Add mechanism for custom dump function assignment Sibi Sankar
@ 2018-10-09 16:23 15% ` Sibi Sankar
2018-10-09 16:23 20% ` [PATCH v4 4/5] remoteproc: qcom: q6v5-mss: Add custom dump function for modem Sibi Sankar
2018-10-09 16:23 20% ` [PATCH v4 5/5] remoteproc: qcom: q6v5-mss: Register segments/dumpfn for coredump Sibi Sankar
4 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2018-10-09 16:23 UTC (permalink / raw)
To: bjorn.andersson, ohad
Cc: linux-remoteproc, linux-kernel, linux-arm-msm, tsoni, sricharan,
akdwived, kyan, Sibi Sankar
Refactor re-useable parts of mba load/unload sequence into mba_load and
mba_reclaim respectively. This is done in order to prevent code duplication
for modem coredump, which requires the mba to be loaded before dumping
the segments. No change in functionality is intended.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
drivers/remoteproc/qcom_q6v5_mss.c | 239 +++++++++++++++++------------
1 file changed, 140 insertions(+), 99 deletions(-)
diff --git a/drivers/remoteproc/qcom_q6v5_mss.c b/drivers/remoteproc/qcom_q6v5_mss.c
index f52b64120877..c475af65ba1d 100644
--- a/drivers/remoteproc/qcom_q6v5_mss.c
+++ b/drivers/remoteproc/qcom_q6v5_mss.c
@@ -679,6 +679,143 @@ static bool q6v5_phdr_valid(const struct elf32_phdr *phdr)
return true;
}
+static int q6v5_mba_load(struct q6v5 *qproc)
+{
+ int ret;
+ int xfermemop_ret;
+
+ ret = q6v5_regulator_enable(qproc, qproc->proxy_regs,
+ qproc->proxy_reg_count);
+ if (ret) {
+ dev_err(qproc->dev, "failed to enable proxy supplies\n");
+ return ret;
+ }
+
+ ret = q6v5_clk_enable(qproc->dev, qproc->proxy_clks,
+ qproc->proxy_clk_count);
+ if (ret) {
+ dev_err(qproc->dev, "failed to enable proxy clocks\n");
+ goto disable_proxy_reg;
+ }
+
+ ret = q6v5_regulator_enable(qproc, qproc->active_regs,
+ qproc->active_reg_count);
+ if (ret) {
+ dev_err(qproc->dev, "failed to enable supplies\n");
+ goto disable_proxy_clk;
+ }
+
+ ret = q6v5_clk_enable(qproc->dev, qproc->reset_clks,
+ qproc->reset_clk_count);
+ if (ret) {
+ dev_err(qproc->dev, "failed to enable reset clocks\n");
+ goto disable_vdd;
+ }
+
+ ret = q6v5_reset_deassert(qproc);
+ if (ret) {
+ dev_err(qproc->dev, "failed to deassert mss restart\n");
+ goto disable_reset_clks;
+ }
+
+ ret = q6v5_clk_enable(qproc->dev, qproc->active_clks,
+ qproc->active_clk_count);
+ if (ret) {
+ dev_err(qproc->dev, "failed to enable clocks\n");
+ goto assert_reset;
+ }
+
+ /* Assign MBA image access in DDR to q6 */
+ ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true,
+ qproc->mba_phys, qproc->mba_size);
+ if (ret) {
+ dev_err(qproc->dev,
+ "assigning Q6 access to mba memory failed: %d\n", ret);
+ goto disable_active_clks;
+ }
+
+ writel(qproc->mba_phys, qproc->rmb_base + RMB_MBA_IMAGE_REG);
+
+ ret = q6v5proc_reset(qproc);
+ if (ret)
+ goto reclaim_mba;
+
+ ret = q6v5_rmb_mba_wait(qproc, 0, 5000);
+ if (ret == -ETIMEDOUT) {
+ dev_err(qproc->dev, "MBA boot timed out\n");
+ goto halt_axi_ports;
+ } else if (ret != RMB_MBA_XPU_UNLOCKED &&
+ ret != RMB_MBA_XPU_UNLOCKED_SCRIBBLED) {
+ dev_err(qproc->dev, "MBA returned unexpected status %d\n", ret);
+ ret = -EINVAL;
+ goto halt_axi_ports;
+ }
+
+ return 0;
+
+halt_axi_ports:
+ q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
+ q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
+ q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
+
+reclaim_mba:
+ xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, false,
+ qproc->mba_phys,
+ qproc->mba_size);
+ if (xfermemop_ret) {
+ dev_err(qproc->dev,
+ "Failed to reclaim mba buffer, system may become unstable\n");
+ }
+
+disable_active_clks:
+ q6v5_clk_disable(qproc->dev, qproc->active_clks,
+ qproc->active_clk_count);
+assert_reset:
+ q6v5_reset_assert(qproc);
+disable_reset_clks:
+ q6v5_clk_disable(qproc->dev, qproc->reset_clks,
+ qproc->reset_clk_count);
+disable_vdd:
+ q6v5_regulator_disable(qproc, qproc->active_regs,
+ qproc->active_reg_count);
+disable_proxy_clk:
+ q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
+ qproc->proxy_clk_count);
+disable_proxy_reg:
+ q6v5_regulator_disable(qproc, qproc->proxy_regs,
+ qproc->proxy_reg_count);
+
+ return ret;
+}
+
+static void q6v5_mba_reclaim(struct q6v5 *qproc)
+{
+ int xfermemop_ret;
+
+ q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
+ q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
+ q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
+ xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, false,
+ qproc->mba_phys,
+ qproc->mba_size);
+ if (xfermemop_ret) {
+ dev_err(qproc->dev,
+ "Failed to reclaim mba buffer, system may become unstable\n");
+ }
+
+ q6v5_clk_disable(qproc->dev, qproc->active_clks,
+ qproc->active_clk_count);
+ q6v5_reset_assert(qproc);
+ q6v5_clk_disable(qproc->dev, qproc->reset_clks,
+ qproc->reset_clk_count);
+ q6v5_regulator_disable(qproc, qproc->active_regs,
+ qproc->active_reg_count);
+ q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
+ qproc->proxy_clk_count);
+ q6v5_regulator_disable(qproc, qproc->proxy_regs,
+ qproc->proxy_reg_count);
+}
+
static int q6v5_mpss_load(struct q6v5 *qproc)
{
const struct elf32_phdr *phdrs;
@@ -803,72 +940,9 @@ static int q6v5_start(struct rproc *rproc)
qcom_q6v5_prepare(&qproc->q6v5);
- ret = q6v5_regulator_enable(qproc, qproc->proxy_regs,
- qproc->proxy_reg_count);
- if (ret) {
- dev_err(qproc->dev, "failed to enable proxy supplies\n");
- goto disable_irqs;
- }
-
- ret = q6v5_clk_enable(qproc->dev, qproc->proxy_clks,
- qproc->proxy_clk_count);
- if (ret) {
- dev_err(qproc->dev, "failed to enable proxy clocks\n");
- goto disable_proxy_reg;
- }
-
- ret = q6v5_regulator_enable(qproc, qproc->active_regs,
- qproc->active_reg_count);
- if (ret) {
- dev_err(qproc->dev, "failed to enable supplies\n");
- goto disable_proxy_clk;
- }
-
- ret = q6v5_clk_enable(qproc->dev, qproc->reset_clks,
- qproc->reset_clk_count);
- if (ret) {
- dev_err(qproc->dev, "failed to enable reset clocks\n");
- goto disable_vdd;
- }
-
- ret = q6v5_reset_deassert(qproc);
- if (ret) {
- dev_err(qproc->dev, "failed to deassert mss restart\n");
- goto disable_reset_clks;
- }
-
- ret = q6v5_clk_enable(qproc->dev, qproc->active_clks,
- qproc->active_clk_count);
- if (ret) {
- dev_err(qproc->dev, "failed to enable clocks\n");
- goto assert_reset;
- }
-
- /* Assign MBA image access in DDR to q6 */
- ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true,
- qproc->mba_phys, qproc->mba_size);
- if (ret) {
- dev_err(qproc->dev,
- "assigning Q6 access to mba memory failed: %d\n", ret);
- goto disable_active_clks;
- }
-
- writel(qproc->mba_phys, qproc->rmb_base + RMB_MBA_IMAGE_REG);
-
- ret = q6v5proc_reset(qproc);
+ ret = q6v5_mba_load(qproc);
if (ret)
- goto reclaim_mba;
-
- ret = q6v5_rmb_mba_wait(qproc, 0, 5000);
- if (ret == -ETIMEDOUT) {
- dev_err(qproc->dev, "MBA boot timed out\n");
- goto halt_axi_ports;
- } else if (ret != RMB_MBA_XPU_UNLOCKED &&
- ret != RMB_MBA_XPU_UNLOCKED_SCRIBBLED) {
- dev_err(qproc->dev, "MBA returned unexpected status %d\n", ret);
- ret = -EINVAL;
- goto halt_axi_ports;
- }
+ goto disable_irqs;
dev_info(qproc->dev, "MBA booted, loading mpss\n");
@@ -897,40 +971,7 @@ static int q6v5_start(struct rproc *rproc)
false, qproc->mpss_phys,
qproc->mpss_size);
WARN_ON(xfermemop_ret);
-
-halt_axi_ports:
- q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
- q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
- q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
-
-reclaim_mba:
- xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, false,
- qproc->mba_phys,
- qproc->mba_size);
- if (xfermemop_ret) {
- dev_err(qproc->dev,
- "Failed to reclaim mba buffer, system may become unstable\n");
- }
-
-disable_active_clks:
- q6v5_clk_disable(qproc->dev, qproc->active_clks,
- qproc->active_clk_count);
-
-assert_reset:
- q6v5_reset_assert(qproc);
-disable_reset_clks:
- q6v5_clk_disable(qproc->dev, qproc->reset_clks,
- qproc->reset_clk_count);
-disable_vdd:
- q6v5_regulator_disable(qproc, qproc->active_regs,
- qproc->active_reg_count);
-disable_proxy_clk:
- q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
- qproc->proxy_clk_count);
-disable_proxy_reg:
- q6v5_regulator_disable(qproc, qproc->proxy_regs,
- qproc->proxy_reg_count);
-
+ q6v5_mba_reclaim(qproc);
disable_irqs:
qcom_q6v5_unprepare(&qproc->q6v5);
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 15%]
* [PATCH v4 4/5] remoteproc: qcom: q6v5-mss: Add custom dump function for modem
2018-10-09 16:23 14% [PATCH v4 0/5] Add coredump support for Q6v5 Modem remoteproc Sibi Sankar
` (2 preceding siblings ...)
2018-10-09 16:23 15% ` [PATCH v4 3/5] remoteproc: qcom: q6v5-mss: Refactor mba load/unload sequence Sibi Sankar
@ 2018-10-09 16:23 20% ` Sibi Sankar
2018-10-09 16:23 20% ` [PATCH v4 5/5] remoteproc: qcom: q6v5-mss: Register segments/dumpfn for coredump Sibi Sankar
4 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2018-10-09 16:23 UTC (permalink / raw)
To: bjorn.andersson, ohad
Cc: linux-remoteproc, linux-kernel, linux-arm-msm, tsoni, sricharan,
akdwived, kyan, Sibi Sankar
The per segment dump function is responsible for loading the mba
before device memory segments associated with coredump can be populated
and for cleaning up the resources post coredump.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
drivers/remoteproc/qcom_q6v5_mss.c | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/drivers/remoteproc/qcom_q6v5_mss.c b/drivers/remoteproc/qcom_q6v5_mss.c
index c475af65ba1d..85db95bfd355 100644
--- a/drivers/remoteproc/qcom_q6v5_mss.c
+++ b/drivers/remoteproc/qcom_q6v5_mss.c
@@ -182,6 +182,7 @@ struct q6v5 {
struct qcom_sysmon *sysmon;
bool need_mem_protection;
bool has_alt_reset;
+ unsigned long dump_segment_cnt;
int mpss_perm;
int mba_perm;
int version;
@@ -932,6 +933,30 @@ static int q6v5_mpss_load(struct q6v5 *qproc)
return ret < 0 ? ret : 0;
}
+static void qcom_q6v5_dump_segment(struct rproc *rproc,
+ struct rproc_dump_segment *segment,
+ void *dest)
+{
+ int ret = 0;
+ struct q6v5 *qproc = rproc->priv;
+ unsigned long dump_cnt = (unsigned long)segment->priv;
+ void *ptr = rproc_da_to_va(rproc, segment->da, segment->size);
+
+ /* Unlock mba before copying segments */
+ if (!dump_cnt)
+ ret = q6v5_mba_load(qproc);
+
+ if (!ptr || ret)
+ memset(dest, 0xff, segment->size);
+ else
+ memcpy(dest, ptr, segment->size);
+
+ dump_cnt++;
+ /* Reclaim mba after copying segments */
+ if (dump_cnt == qproc->dump_segment_cnt)
+ q6v5_mba_reclaim(qproc);
+}
+
static int q6v5_start(struct rproc *rproc)
{
struct q6v5 *qproc = (struct q6v5 *)rproc->priv;
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 20%]
* [PATCH v4 5/5] remoteproc: qcom: q6v5-mss: Register segments/dumpfn for coredump
2018-10-09 16:23 14% [PATCH v4 0/5] Add coredump support for Q6v5 Modem remoteproc Sibi Sankar
` (3 preceding siblings ...)
2018-10-09 16:23 20% ` [PATCH v4 4/5] remoteproc: qcom: q6v5-mss: Add custom dump function for modem Sibi Sankar
@ 2018-10-09 16:23 20% ` Sibi Sankar
4 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2018-10-09 16:23 UTC (permalink / raw)
To: bjorn.andersson, ohad
Cc: linux-remoteproc, linux-kernel, linux-arm-msm, tsoni, sricharan,
akdwived, kyan, Sibi Sankar
Register the MDT segments, custom dumpfn and private data with the
remoteproc core dump functionality.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
drivers/remoteproc/qcom_q6v5_mss.c | 43 ++++++++++++++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/drivers/remoteproc/qcom_q6v5_mss.c b/drivers/remoteproc/qcom_q6v5_mss.c
index 85db95bfd355..bece5dd46bca 100644
--- a/drivers/remoteproc/qcom_q6v5_mss.c
+++ b/drivers/remoteproc/qcom_q6v5_mss.c
@@ -1065,10 +1065,53 @@ static void *q6v5_da_to_va(struct rproc *rproc, u64 da, int len)
return qproc->mpss_region + offset;
}
+static int qcom_q6v5_register_dump_segments(struct rproc *rproc,
+ const struct firmware *mba_fw)
+{
+ const struct firmware *fw;
+ const struct elf32_phdr *phdrs;
+ const struct elf32_phdr *phdr;
+ const struct elf32_hdr *ehdr;
+ struct q6v5 *qproc = rproc->priv;
+ unsigned long segment_cnt = 0;
+ int ret;
+ int i;
+
+ ret = request_firmware(&fw, "modem.mdt", qproc->dev);
+ if (ret < 0) {
+ dev_err(qproc->dev, "unable to load modem.mdt\n");
+ return ret;
+ }
+
+ ehdr = (struct elf32_hdr *)fw->data;
+ phdrs = (struct elf32_phdr *)(ehdr + 1);
+
+ for (i = 0; i < ehdr->e_phnum; i++) {
+ phdr = &phdrs[i];
+
+ if (!q6v5_phdr_valid(phdr))
+ continue;
+
+ ret = rproc_coredump_add_custom_segment(rproc, phdr->p_paddr,
+ phdr->p_memsz,
+ (void *)segment_cnt,
+ qcom_q6v5_dump_segment);
+ if (ret)
+ break;
+
+ segment_cnt++;
+ }
+
+ qproc->dump_segment_cnt = segment_cnt;
+ release_firmware(fw);
+ return ret;
+}
+
static const struct rproc_ops q6v5_ops = {
.start = q6v5_start,
.stop = q6v5_stop,
.da_to_va = q6v5_da_to_va,
+ .parse_fw = qcom_q6v5_register_dump_segments,
.load = q6v5_load,
};
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 20%]
* Re: [PATCH] remoteproc: qcom: q6v5-pil: add SCM probe dependency
@ 2018-10-09 17:21 6% ` Sibi Sankar
0 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2018-10-09 17:21 UTC (permalink / raw)
To: Brian Norris
Cc: Bjorn Andersson, Ohad Ben-Cohen, linux-remoteproc, linux-kernel,
linux-arm-msm, linux-soc
On 2018-10-09 22:32, Brian Norris wrote:
> On Mon, Oct 08, 2018 at 11:21:25PM -0700, Bjorn Andersson wrote:
>> On Mon 08 Oct 19:08 PDT 2018, Brian Norris wrote:
>>
>> > Similar to qcom_q6v5_pas and qcom_wcnss drivers, probe will fail if SCM
>> > is not up.
>> >
>>
>> Thanks Brian, this dependency was introduced with the memory ownership
>> support.
>
> That's a good point. I'm actually not that familiar with this
> particular
> driver--I was just trying to resolve an OOPS I saw while bringing this
> driver up--but that does look correct.
>
>> I applied it with an updated conditional to make it explicit that it
>> related to need_mem_protection, updated the commit message to describe
>> actual relationship to the memory protection mechanism and added a
>> Fixes: tag.
>
> Your version looks good, thanks.
>
>> Don't we also need to add the ability to disable need_mem_protection
>> when we're running ATF?
>
> I'm not sure exactly, but FWIW I'm running some form of ATF on SDM845
> and I'm running with 'needs_memory_protection' (hence, this patch).
>
AFAIK ATF will eventually support the hyp assign calls even though they
are just stubs as of now.
> Regards,
> Brian
--
-- Sibi Sankar --
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
^ permalink raw reply [relevance 6%]
* [PATCH v5 0/5] Add coredump support for Q6v5 Modem remoteproc
@ 2018-10-17 13:55 14% Sibi Sankar
2018-10-17 13:55 20% ` [PATCH v5 1/5] remoteproc: Introduce custom dump function for each remoteproc segment Sibi Sankar
0 siblings, 1 reply; 200+ results
From: Sibi Sankar @ 2018-10-17 13:55 UTC (permalink / raw)
To: bjorn.andersson, ohad
Cc: linux-remoteproc, linux-kernel, linux-arm-msm, tsoni, sricharan,
akdwived, kyan, Sibi Sankar
This patch series add coredump support for modem on SDM845, MSM8996
and MSM8916 SoCs. Modem requires the mba to be loaded before a
coredump can be performed and this is achieved using a custom per
segment dump function.
V5:
Add software bypass to avoid high MX current in mpss_load error path.
Remove the proxy votes of clk/regs only after the active/reset clks/regs.
Reclaim MBA memory after mpss_load failure in mba_reclaim func.
Revert to dump_fn to as done with v3 with a mask based approach.
V4:
Addressed Bjorn's comments.
V3:
[bjorn]:replace prepare/unprepare ops with a more generalised per segment
dump function
V2:
Introduce prepare/unprepare ops for rproc coredump
Sibi Sankar (5):
remoteproc: Introduce custom dump function for each remoteproc segment
remoteproc: Add mechanism for custom dump function assignment
remoteproc: qcom: q6v5-mss: Refactor mba load/unload sequence
remoteproc: qcom: q6v5-mss: Add custom dump function for modem
remoteproc: qcom: q6v5-mss: Register segments/dumpfn for coredump
drivers/remoteproc/qcom_q6v5_mss.c | 379 +++++++++++++++++----------
drivers/remoteproc/remoteproc_core.c | 55 +++-
include/linux/remoteproc.h | 11 +
3 files changed, 303 insertions(+), 142 deletions(-)
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [relevance 14%]
* [PATCH v5 1/5] remoteproc: Introduce custom dump function for each remoteproc segment
2018-10-17 13:55 14% [PATCH v5 0/5] Add coredump support for Q6v5 Modem remoteproc Sibi Sankar
@ 2018-10-17 13:55 20% ` Sibi Sankar
0 siblings, 0 replies; 200+ results
From: Sibi Sankar @ 2018-10-17 13:55 UTC (permalink / raw)
To: bjorn.andersson, ohad
Cc: linux-remoteproc, linux-kernel, linux-arm-msm, tsoni, sricharan,
akdwived, kyan, Sibi Sankar
Introduce custom dump function and private data per remoteproc dump
segment. The dump function is responsible for filling the device memory
segment associated with coredump
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
drivers/remoteproc/remoteproc_core.c | 16 ++++++++++------
include/linux/remoteproc.h | 6 ++++++
2 files changed, 16 insertions(+), 6 deletions(-)
diff --git a/drivers/remoteproc/remoteproc_core.c b/drivers/remoteproc/remoteproc_core.c
index aa6206706fe3..afa4274b6ccd 100644
--- a/drivers/remoteproc/remoteproc_core.c
+++ b/drivers/remoteproc/remoteproc_core.c
@@ -1183,14 +1183,18 @@ static void rproc_coredump(struct rproc *rproc)
phdr->p_flags = PF_R | PF_W | PF_X;
phdr->p_align = 0;
- ptr = rproc_da_to_va(rproc, segment->da, segment->size);
- if (!ptr) {
- dev_err(&rproc->dev,
+ if (segment->dump) {
+ segment->dump(rproc, segment, data + offset);
+ } else {
+ ptr = rproc_da_to_va(rproc, segment->da, segment->size);
+ if (!ptr) {
+ dev_err(&rproc->dev,
"invalid coredump segment (%pad, %zu)\n",
&segment->da, segment->size);
- memset(data + offset, 0xff, segment->size);
- } else {
- memcpy(data + offset, ptr, segment->size);
+ memset(data + offset, 0xff, segment->size);
+ } else {
+ memcpy(data + offset, ptr, segment->size);
+ }
}
offset += phdr->p_filesz;
diff --git a/include/linux/remoteproc.h b/include/linux/remoteproc.h
index e3c5d856b6da..2a93e102d2ad 100644
--- a/include/linux/remoteproc.h
+++ b/include/linux/remoteproc.h
@@ -399,6 +399,9 @@ enum rproc_crash_type {
* @node: list node related to the rproc segment list
* @da: device address of the segment
* @size: size of the segment
+ * @priv: private data associated with the dump_segment
+ * @dump: custom dump function to fill device memory segment associated
+ * with coredump
*/
struct rproc_dump_segment {
struct list_head node;
@@ -406,6 +409,9 @@ struct rproc_dump_segment {
dma_addr_t da;
size_t size;
+ void *priv;
+ void (*dump)(struct rproc *rproc, struct rproc_dump_segment *segment,
+ void *dest);
loff_t offset;
};
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [relevance 20%]
Results 1-200 of ~2000 next (newer) | reverse | options above
-- pct% links below jump to the message on this page, permalinks otherwise --
2018-03-02 9:23 13% [PATCH 0/6] Add support for remoteproc modem-pil on SDM845 SoCs sibis
2018-03-02 9:23 15% ` [PATCH 1/6] reset: qcom: AOSS (Always on subsystem) reset controller sibis
2018-03-02 10:30 0% ` Philipp Zabel
2018-03-05 6:47 6% ` Sibi S
2018-03-02 9:23 21% ` [PATCH 2/6] dt-bindings: mailbox: Add APCS global binding for SDM845 SoCs sibis
2018-03-02 9:23 21% ` [PATCH 3/6] mailbox: Add support for Qualcomm " sibis
2018-03-02 9:23 21% ` [PATCH 4/6] dt-bindings: remoteproc: Add Q6v5 Modem PIL binding for SDM845 sibis
2018-03-02 9:23 16% ` [PATCH 5/6] remoteproc: qcom: Add support for mss remoteproc on SDM845 sibis
2018-03-02 9:23 20% ` [PATCH 6/6] remoteproc: qcom: Reorder active clks enable and reset sibis
2018-03-05 9:53 13% [PATCH 0/6] Add support for remoteproc modem-pil on SDM845 SoCs sibis
2018-03-05 9:53 15% ` [PATCH 1/6] reset: qcom: AOSS (Always on subsystem) reset controller sibis
2018-03-07 21:35 0% ` Rob Herring
2018-03-09 14:55 6% ` Sibi S
2018-03-09 21:29 ` Trilok Soni
2018-03-12 7:01 6% ` Sibi S
2018-03-05 9:53 21% ` [PATCH 2/6] dt-bindings: mailbox: Add APCS global binding for SDM845 SoCs sibis
2018-03-07 21:55 0% ` Rob Herring
2018-03-05 9:53 21% ` [PATCH 3/6] mailbox: Add support for Qualcomm " sibis
2018-03-05 9:53 21% ` [PATCH 4/6] dt-bindings: remoteproc: Add Q6v5 Modem PIL binding for SDM845 sibis
2018-03-07 21:56 0% ` Rob Herring
2018-03-05 9:53 18% ` [PATCH 5/6] remoteproc: qcom: Add support for mss remoteproc on SDM845 sibis
2018-03-05 9:53 17% ` [PATCH 6/6] remoteproc: qcom: Always assert and deassert reset signals in SDM845 sibis
2018-03-14 9:21 11% [PATCH v3 0/7] Add support for remoteproc modem-pil on SDM845 SoCs Sibi S
2018-03-14 9:21 17% ` [PATCH v3 1/7] dt-bindings: reset: Add AOSS reset bindings for " Sibi S
2018-03-18 12:49 0% ` Rob Herring
2018-03-18 22:44 ` Bjorn Andersson
2018-03-21 6:29 6% ` Sibi S
2018-03-14 9:21 14% ` [PATCH v3 2/7] reset: qcom: AOSS (always on subsystem) reset controller Sibi S
2018-03-14 10:48 0% ` Vivek Gautam
2018-03-18 22:45 ` Bjorn Andersson
2018-03-22 22:32 6% ` Sibi S
2018-03-14 9:21 19% ` [PATCH v3 3/7] dt-bindings: mailbox: Add APCS global binding for SDM845 SoCs Sibi S
2018-03-18 22:45 0% ` Bjorn Andersson
2018-03-14 9:21 19% ` [PATCH v3 4/7] mailbox: Add support for Qualcomm " Sibi S
2018-03-18 22:45 0% ` Bjorn Andersson
2018-04-19 17:22 0% ` Bjorn Andersson
2018-03-14 9:21 19% ` [PATCH v3 5/7] dt-bindings: remoteproc: Add Q6v5 Modem PIL binding for SDM845 Sibi S
2018-03-18 22:46 0% ` Bjorn Andersson
2018-03-14 9:21 16% ` [PATCH v3 6/7] remoteproc: qcom: Add support for mss remoteproc on SDM845 Sibi S
2018-03-14 9:21 14% ` [PATCH v3 7/7] remoteproc: qcom: Always assert and deassert reset signals in SDM845 Sibi S
2018-03-18 22:46 ` Bjorn Andersson
2018-03-22 22:10 6% ` Sibi S
2018-04-25 14:38 21% [PATCH 1/3] dt-bindings: mailbox: Add APSS shared binding for SDM845 SoCs Sibi Sankar
2018-04-25 14:38 21% ` [PATCH 2/3] mailbox: Add support for Qualcomm " Sibi Sankar
2018-04-25 16:26 0% ` Bjorn Andersson
2018-04-25 14:38 21% ` [PATCH 3/3] arm64: dts: qcom: Add APSS shared mailbox node to SDM845 Sibi Sankar
2018-04-25 16:30 0% ` Bjorn Andersson
2018-04-25 16:26 0% ` [PATCH 1/3] dt-bindings: mailbox: Add APSS shared binding for SDM845 SoCs Bjorn Andersson
2018-05-01 14:28 0% ` Rob Herring
2018-04-25 14:46 20% [PATCH] arm64: dts: qcom: Add SDM845 SMEM nodes Sibi Sankar
2018-04-25 22:06 ` Bjorn Andersson
2018-04-26 14:25 6% ` Sibi S
2018-04-25 14:50 17% [PATCH] remoteproc: Proxy unvote clk/regs in handover context Sibi Sankar
2018-05-18 19:58 0% ` Bjorn Andersson
2018-05-21 16:49 6% ` Sibi S
2018-04-25 15:08 13% [PATCH v4 0/5] Add support for remoteproc modem-pil on SDM845 SoCs Sibi Sankar
2018-04-25 15:08 19% ` [PATCH v4 1/5] dt-bindings: reset: Add AOSS reset bindings for " Sibi Sankar
2018-04-27 10:24 0% ` Philipp Zabel
2018-04-27 10:45 6% ` Sibi S
2018-04-25 15:08 16% ` [PATCH v4 2/5] reset: qcom: AOSS (always on subsystem) reset controller Sibi Sankar
2018-04-27 10:41 0% ` Philipp Zabel
2018-04-27 11:15 6% ` Sibi S
2018-04-25 15:08 21% ` [PATCH v4 3/5] dt-bindings: remoteproc: Add Q6v5 Modem PIL binding for SDM845 Sibi Sankar
2018-04-27 14:32 0% ` Rob Herring
2018-04-25 15:08 18% ` [PATCH v4 4/5] remoteproc: qcom: Add support for mss remoteproc on SDM845 Sibi Sankar
2018-05-18 21:31 0% ` Bjorn Andersson
2018-05-21 16:51 6% ` Sibi S
2018-04-25 15:08 16% ` [PATCH v4 5/5] remoteproc: qcom: Always assert and deassert reset signals in SDM845 Sibi Sankar
2018-05-18 21:47 0% ` Bjorn Andersson
2018-05-21 16:57 6% ` Sibi S
2018-04-30 14:44 20% [PATCH v2] arm64: dts: qcom: Add SDM845 SMEM nodes Sibi Sankar
2018-05-01 0:20 0% ` Bjorn Andersson
2018-05-12 14:21 15% [PATCH] remoteproc: Introduce prepare/unprepare ops for rproc coredump Sibi Sankar
2018-05-21 17:27 13% [PATCH v5 0/8] Add support for remoteproc modem-pil on SDM845 SoCs Sibi Sankar
2018-05-21 17:27 19% ` [PATCH v5 1/8] dt-bindings: reset: Add AOSS reset bindings for " Sibi Sankar
2018-05-22 16:17 0% ` Rob Herring
2018-06-23 0:44 0% ` Bjorn Andersson
2018-06-27 14:24 6% ` Sibi S
2018-05-21 17:27 16% ` [PATCH v5 2/8] reset: qcom: AOSS (always on subsystem) reset controller Sibi Sankar
2018-06-23 0:46 0% ` Bjorn Andersson
2018-05-21 17:27 19% ` [PATCH v5 3/8] remoteproc: Move proxy unvote to handover irq handler Sibi Sankar
2018-05-22 4:35 0% ` Bjorn Andersson
2018-05-22 6:31 6% ` Sibi S
2018-05-21 17:27 17% ` [PATCH v5 4/8] remoteproc: Synchronize proxy unvote from multiple contexts Sibi Sankar
2018-05-21 17:27 21% ` [PATCH v5 5/8] dt-bindings: remoteproc: Add Q6v5 Modem PIL binding for SDM845 Sibi Sankar
2018-05-22 15:56 0% ` Rob Herring
2018-05-29 14:37 6% ` Sibi S
2018-05-29 15:45 6% ` Rob Herring
2018-05-21 17:27 20% ` [PATCH v5 6/8] remoteproc: qcom: Introduce reset assert/deassert helper functions Sibi Sankar
2018-05-21 17:27 15% ` [PATCH v5 7/8] remoteproc: qcom: Add support for mss remoteproc on SDM845 Sibi Sankar
2018-05-21 17:27 20% ` [PATCH v5 8/8] remoteproc: qcom: Allow defining GLINK edge for mss remoteproc Sibi Sankar
2018-05-21 18:45 15% [PATCH v2] remoteproc: Introduce prepare/unprepare ops for rproc coredump Sibi Sankar
2018-05-29 5:05 ` Bjorn Andersson
2018-05-29 14:06 6% ` Sibi S
2018-05-23 5:20 [RFC PATCH 0/5] Hexagon remoteproc spring cleaning Bjorn Andersson
2018-05-23 5:20 ` [RFC PATCH 2/5] remoteproc: q6v5: Extract common resource handling Bjorn Andersson
2018-06-01 6:16 ` Sricharan R
2018-06-01 15:18 6% ` Sibi S
2018-05-29 14:20 14% [PATCH v4 0/3] Cleanup excessive DSI host controller version checks Sibi Sankar
2018-05-29 14:20 20% ` [PATCH v4 1/3] drm/msm/dsi: add dsi host helper functions support Sibi Sankar
2018-05-29 14:20 13% ` [PATCH v4 2/3] drm/msm/dsi: add implementation for helper functions Sibi Sankar
2018-05-29 14:20 12% ` [PATCH v4 3/3] drm/msm/dsi: replace version checks with " Sibi Sankar
2018-05-29 14:41 21% [PATCH v5 5/8] dt-bindings: remoteproc: Add Q6v5 Modem PIL binding for SDM845 Sibi Sankar
2018-06-27 14:24 19% [PATCH v6 1/8] dt-bindings: reset: Add AOSS reset bindings for SDM845 SoCs Sibi Sankar
2018-06-27 14:24 17% ` [PATCH v6 2/8] reset: qcom: AOSS (always on subsystem) reset controller Sibi Sankar
2018-06-27 16:47 0% ` [PATCH v6 1/8] dt-bindings: reset: Add AOSS reset bindings for SDM845 SoCs Bjorn Andersson
2018-07-03 2:32 0% ` Rob Herring
2018-07-16 10:19 0% ` Philipp Zabel
2018-07-01 16:20 2% [PATCH 4.17 000/220] 4.17.4-stable review Greg Kroah-Hartman
2018-07-01 16:23 8% ` [PATCH 4.17 165/220] remoteproc: Prevent incorrect rproc state on xfer mem ownership failure Greg Kroah-Hartman
2018-07-09 15:12 20% [PATCH] remoteproc: qcom: q6v5-pil: fix modem hang on SDM845 after axis2 clk unvote Sibi Sankar
2018-07-10 21:09 0% ` Bjorn Andersson
2018-07-27 15:19 14% [PATCH v3 0/6] Add coredump support for Q6v5 Modem remoteproc Sibi Sankar
2018-07-27 15:19 20% ` [PATCH v3 1/6] remoteproc: Introduce custom dump function for each remoteproc segment Sibi Sankar
2018-08-07 6:15 0% ` Vinod
2018-08-08 14:10 6% ` Sibi Sankar
2018-10-08 6:23 0% ` Bjorn Andersson
2018-10-09 16:08 6% ` Sibi Sankar
2018-07-27 15:19 19% ` [PATCH v3 2/6] remoteproc: Add mechanism for custom dump function assignment Sibi Sankar
2018-07-27 15:20 15% ` [PATCH v3 3/6] remoteproc: qcom: q6v5-pil: Refactor mba load/unload sequence Sibi Sankar
2018-07-27 15:20 20% ` [PATCH v3 4/6] remoteproc: qcom: q6v5-pil: Add custom dump function for modem Sibi Sankar
2018-10-08 6:45 ` Bjorn Andersson
2018-10-09 16:19 6% ` Sibi Sankar
2018-07-27 15:20 20% ` [PATCH v3 5/6] remoteproc: qcom: q6v5-pil: Register segments/dumpfn for coredump Sibi Sankar
2018-10-08 6:48 0% ` Bjorn Andersson
2018-10-09 16:21 6% ` Sibi Sankar
2018-07-27 15:20 21% ` [PATCH v3 6/6] remoteproc: qcom: q6v5-pil: Assign the relocated address Sibi Sankar
2018-10-08 6:55 0% ` Bjorn Andersson
2018-07-27 15:28 19% [PATCH 1/4] dt-bindings: reset: Add PDC reset binding for SDM845 SoCs Sibi Sankar
2018-07-27 15:28 16% ` [PATCH 2/4] reset: qcom: PDC (Power Domain Controller) reset controller Sibi Sankar
2018-07-31 8:51 0% ` Philipp Zabel
2018-07-31 13:00 6% ` Sibi S
2018-08-21 22:17 0% ` Bjorn Andersson
2018-07-27 15:28 21% ` [PATCH 3/4] remoteproc: qcom: q6v5-pil: Explicitly get mss_restart line Sibi Sankar
2018-07-31 8:57 0% ` Philipp Zabel
2018-07-31 13:11 6% ` Sibi S
2018-07-27 15:28 19% ` [PATCH 4/4] remoteproc: qcom: q6v5-pil: Add PDC restart for modem on SDM845 SoCs Sibi Sankar
2018-07-31 8:54 0% ` Philipp Zabel
2018-07-31 13:13 6% ` Sibi S
2018-08-07 18:18 0% ` Rob Herring
2018-08-08 15:45 6% ` Sibi Sankar
2018-08-21 22:33 0% ` Bjorn Andersson
2018-07-31 8:42 0% ` [PATCH 1/4] dt-bindings: reset: Add PDC reset binding for " Philipp Zabel
2018-07-31 12:57 6% ` Sibi S
2018-08-07 18:16 0% ` Rob Herring
2018-08-08 15:44 6% ` Sibi Sankar
2018-08-08 21:37 0% ` Jordan Crouse
2018-08-08 22:48 0% ` Jordan Crouse
2018-08-21 22:08 0% ` Bjorn Andersson
2018-08-02 0:57 [PATCH v3 1/2] PM / devfreq: Generic CPU frequency to device frequency mapping governor Saravana Kannan
[not found] ` <CGME20180802005756epcas4p465a12f42a0e36f0af6fd276a3a56957f@epcms1p3>
2018-08-02 9:56 ` MyungJoo Ham
2018-08-02 21:00 ` skannan
2018-08-07 5:49 ` skannan
2018-09-10 18:45 6% ` Sibi Sankar
2018-08-02 0:57 [PATCH v3 2/2] PM / devfreq: Add devfreq driver for interconnect bandwidth voting Saravana Kannan
2018-08-23 13:00 ` Georgi Djakov
2018-09-10 18:55 6% ` Sibi Sankar
2018-09-14 12:53 6% ` Sibi Sankar
2018-08-24 13:18 13% [PATCH v2 0/6] Add support for PDC Global on SDM845 SoCs Sibi Sankar
2018-08-24 13:18 19% ` [PATCH v2 1/6] dt-bindings: reset: Add PDC Global binding for " Sibi Sankar
2018-08-28 0:33 0% ` Bjorn Andersson
2018-08-28 0:38 0% ` Matthias Kaehlcke
2018-08-28 6:08 6% ` sibis
2018-08-28 17:11 6% ` Matthias Kaehlcke
2018-08-29 0:43 0% ` Rob Herring
2018-08-24 13:18 16% ` [PATCH v2 2/6] reset: qcom: PDC Global (Power Domain Controller) reset controller Sibi Sankar
2018-08-28 0:22 0% ` Matthias Kaehlcke
2018-08-28 3:02 ` Bjorn Andersson
2018-08-28 7:11 6% ` Sibi Sankar
2018-08-24 13:18 21% ` [PATCH v2 3/6] dt-bindings: remoteproc: Remove additional definition tag Sibi Sankar
2018-08-28 0:44 0% ` Matthias Kaehlcke
2018-08-29 16:38 6% ` Sibi Sankar
2018-08-24 13:18 20% ` [PATCH v2 4/6] dt-bindings: remoteproc: Add PDC reset binding for Q6V5 PIL Sibi Sankar
2018-08-29 0:44 0% ` Rob Herring
2018-08-24 13:18 21% ` [PATCH v2 5/6] remoteproc: qcom: q6v5-pil: Explicitly get mss_restart line Sibi Sankar
2018-08-24 13:19 19% ` [PATCH v2 6/6] remoteproc: qcom: q6v5-pil: Add PDC reset for modem on SDM845 SoCs Sibi Sankar
2018-08-28 7:12 [PATCH] arm64: dts: qcom: sdm845: Add smp2p nodes Bjorn Andersson
2018-08-28 8:52 13% ` Sibi Sankar
2018-08-28 7:14 [PATCH] remoteproc: qcom: adsp: Add SDM845 ADSP and CDSP support Bjorn Andersson
2018-08-28 8:43 13% ` Sibi Sankar
2018-08-29 19:12 13% [PATCH v3 0/6] Add support for PDC Global on SDM845 SoCs Sibi Sankar
2018-08-29 19:12 19% ` [PATCH v3 1/6] dt-bindings: reset: Add PDC Global binding for " Sibi Sankar
2018-08-29 19:12 17% ` [PATCH v3 2/6] reset: qcom: PDC Global (Power Domain Controller) reset controller Sibi Sankar
2018-09-03 19:31 0% ` Bjorn Andersson
2018-08-29 19:12 21% ` [PATCH v3 3/6] dt-bindings: remoteproc: qcom: Remove additional definition tag Sibi Sankar
2018-09-03 19:32 0% ` Bjorn Andersson
2018-09-10 18:28 0% ` Rob Herring
2018-08-29 19:12 20% ` [PATCH v3 4/6] dt-bindings: remoteproc: Add PDC reset binding for Q6V5 PIL Sibi Sankar
2018-08-29 19:12 21% ` [PATCH v3 5/6] remoteproc: qcom: q6v5-pil: Explicitly get mss_restart line Sibi Sankar
2018-08-29 19:12 20% ` [PATCH v3 6/6] remoteproc: qcom: q6v5-pil: Add PDC reset for modem on SDM845 SoCs Sibi Sankar
2018-09-03 19:36 ` [PATCH v3 0/6] Add support for PDC Global " Bjorn Andersson
2018-10-04 18:27 6% ` Sibi Sankar
2018-09-01 22:23 8% [PATCH] arm64: dts: qcom: Add AOSS reset driver node for SDM845 Bjorn Andersson
2018-09-06 16:00 0% ` Doug Anderson
2018-09-03 11:52 [PATCH v3 0/2] Add ADSP PIL driver " Rohit kumar
2018-09-03 11:52 ` [PATCH v3 2/2] remoteproc: qcom: Introduce Non-PAS ADSP PIL driver Rohit kumar
2018-09-21 19:41 6% ` Sibi Sankar
2018-09-24 6:49 ` Rohit Kumar
2018-09-24 7:08 ` Rohit Kumar
2018-09-24 12:02 6% ` Sibi Sankar
2018-09-24 12:04 6% ` Sibi Sankar
2018-09-15 1:29 [PATCH AUTOSEL 4.18 01/92] binfmt_elf: Respect error return from `regset->active' Sasha Levin
2018-09-15 1:30 8% ` [PATCH AUTOSEL 4.18 74/92] remoteproc: qcom: q6v5-pil: fix modem hang on SDM845 after axis2 clk unvote Sasha Levin
2018-09-20 1:51 [PATCH] remoteproc: qcom: q6v5: Propagate EPROBE_DEFER Bjorn Andersson
2018-09-25 6:50 13% ` Sibi Sankar
2018-10-06 6:39 0% ` Bjorn Andersson
2018-09-20 17:22 [PATCH] remoteproc: qcom: pas: Add QCS404 remoteprocs Bjorn Andersson
2018-09-25 10:18 6% ` Sibi Sankar
2018-09-25 23:35 ` Bjorn Andersson
2018-09-26 15:48 6% ` Sibi Sankar
2018-09-24 11:07 [PATCH v4] remoteproc: qcom: Introduce Non-PAS ADSP PIL driver Rohit kumar
2018-09-24 12:08 14% ` Sibi Sankar
2018-09-24 11:49 2% [PATCH 4.18 000/235] 4.18.10-stable review Greg Kroah-Hartman
2018-09-24 11:53 8% ` [PATCH 4.18 217/235] remoteproc: qcom: q6v5-pil: fix modem hang on SDM845 after axis2 clk unvote Greg Kroah-Hartman
2018-09-25 8:06 [RFC PATCH] soc: qcom: rmtfs_mem: Control remoteproc from rmtfs_mem Bjorn Andersson
2018-09-25 17:29 ` Brian Norris
2018-09-30 15:28 6% ` Sibi Sankar
2018-09-27 19:03 [PATCH v2] remoteproc: qcom: pas: Add QCS404 remoteprocs Bjorn Andersson
2018-09-28 6:27 13% ` Sibi Sankar
2018-10-06 6:38 0% ` Bjorn Andersson
2018-09-30 15:56 16% [RFC PATCH v2] soc: qcom: rmtfs_mem: Control remoteproc from rmtfs_mem Sibi Sankar
2018-10-01 14:25 19% [PATCH] remoteproc: qcom: q6v5: Fix a race condition on fatal crash Sibi Sankar
2018-10-06 6:35 0% ` Bjorn Andersson
2018-10-09 2:08 [PATCH] remoteproc: qcom: q6v5-pil: add SCM probe dependency Brian Norris
2018-10-09 6:21 ` Bjorn Andersson
2018-10-09 17:02 ` Brian Norris
2018-10-09 17:21 6% ` Sibi Sankar
2018-10-09 16:23 14% [PATCH v4 0/5] Add coredump support for Q6v5 Modem remoteproc Sibi Sankar
2018-10-09 16:23 20% ` [PATCH v4 1/5] remoteproc: Introduce custom dump function for each remoteproc segment Sibi Sankar
2018-10-09 16:23 19% ` [PATCH v4 2/5] remoteproc: Add mechanism for custom dump function assignment Sibi Sankar
2018-10-09 16:23 15% ` [PATCH v4 3/5] remoteproc: qcom: q6v5-mss: Refactor mba load/unload sequence Sibi Sankar
2018-10-09 16:23 20% ` [PATCH v4 4/5] remoteproc: qcom: q6v5-mss: Add custom dump function for modem Sibi Sankar
2018-10-09 16:23 20% ` [PATCH v4 5/5] remoteproc: qcom: q6v5-mss: Register segments/dumpfn for coredump Sibi Sankar
2018-10-17 13:55 14% [PATCH v5 0/5] Add coredump support for Q6v5 Modem remoteproc Sibi Sankar
2018-10-17 13:55 20% ` [PATCH v5 1/5] remoteproc: Introduce custom dump function for each remoteproc segment Sibi Sankar
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