From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 73F1BC2BA19 for ; Thu, 23 Apr 2020 07:30:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 48E5A2076C for ; Thu, 23 Apr 2020 07:30:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726806AbgDWHaO convert rfc822-to-8bit (ORCPT ); Thu, 23 Apr 2020 03:30:14 -0400 Received: from mga05.intel.com ([192.55.52.43]:59180 "EHLO mga05.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725562AbgDWHaN (ORCPT ); Thu, 23 Apr 2020 03:30:13 -0400 IronPort-SDR: 07WQX89C5kGyXwLE+SUTFf1qUMmBv6yxzQpjLbGuS1YAEKvrjZxRRNlApqMxfoXENLAWZA4SOz TTdGGz1VU2eA== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Apr 2020 00:30:13 -0700 IronPort-SDR: 5nWklFsLj8V+HPKfgDgkg+qhYZpUR6WsZFxOaqMu8KKW2eEaKoS9dEfu8FUT6uBctg/FZkDkd9 qOtaavvisRbA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,306,1583222400"; d="scan'208";a="274148072" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by orsmga002.jf.intel.com with ESMTP; 23 Apr 2020 00:30:12 -0700 Received: from fmsmsx604.amr.corp.intel.com (10.18.126.84) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.439.0; Thu, 23 Apr 2020 00:30:02 -0700 Received: from fmsmsx604.amr.corp.intel.com (10.18.126.84) by fmsmsx604.amr.corp.intel.com (10.18.126.84) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Thu, 23 Apr 2020 00:29:59 -0700 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by fmsmsx604.amr.corp.intel.com (10.18.126.84) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.1713.5 via Frontend Transport; Thu, 23 Apr 2020 00:29:59 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.225]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.209]) with mapi id 14.03.0439.000; Thu, 23 Apr 2020 15:29:57 +0800 From: "Tian, Kevin" To: Jacob Pan , Lu Baolu , "iommu@lists.linux-foundation.org" , LKML , Joerg Roedel , David Woodhouse , Jean-Philippe Brucker , Eric Auger CC: "Liu, Yi L" , "Raj, Ashok" , "Alex Williamson" , Christoph Hellwig , Jonathan Cameron Subject: RE: [PATCH v12 2/8] iommu/vt-d: Use a helper function to skip agaw for SL Thread-Topic: [PATCH v12 2/8] iommu/vt-d: Use a helper function to skip agaw for SL Thread-Index: AQHWGA061s2Otz/cL0WDDwOKAajsVqiGUa+A Date: Thu, 23 Apr 2020 07:29:56 +0000 Message-ID: References: <1587495165-80096-1-git-send-email-jacob.jun.pan@linux.intel.com> <1587495165-80096-3-git-send-email-jacob.jun.pan@linux.intel.com> In-Reply-To: <1587495165-80096-3-git-send-email-jacob.jun.pan@linux.intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > From: Jacob Pan > Sent: Wednesday, April 22, 2020 2:53 AM > > An Intel iommu domain uses 5-level page table by default. If the > iommu that the domain tries to attach supports less page levels, > the top level page tables should be skipped. Add a helper to do > this so that it could be used in other places. > > Signed-off-by: Jacob Pan > Reviewed-by: Eric Auger > --- > drivers/iommu/intel-pasid.c | 33 +++++++++++++++++++++++---------- > 1 file changed, 23 insertions(+), 10 deletions(-) > > diff --git a/drivers/iommu/intel-pasid.c b/drivers/iommu/intel-pasid.c > index 22b30f10b396..d9cea3011b58 100644 > --- a/drivers/iommu/intel-pasid.c > +++ b/drivers/iommu/intel-pasid.c > @@ -500,6 +500,25 @@ int intel_pasid_setup_first_level(struct intel_iommu > *iommu, > } > > /* > + * Skip top levels of page tables for iommu which has less agaw > + * than default. Unnecessary for PT mode. > + */ > +static inline int iommu_skip_agaw(struct dmar_domain *domain, > + struct intel_iommu *iommu, > + struct dma_pte **pgd) > +{ > + int agaw; > + > + for (agaw = domain->agaw; agaw > iommu->agaw; agaw--) { > + *pgd = phys_to_virt(dma_pte_addr(*pgd)); > + if (!dma_pte_present(*pgd)) > + return -EINVAL; > + } > + > + return agaw; > +} > + > +/* > * Set up the scalable mode pasid entry for second only translation type. > */ > int intel_pasid_setup_second_level(struct intel_iommu *iommu, > @@ -522,17 +541,11 @@ int intel_pasid_setup_second_level(struct > intel_iommu *iommu, > return -EINVAL; > } > > - /* > - * Skip top levels of page tables for iommu which has less agaw > - * than default. Unnecessary for PT mode. > - */ > pgd = domain->pgd; > - for (agaw = domain->agaw; agaw > iommu->agaw; agaw--) { > - pgd = phys_to_virt(dma_pte_addr(pgd)); > - if (!dma_pte_present(pgd)) { > - dev_err(dev, "Invalid domain page table\n"); > - return -EINVAL; > - } > + agaw = iommu_skip_agaw(domain, iommu, &pgd); > + if (agaw < 0) { > + dev_err(dev, "Invalid domain page table\n"); > + return -EINVAL; > } > > pgd_val = virt_to_phys(pgd); > -- > 2.7.4 Reviewed-by: Kevin Tian